stats.txt revision 11731
111731Sjason@lowepower.com 211731Sjason@lowepower.com---------- Begin Simulation Statistics ---------- 311731Sjason@lowepower.comsim_seconds 0.000113 # Number of seconds simulated 411731Sjason@lowepower.comsim_ticks 113397000 # Number of ticks simulated 511731Sjason@lowepower.comfinal_tick 113397000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611731Sjason@lowepower.comsim_freq 1000000000000 # Frequency of simulated ticks 711731Sjason@lowepower.comhost_inst_rate 22733 # Simulator instruction rate (inst/s) 811731Sjason@lowepower.comhost_op_rate 22733 # Simulator op (including micro ops) rate (op/s) 911731Sjason@lowepower.comhost_tick_rate 11398414 # Simulator tick rate (ticks/s) 1011731Sjason@lowepower.comhost_mem_usage 246096 # Number of bytes of host memory used 1111731Sjason@lowepower.comhost_seconds 9.95 # Real time elapsed on the host 1211731Sjason@lowepower.comsim_insts 226159 # Number of instructions simulated 1311731Sjason@lowepower.comsim_ops 226159 # Number of ops (including micro ops) simulated 1411731Sjason@lowepower.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511731Sjason@lowepower.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611731Sjason@lowepower.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states 1711731Sjason@lowepower.comsystem.physmem.bytes_read::cpu.inst 65856 # Number of bytes read from this memory 1811731Sjason@lowepower.comsystem.physmem.bytes_read::cpu.data 19264 # Number of bytes read from this memory 1911731Sjason@lowepower.comsystem.physmem.bytes_read::total 85120 # Number of bytes read from this memory 2011731Sjason@lowepower.comsystem.physmem.bytes_inst_read::cpu.inst 65856 # Number of instructions bytes read from this memory 2111731Sjason@lowepower.comsystem.physmem.bytes_inst_read::total 65856 # Number of instructions bytes read from this memory 2211731Sjason@lowepower.comsystem.physmem.num_reads::cpu.inst 1029 # Number of read requests responded to by this memory 2311731Sjason@lowepower.comsystem.physmem.num_reads::cpu.data 301 # Number of read requests responded to by this memory 2411731Sjason@lowepower.comsystem.physmem.num_reads::total 1330 # Number of read requests responded to by this memory 2511731Sjason@lowepower.comsystem.physmem.bw_read::cpu.inst 580756105 # Total read bandwidth from this memory (bytes/s) 2611731Sjason@lowepower.comsystem.physmem.bw_read::cpu.data 169881037 # Total read bandwidth from this memory (bytes/s) 2711731Sjason@lowepower.comsystem.physmem.bw_read::total 750637142 # Total read bandwidth from this memory (bytes/s) 2811731Sjason@lowepower.comsystem.physmem.bw_inst_read::cpu.inst 580756105 # Instruction read bandwidth from this memory (bytes/s) 2911731Sjason@lowepower.comsystem.physmem.bw_inst_read::total 580756105 # Instruction read bandwidth from this memory (bytes/s) 3011731Sjason@lowepower.comsystem.physmem.bw_total::cpu.inst 580756105 # Total bandwidth to/from this memory (bytes/s) 3111731Sjason@lowepower.comsystem.physmem.bw_total::cpu.data 169881037 # Total bandwidth to/from this memory (bytes/s) 3211731Sjason@lowepower.comsystem.physmem.bw_total::total 750637142 # Total bandwidth to/from this memory (bytes/s) 3311731Sjason@lowepower.comsystem.physmem.readReqs 1330 # Number of read requests accepted 3411731Sjason@lowepower.comsystem.physmem.writeReqs 0 # Number of write requests accepted 3511731Sjason@lowepower.comsystem.physmem.readBursts 1330 # Number of DRAM read bursts, including those serviced by the write queue 3611731Sjason@lowepower.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 3711731Sjason@lowepower.comsystem.physmem.bytesReadDRAM 85120 # Total number of bytes read from DRAM 3811731Sjason@lowepower.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 3911731Sjason@lowepower.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 4011731Sjason@lowepower.comsystem.physmem.bytesReadSys 85120 # Total read bytes from the system interface side 4111731Sjason@lowepower.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 4211731Sjason@lowepower.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 4311731Sjason@lowepower.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 4411731Sjason@lowepower.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 4511731Sjason@lowepower.comsystem.physmem.perBankRdBursts::0 174 # Per bank write bursts 4611731Sjason@lowepower.comsystem.physmem.perBankRdBursts::1 18 # Per bank write bursts 4711731Sjason@lowepower.comsystem.physmem.perBankRdBursts::2 15 # Per bank write bursts 4811731Sjason@lowepower.comsystem.physmem.perBankRdBursts::3 82 # Per bank write bursts 4911731Sjason@lowepower.comsystem.physmem.perBankRdBursts::4 195 # Per bank write bursts 5011731Sjason@lowepower.comsystem.physmem.perBankRdBursts::5 254 # Per bank write bursts 5111731Sjason@lowepower.comsystem.physmem.perBankRdBursts::6 22 # Per bank write bursts 5211731Sjason@lowepower.comsystem.physmem.perBankRdBursts::7 4 # Per bank write bursts 5311731Sjason@lowepower.comsystem.physmem.perBankRdBursts::8 25 # Per bank write bursts 5411731Sjason@lowepower.comsystem.physmem.perBankRdBursts::9 103 # Per bank write bursts 5511731Sjason@lowepower.comsystem.physmem.perBankRdBursts::10 149 # Per bank write bursts 5611731Sjason@lowepower.comsystem.physmem.perBankRdBursts::11 145 # Per bank write bursts 5711731Sjason@lowepower.comsystem.physmem.perBankRdBursts::12 50 # Per bank write bursts 5811731Sjason@lowepower.comsystem.physmem.perBankRdBursts::13 51 # Per bank write bursts 5911731Sjason@lowepower.comsystem.physmem.perBankRdBursts::14 14 # Per bank write bursts 6011731Sjason@lowepower.comsystem.physmem.perBankRdBursts::15 29 # Per bank write bursts 6111731Sjason@lowepower.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 6211731Sjason@lowepower.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 6311731Sjason@lowepower.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 6411731Sjason@lowepower.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 6511731Sjason@lowepower.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 6611731Sjason@lowepower.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 6711731Sjason@lowepower.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 6811731Sjason@lowepower.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 6911731Sjason@lowepower.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 7011731Sjason@lowepower.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 7111731Sjason@lowepower.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 7211731Sjason@lowepower.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 7311731Sjason@lowepower.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 7411731Sjason@lowepower.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 7511731Sjason@lowepower.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 7611731Sjason@lowepower.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 7711731Sjason@lowepower.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 7811731Sjason@lowepower.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 7911731Sjason@lowepower.comsystem.physmem.totGap 113291000 # Total gap between requests 8011731Sjason@lowepower.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 8111731Sjason@lowepower.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 8211731Sjason@lowepower.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 8311731Sjason@lowepower.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 8411731Sjason@lowepower.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 8511731Sjason@lowepower.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 8611731Sjason@lowepower.comsystem.physmem.readPktSize::6 1330 # Read request sizes (log2) 8711731Sjason@lowepower.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 8811731Sjason@lowepower.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 8911731Sjason@lowepower.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 9011731Sjason@lowepower.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 9111731Sjason@lowepower.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 9211731Sjason@lowepower.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 9311731Sjason@lowepower.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9411731Sjason@lowepower.comsystem.physmem.rdQLenPdf::0 807 # What read queue length does an incoming req see 9511731Sjason@lowepower.comsystem.physmem.rdQLenPdf::1 369 # What read queue length does an incoming req see 9611731Sjason@lowepower.comsystem.physmem.rdQLenPdf::2 107 # What read queue length does an incoming req see 9711731Sjason@lowepower.comsystem.physmem.rdQLenPdf::3 43 # What read queue length does an incoming req see 9811731Sjason@lowepower.comsystem.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see 9911731Sjason@lowepower.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 10011731Sjason@lowepower.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 10111731Sjason@lowepower.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 10211731Sjason@lowepower.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 10311731Sjason@lowepower.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 10411731Sjason@lowepower.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 10511731Sjason@lowepower.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 10611731Sjason@lowepower.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 10711731Sjason@lowepower.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 10811731Sjason@lowepower.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 10911731Sjason@lowepower.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 11011731Sjason@lowepower.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 11111731Sjason@lowepower.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 11211731Sjason@lowepower.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 11311731Sjason@lowepower.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 11411731Sjason@lowepower.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 11511731Sjason@lowepower.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 11611731Sjason@lowepower.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 11711731Sjason@lowepower.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 11811731Sjason@lowepower.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 11911731Sjason@lowepower.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 12011731Sjason@lowepower.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 12111731Sjason@lowepower.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 12211731Sjason@lowepower.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 12311731Sjason@lowepower.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 12411731Sjason@lowepower.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 12511731Sjason@lowepower.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 12611731Sjason@lowepower.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 12711731Sjason@lowepower.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 12811731Sjason@lowepower.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 12911731Sjason@lowepower.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 13011731Sjason@lowepower.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 13111731Sjason@lowepower.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 13211731Sjason@lowepower.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 13311731Sjason@lowepower.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 13411731Sjason@lowepower.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 13511731Sjason@lowepower.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 13611731Sjason@lowepower.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 13711731Sjason@lowepower.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 13811731Sjason@lowepower.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 13911731Sjason@lowepower.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 14011731Sjason@lowepower.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 14111731Sjason@lowepower.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 14211731Sjason@lowepower.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 14311731Sjason@lowepower.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 14411731Sjason@lowepower.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 14511731Sjason@lowepower.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 14611731Sjason@lowepower.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 14711731Sjason@lowepower.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 14811731Sjason@lowepower.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 14911731Sjason@lowepower.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 15011731Sjason@lowepower.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 15111731Sjason@lowepower.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 15211731Sjason@lowepower.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 15311731Sjason@lowepower.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 15411731Sjason@lowepower.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 15511731Sjason@lowepower.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 15611731Sjason@lowepower.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 15711731Sjason@lowepower.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 15811731Sjason@lowepower.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 15911731Sjason@lowepower.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 16011731Sjason@lowepower.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16111731Sjason@lowepower.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16211731Sjason@lowepower.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16311731Sjason@lowepower.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16411731Sjason@lowepower.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16511731Sjason@lowepower.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16611731Sjason@lowepower.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 16711731Sjason@lowepower.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 16811731Sjason@lowepower.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 16911731Sjason@lowepower.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 17011731Sjason@lowepower.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17111731Sjason@lowepower.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17211731Sjason@lowepower.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17311731Sjason@lowepower.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17411731Sjason@lowepower.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17511731Sjason@lowepower.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17611731Sjason@lowepower.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 17711731Sjason@lowepower.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 17811731Sjason@lowepower.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 17911731Sjason@lowepower.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 18011731Sjason@lowepower.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18111731Sjason@lowepower.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18211731Sjason@lowepower.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18311731Sjason@lowepower.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18411731Sjason@lowepower.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18511731Sjason@lowepower.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18611731Sjason@lowepower.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 18711731Sjason@lowepower.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 18811731Sjason@lowepower.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 18911731Sjason@lowepower.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 19011731Sjason@lowepower.comsystem.physmem.bytesPerActivate::samples 210 # Bytes accessed per row activation 19111731Sjason@lowepower.comsystem.physmem.bytesPerActivate::mean 393.752381 # Bytes accessed per row activation 19211731Sjason@lowepower.comsystem.physmem.bytesPerActivate::gmean 254.589157 # Bytes accessed per row activation 19311731Sjason@lowepower.comsystem.physmem.bytesPerActivate::stdev 342.600882 # Bytes accessed per row activation 19411731Sjason@lowepower.comsystem.physmem.bytesPerActivate::0-127 48 22.86% 22.86% # Bytes accessed per row activation 19511731Sjason@lowepower.comsystem.physmem.bytesPerActivate::128-255 44 20.95% 43.81% # Bytes accessed per row activation 19611731Sjason@lowepower.comsystem.physmem.bytesPerActivate::256-383 35 16.67% 60.48% # Bytes accessed per row activation 19711731Sjason@lowepower.comsystem.physmem.bytesPerActivate::384-511 18 8.57% 69.05% # Bytes accessed per row activation 19811731Sjason@lowepower.comsystem.physmem.bytesPerActivate::512-639 13 6.19% 75.24% # Bytes accessed per row activation 19911731Sjason@lowepower.comsystem.physmem.bytesPerActivate::640-767 10 4.76% 80.00% # Bytes accessed per row activation 20011731Sjason@lowepower.comsystem.physmem.bytesPerActivate::768-895 5 2.38% 82.38% # Bytes accessed per row activation 20111731Sjason@lowepower.comsystem.physmem.bytesPerActivate::896-1023 5 2.38% 84.76% # Bytes accessed per row activation 20211731Sjason@lowepower.comsystem.physmem.bytesPerActivate::1024-1151 32 15.24% 100.00% # Bytes accessed per row activation 20311731Sjason@lowepower.comsystem.physmem.bytesPerActivate::total 210 # Bytes accessed per row activation 20411731Sjason@lowepower.comsystem.physmem.totQLat 16749000 # Total ticks spent queuing 20511731Sjason@lowepower.comsystem.physmem.totMemAccLat 41686500 # Total ticks spent from burst creation until serviced by the DRAM 20611731Sjason@lowepower.comsystem.physmem.totBusLat 6650000 # Total ticks spent in databus transfers 20711731Sjason@lowepower.comsystem.physmem.avgQLat 12593.23 # Average queueing delay per DRAM burst 20811731Sjason@lowepower.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 20911731Sjason@lowepower.comsystem.physmem.avgMemAccLat 31343.23 # Average memory access latency per DRAM burst 21011731Sjason@lowepower.comsystem.physmem.avgRdBW 750.64 # Average DRAM read bandwidth in MiByte/s 21111731Sjason@lowepower.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21211731Sjason@lowepower.comsystem.physmem.avgRdBWSys 750.64 # Average system read bandwidth in MiByte/s 21311731Sjason@lowepower.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 21411731Sjason@lowepower.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21511731Sjason@lowepower.comsystem.physmem.busUtil 5.86 # Data bus utilization in percentage 21611731Sjason@lowepower.comsystem.physmem.busUtilRead 5.86 # Data bus utilization in percentage for reads 21711731Sjason@lowepower.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 21811731Sjason@lowepower.comsystem.physmem.avgRdQLen 1.57 # Average read queue length when enqueuing 21911731Sjason@lowepower.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 22011731Sjason@lowepower.comsystem.physmem.readRowHits 1108 # Number of row buffer hits during reads 22111731Sjason@lowepower.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 22211731Sjason@lowepower.comsystem.physmem.readRowHitRate 83.31 # Row buffer hit rate for reads 22311731Sjason@lowepower.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22411731Sjason@lowepower.comsystem.physmem.avgGap 85181.20 # Average gap between requests 22511731Sjason@lowepower.comsystem.physmem.pageHitRate 83.31 # Row buffer hit rate, read and write combined 22611731Sjason@lowepower.comsystem.physmem_0.actEnergy 763980 # Energy for activate commands per rank (pJ) 22711731Sjason@lowepower.comsystem.physmem_0.preEnergy 387090 # Energy for precharge commands per rank (pJ) 22811731Sjason@lowepower.comsystem.physmem_0.readEnergy 5454960 # Energy for read commands per rank (pJ) 22911731Sjason@lowepower.comsystem.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 23011731Sjason@lowepower.comsystem.physmem_0.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) 23111731Sjason@lowepower.comsystem.physmem_0.actBackEnergy 9828510 # Energy for active background per rank (pJ) 23211731Sjason@lowepower.comsystem.physmem_0.preBackEnergy 194400 # Energy for precharge background per rank (pJ) 23311731Sjason@lowepower.comsystem.physmem_0.actPowerDownEnergy 40216350 # Energy for active power-down per rank (pJ) 23411731Sjason@lowepower.comsystem.physmem_0.prePowerDownEnergy 1207200 # Energy for precharge power-down per rank (pJ) 23511731Sjason@lowepower.comsystem.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 23611731Sjason@lowepower.comsystem.physmem_0.totalEnergy 66657450 # Total energy per rank (pJ) 23711731Sjason@lowepower.comsystem.physmem_0.averagePower 587.821160 # Core power per rank (mW) 23811731Sjason@lowepower.comsystem.physmem_0.totalIdleTime 91041000 # Total Idle time Per DRAM Rank 23911731Sjason@lowepower.comsystem.physmem_0.memoryStateTime::IDLE 89500 # Time in different power states 24011731Sjason@lowepower.comsystem.physmem_0.memoryStateTime::REF 3640000 # Time in different power states 24111731Sjason@lowepower.comsystem.physmem_0.memoryStateTime::SREF 0 # Time in different power states 24211731Sjason@lowepower.comsystem.physmem_0.memoryStateTime::PRE_PDN 3144500 # Time in different power states 24311731Sjason@lowepower.comsystem.physmem_0.memoryStateTime::ACT 18326750 # Time in different power states 24411731Sjason@lowepower.comsystem.physmem_0.memoryStateTime::ACT_PDN 88196250 # Time in different power states 24511731Sjason@lowepower.comsystem.physmem_1.actEnergy 821100 # Energy for activate commands per rank (pJ) 24611731Sjason@lowepower.comsystem.physmem_1.preEnergy 409860 # Energy for precharge commands per rank (pJ) 24711731Sjason@lowepower.comsystem.physmem_1.readEnergy 4041240 # Energy for read commands per rank (pJ) 24811731Sjason@lowepower.comsystem.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 24911731Sjason@lowepower.comsystem.physmem_1.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) 25011731Sjason@lowepower.comsystem.physmem_1.actBackEnergy 7868280 # Energy for active background per rank (pJ) 25111731Sjason@lowepower.comsystem.physmem_1.preBackEnergy 220800 # Energy for precharge background per rank (pJ) 25211731Sjason@lowepower.comsystem.physmem_1.actPowerDownEnergy 41251470 # Energy for active power-down per rank (pJ) 25311731Sjason@lowepower.comsystem.physmem_1.prePowerDownEnergy 1959840 # Energy for precharge power-down per rank (pJ) 25411731Sjason@lowepower.comsystem.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 25511731Sjason@lowepower.comsystem.physmem_1.totalEnergy 65177550 # Total energy per rank (pJ) 25611731Sjason@lowepower.comsystem.physmem_1.averagePower 574.770608 # Core power per rank (mW) 25711731Sjason@lowepower.comsystem.physmem_1.totalIdleTime 95505000 # Total Idle time Per DRAM Rank 25811731Sjason@lowepower.comsystem.physmem_1.memoryStateTime::IDLE 174500 # Time in different power states 25911731Sjason@lowepower.comsystem.physmem_1.memoryStateTime::REF 3640000 # Time in different power states 26011731Sjason@lowepower.comsystem.physmem_1.memoryStateTime::SREF 0 # Time in different power states 26111731Sjason@lowepower.comsystem.physmem_1.memoryStateTime::PRE_PDN 5102500 # Time in different power states 26211731Sjason@lowepower.comsystem.physmem_1.memoryStateTime::ACT 14007750 # Time in different power states 26311731Sjason@lowepower.comsystem.physmem_1.memoryStateTime::ACT_PDN 90472250 # Time in different power states 26411731Sjason@lowepower.comsystem.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states 26511731Sjason@lowepower.comsystem.cpu.branchPred.lookups 78040 # Number of BP lookups 26611731Sjason@lowepower.comsystem.cpu.branchPred.condPredicted 47825 # Number of conditional branches predicted 26711731Sjason@lowepower.comsystem.cpu.branchPred.condIncorrect 4968 # Number of conditional branches incorrect 26811731Sjason@lowepower.comsystem.cpu.branchPred.BTBLookups 59525 # Number of BTB lookups 26911731Sjason@lowepower.comsystem.cpu.branchPred.BTBHits 36023 # Number of BTB hits 27011731Sjason@lowepower.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 27111731Sjason@lowepower.comsystem.cpu.branchPred.BTBHitPct 60.517430 # BTB Hit Percentage 27211731Sjason@lowepower.comsystem.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. 27311731Sjason@lowepower.comsystem.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. 27411731Sjason@lowepower.comsystem.cpu.branchPred.indirectLookups 14832 # Number of indirect predictor lookups. 27511731Sjason@lowepower.comsystem.cpu.branchPred.indirectHits 6672 # Number of indirect target hits. 27611731Sjason@lowepower.comsystem.cpu.branchPred.indirectMisses 8160 # Number of indirect misses. 27711731Sjason@lowepower.comsystem.cpu.branchPredindirectMispredicted 2577 # Number of mispredicted indirect branches. 27811731Sjason@lowepower.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 27911731Sjason@lowepower.comsystem.cpu.dtb.read_hits 0 # DTB read hits 28011731Sjason@lowepower.comsystem.cpu.dtb.read_misses 0 # DTB read misses 28111731Sjason@lowepower.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 28211731Sjason@lowepower.comsystem.cpu.dtb.write_hits 0 # DTB write hits 28311731Sjason@lowepower.comsystem.cpu.dtb.write_misses 0 # DTB write misses 28411731Sjason@lowepower.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 28511731Sjason@lowepower.comsystem.cpu.dtb.hits 0 # DTB hits 28611731Sjason@lowepower.comsystem.cpu.dtb.misses 0 # DTB misses 28711731Sjason@lowepower.comsystem.cpu.dtb.accesses 0 # DTB accesses 28811731Sjason@lowepower.comsystem.cpu.itb.read_hits 0 # DTB read hits 28911731Sjason@lowepower.comsystem.cpu.itb.read_misses 0 # DTB read misses 29011731Sjason@lowepower.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 29111731Sjason@lowepower.comsystem.cpu.itb.write_hits 0 # DTB write hits 29211731Sjason@lowepower.comsystem.cpu.itb.write_misses 0 # DTB write misses 29311731Sjason@lowepower.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 29411731Sjason@lowepower.comsystem.cpu.itb.hits 0 # DTB hits 29511731Sjason@lowepower.comsystem.cpu.itb.misses 0 # DTB misses 29611731Sjason@lowepower.comsystem.cpu.itb.accesses 0 # DTB accesses 29711731Sjason@lowepower.comsystem.cpu.workload.num_syscalls 115 # Number of system calls 29811731Sjason@lowepower.comsystem.cpu.pwrStateResidencyTicks::ON 113397000 # Cumulative time (in ticks) in various power states 29911731Sjason@lowepower.comsystem.cpu.numCycles 226795 # number of cpu cycles simulated 30011731Sjason@lowepower.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 30111731Sjason@lowepower.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 30211731Sjason@lowepower.comsystem.cpu.fetch.icacheStallCycles 73757 # Number of cycles fetch is stalled on an Icache miss 30311731Sjason@lowepower.comsystem.cpu.fetch.Insts 336548 # Number of instructions fetch has processed 30411731Sjason@lowepower.comsystem.cpu.fetch.Branches 78040 # Number of branches that fetch encountered 30511731Sjason@lowepower.comsystem.cpu.fetch.predictedBranches 42695 # Number of branches that fetch has predicted taken 30611731Sjason@lowepower.comsystem.cpu.fetch.Cycles 87262 # Number of cycles fetch has run and was not squashing or blocked 30711731Sjason@lowepower.comsystem.cpu.fetch.SquashCycles 10228 # Number of cycles fetch has spent squashing 30811731Sjason@lowepower.comsystem.cpu.fetch.MiscStallCycles 401 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 30911731Sjason@lowepower.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 192 # Number of stall cycles due to full MSHR 31011731Sjason@lowepower.comsystem.cpu.fetch.CacheLines 60631 # Number of cache lines fetched 31111731Sjason@lowepower.comsystem.cpu.fetch.IcacheSquashes 2398 # Number of outstanding Icache misses that were squashed 31211731Sjason@lowepower.comsystem.cpu.fetch.rateDist::samples 166726 # Number of instructions fetched each cycle (Total) 31311731Sjason@lowepower.comsystem.cpu.fetch.rateDist::mean 2.018569 # Number of instructions fetched each cycle (Total) 31411731Sjason@lowepower.comsystem.cpu.fetch.rateDist::stdev 2.822541 # Number of instructions fetched each cycle (Total) 31511731Sjason@lowepower.comsystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 31611731Sjason@lowepower.comsystem.cpu.fetch.rateDist::0 89937 53.94% 53.94% # Number of instructions fetched each cycle (Total) 31711731Sjason@lowepower.comsystem.cpu.fetch.rateDist::1 11784 7.07% 61.01% # Number of instructions fetched each cycle (Total) 31811731Sjason@lowepower.comsystem.cpu.fetch.rateDist::2 13843 8.30% 69.31% # Number of instructions fetched each cycle (Total) 31911731Sjason@lowepower.comsystem.cpu.fetch.rateDist::3 11668 7.00% 76.31% # Number of instructions fetched each cycle (Total) 32011731Sjason@lowepower.comsystem.cpu.fetch.rateDist::4 5791 3.47% 79.79% # Number of instructions fetched each cycle (Total) 32111731Sjason@lowepower.comsystem.cpu.fetch.rateDist::5 6797 4.08% 83.86% # Number of instructions fetched each cycle (Total) 32211731Sjason@lowepower.comsystem.cpu.fetch.rateDist::6 2856 1.71% 85.58% # Number of instructions fetched each cycle (Total) 32311731Sjason@lowepower.comsystem.cpu.fetch.rateDist::7 4611 2.77% 88.34% # Number of instructions fetched each cycle (Total) 32411731Sjason@lowepower.comsystem.cpu.fetch.rateDist::8 19439 11.66% 100.00% # Number of instructions fetched each cycle (Total) 32511731Sjason@lowepower.comsystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 32611731Sjason@lowepower.comsystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 32711731Sjason@lowepower.comsystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 32811731Sjason@lowepower.comsystem.cpu.fetch.rateDist::total 166726 # Number of instructions fetched each cycle (Total) 32911731Sjason@lowepower.comsystem.cpu.fetch.branchRate 0.344099 # Number of branch fetches per cycle 33011731Sjason@lowepower.comsystem.cpu.fetch.rate 1.483930 # Number of inst fetches per cycle 33111731Sjason@lowepower.comsystem.cpu.decode.IdleCycles 72653 # Number of cycles decode is idle 33211731Sjason@lowepower.comsystem.cpu.decode.BlockedCycles 18351 # Number of cycles decode is blocked 33311731Sjason@lowepower.comsystem.cpu.decode.RunCycles 70165 # Number of cycles decode is running 33411731Sjason@lowepower.comsystem.cpu.decode.UnblockCycles 1269 # Number of cycles decode is unblocking 33511731Sjason@lowepower.comsystem.cpu.decode.SquashCycles 4288 # Number of cycles decode is squashing 33611731Sjason@lowepower.comsystem.cpu.decode.BranchResolved 13538 # Number of times decode resolved a branch 33711731Sjason@lowepower.comsystem.cpu.decode.BranchMispred 899 # Number of times decode detected a branch misprediction 33811731Sjason@lowepower.comsystem.cpu.decode.DecodedInsts 310274 # Number of instructions handled by decode 33911731Sjason@lowepower.comsystem.cpu.decode.SquashedInsts 2536 # Number of squashed instructions handled by decode 34011731Sjason@lowepower.comsystem.cpu.rename.SquashCycles 4288 # Number of cycles rename is squashing 34111731Sjason@lowepower.comsystem.cpu.rename.IdleCycles 75144 # Number of cycles rename is idle 34211731Sjason@lowepower.comsystem.cpu.rename.BlockCycles 7711 # Number of cycles rename is blocking 34311731Sjason@lowepower.comsystem.cpu.rename.serializeStallCycles 3158 # count of cycles rename stalled for serializing inst 34411731Sjason@lowepower.comsystem.cpu.rename.RunCycles 68795 # Number of cycles rename is running 34511731Sjason@lowepower.comsystem.cpu.rename.UnblockCycles 7630 # Number of cycles rename is unblocking 34611731Sjason@lowepower.comsystem.cpu.rename.RenamedInsts 298982 # Number of instructions processed by rename 34711731Sjason@lowepower.comsystem.cpu.rename.ROBFullEvents 168 # Number of times rename has blocked due to ROB full 34811731Sjason@lowepower.comsystem.cpu.rename.IQFullEvents 64 # Number of times rename has blocked due to IQ full 34911731Sjason@lowepower.comsystem.cpu.rename.LQFullEvents 782 # Number of times rename has blocked due to LQ full 35011731Sjason@lowepower.comsystem.cpu.rename.SQFullEvents 6500 # Number of times rename has blocked due to SQ full 35111731Sjason@lowepower.comsystem.cpu.rename.RenamedOperands 208109 # Number of destination operands rename has renamed 35211731Sjason@lowepower.comsystem.cpu.rename.RenameLookups 389749 # Number of register rename lookups that rename has made 35311731Sjason@lowepower.comsystem.cpu.rename.int_rename_lookups 387389 # Number of integer rename lookups 35411731Sjason@lowepower.comsystem.cpu.rename.fp_rename_lookups 2360 # Number of floating rename lookups 35511731Sjason@lowepower.comsystem.cpu.rename.CommittedMaps 155141 # Number of HB maps that are committed 35611731Sjason@lowepower.comsystem.cpu.rename.UndoneMaps 52968 # Number of HB maps that are undone due to squashing 35711731Sjason@lowepower.comsystem.cpu.rename.serializingInsts 133 # count of serializing insts renamed 35811731Sjason@lowepower.comsystem.cpu.rename.tempSerializingInsts 133 # count of temporary serializing insts renamed 35911731Sjason@lowepower.comsystem.cpu.rename.skidInsts 3030 # count of insts added to the skid buffer 36011731Sjason@lowepower.comsystem.cpu.memDep0.insertedLoads 62164 # Number of loads inserted to the mem dependence unit. 36111731Sjason@lowepower.comsystem.cpu.memDep0.insertedStores 43440 # Number of stores inserted to the mem dependence unit. 36211731Sjason@lowepower.comsystem.cpu.memDep0.conflictingLoads 1172 # Number of conflicting loads. 36311731Sjason@lowepower.comsystem.cpu.memDep0.conflictingStores 335 # Number of conflicting stores. 36411731Sjason@lowepower.comsystem.cpu.iq.iqInstsAdded 273555 # Number of instructions added to the IQ (excludes non-spec) 36511731Sjason@lowepower.comsystem.cpu.iq.iqNonSpecInstsAdded 154 # Number of non-speculative instructions added to the IQ 36611731Sjason@lowepower.comsystem.cpu.iq.iqInstsIssued 261697 # Number of instructions issued 36711731Sjason@lowepower.comsystem.cpu.iq.iqSquashedInstsIssued 610 # Number of squashed instructions issued 36811731Sjason@lowepower.comsystem.cpu.iq.iqSquashedInstsExamined 47545 # Number of squashed instructions iterated over during squash; mainly for profiling 36911731Sjason@lowepower.comsystem.cpu.iq.iqSquashedOperandsExamined 26182 # Number of squashed operands that are examined and possibly removed from graph 37011731Sjason@lowepower.comsystem.cpu.iq.iqSquashedNonSpecRemoved 33 # Number of squashed non-spec instructions that were removed 37111731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::samples 166726 # Number of insts issued each cycle 37211731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::mean 1.569623 # Number of insts issued each cycle 37311731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::stdev 1.886679 # Number of insts issued each cycle 37411731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 37511731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::0 67362 40.40% 40.40% # Number of insts issued each cycle 37611731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::1 36208 21.72% 62.12% # Number of insts issued each cycle 37711731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::2 23951 14.37% 76.49% # Number of insts issued each cycle 37811731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::3 10817 6.49% 82.97% # Number of insts issued each cycle 37911731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::4 10352 6.21% 89.18% # Number of insts issued each cycle 38011731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::5 8029 4.82% 94.00% # Number of insts issued each cycle 38111731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::6 7579 4.55% 98.54% # Number of insts issued each cycle 38211731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::7 1315 0.79% 99.33% # Number of insts issued each cycle 38311731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::8 1113 0.67% 100.00% # Number of insts issued each cycle 38411731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 38511731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 38611731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 38711731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::total 166726 # Number of insts issued each cycle 38811731Sjason@lowepower.comsystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 38911731Sjason@lowepower.comsystem.cpu.iq.fu_full::IntAlu 704 10.43% 10.43% # attempts to use FU when none available 39011731Sjason@lowepower.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 10.43% # attempts to use FU when none available 39111731Sjason@lowepower.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 10.43% # attempts to use FU when none available 39211731Sjason@lowepower.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 10.43% # attempts to use FU when none available 39311731Sjason@lowepower.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 10.43% # attempts to use FU when none available 39411731Sjason@lowepower.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 10.43% # attempts to use FU when none available 39511731Sjason@lowepower.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 10.43% # attempts to use FU when none available 39611731Sjason@lowepower.comsystem.cpu.iq.fu_full::FloatMultAcc 0 0.00% 10.43% # attempts to use FU when none available 39711731Sjason@lowepower.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 10.43% # attempts to use FU when none available 39811731Sjason@lowepower.comsystem.cpu.iq.fu_full::FloatMisc 0 0.00% 10.43% # attempts to use FU when none available 39911731Sjason@lowepower.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.43% # attempts to use FU when none available 40011731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 10.43% # attempts to use FU when none available 40111731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.43% # attempts to use FU when none available 40211731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 10.43% # attempts to use FU when none available 40311731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 10.43% # attempts to use FU when none available 40411731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 10.43% # attempts to use FU when none available 40511731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 10.43% # attempts to use FU when none available 40611731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 10.43% # attempts to use FU when none available 40711731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.43% # attempts to use FU when none available 40811731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 10.43% # attempts to use FU when none available 40911731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.43% # attempts to use FU when none available 41011731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.43% # attempts to use FU when none available 41111731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.43% # attempts to use FU when none available 41211731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.43% # attempts to use FU when none available 41311731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.43% # attempts to use FU when none available 41411731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.43% # attempts to use FU when none available 41511731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.43% # attempts to use FU when none available 41611731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.43% # attempts to use FU when none available 41711731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.43% # attempts to use FU when none available 41811731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.43% # attempts to use FU when none available 41911731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.43% # attempts to use FU when none available 42011731Sjason@lowepower.comsystem.cpu.iq.fu_full::MemRead 2989 44.27% 54.69% # attempts to use FU when none available 42111731Sjason@lowepower.comsystem.cpu.iq.fu_full::MemWrite 2970 43.99% 98.68% # attempts to use FU when none available 42211731Sjason@lowepower.comsystem.cpu.iq.fu_full::FloatMemRead 88 1.30% 99.99% # attempts to use FU when none available 42311731Sjason@lowepower.comsystem.cpu.iq.fu_full::FloatMemWrite 1 0.01% 100.00% # attempts to use FU when none available 42411731Sjason@lowepower.comsystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 42511731Sjason@lowepower.comsystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 42611731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::No_OpClass 117 0.04% 0.04% # Type of FU issued 42711731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::IntAlu 159679 61.02% 61.06% # Type of FU issued 42811731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::IntMult 326 0.12% 61.19% # Type of FU issued 42911731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::IntDiv 44 0.02% 61.20% # Type of FU issued 43011731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatAdd 172 0.07% 61.27% # Type of FU issued 43111731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatCmp 120 0.05% 61.31% # Type of FU issued 43211731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatCvt 58 0.02% 61.34% # Type of FU issued 43311731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatMult 30 0.01% 61.35% # Type of FU issued 43411731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 61.35% # Type of FU issued 43511731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatDiv 12 0.00% 61.35% # Type of FU issued 43611731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatMisc 0 0.00% 61.35% # Type of FU issued 43711731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatSqrt 5 0.00% 61.35% # Type of FU issued 43811731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.35% # Type of FU issued 43911731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.35% # Type of FU issued 44011731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.35% # Type of FU issued 44111731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.35% # Type of FU issued 44211731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.35% # Type of FU issued 44311731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.35% # Type of FU issued 44411731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.35% # Type of FU issued 44511731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.35% # Type of FU issued 44611731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.35% # Type of FU issued 44711731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.35% # Type of FU issued 44811731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.35% # Type of FU issued 44911731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.35% # Type of FU issued 45011731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.35% # Type of FU issued 45111731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.35% # Type of FU issued 45211731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.35% # Type of FU issued 45311731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.35% # Type of FU issued 45411731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.35% # Type of FU issued 45511731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.35% # Type of FU issued 45611731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.35% # Type of FU issued 45711731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.35% # Type of FU issued 45811731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::MemRead 59286 22.65% 84.01% # Type of FU issued 45911731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::MemWrite 40948 15.65% 99.66% # Type of FU issued 46011731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatMemRead 721 0.28% 99.93% # Type of FU issued 46111731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatMemWrite 179 0.07% 100.00% # Type of FU issued 46211731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 46311731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 46411731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::total 261697 # Type of FU issued 46511731Sjason@lowepower.comsystem.cpu.iq.rate 1.153892 # Inst issue rate 46611731Sjason@lowepower.comsystem.cpu.iq.fu_busy_cnt 6752 # FU busy when requested 46711731Sjason@lowepower.comsystem.cpu.iq.fu_busy_rate 0.025801 # FU busy rate (busy events/executed inst) 46811731Sjason@lowepower.comsystem.cpu.iq.int_inst_queue_reads 694798 # Number of integer instruction queue reads 46911731Sjason@lowepower.comsystem.cpu.iq.int_inst_queue_writes 318360 # Number of integer instruction queue writes 47011731Sjason@lowepower.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 249994 # Number of integer instruction queue wakeup accesses 47111731Sjason@lowepower.comsystem.cpu.iq.fp_inst_queue_reads 2684 # Number of floating instruction queue reads 47211731Sjason@lowepower.comsystem.cpu.iq.fp_inst_queue_writes 2938 # Number of floating instruction queue writes 47311731Sjason@lowepower.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 1006 # Number of floating instruction queue wakeup accesses 47411731Sjason@lowepower.comsystem.cpu.iq.int_alu_accesses 266946 # Number of integer alu accesses 47511731Sjason@lowepower.comsystem.cpu.iq.fp_alu_accesses 1386 # Number of floating point alu accesses 47611731Sjason@lowepower.comsystem.cpu.iew.lsq.thread0.forwLoads 5628 # Number of loads that had data forwarded from stores 47711731Sjason@lowepower.comsystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 47811731Sjason@lowepower.comsystem.cpu.iew.lsq.thread0.squashedLoads 10453 # Number of loads squashed 47911731Sjason@lowepower.comsystem.cpu.iew.lsq.thread0.ignoredResponses 28 # Number of memory responses ignored because the instruction is squashed 48011731Sjason@lowepower.comsystem.cpu.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations 48111731Sjason@lowepower.comsystem.cpu.iew.lsq.thread0.squashedStores 6211 # Number of stores squashed 48211731Sjason@lowepower.comsystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 48311731Sjason@lowepower.comsystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 48411731Sjason@lowepower.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 10 # Number of loads that were rescheduled 48511731Sjason@lowepower.comsystem.cpu.iew.lsq.thread0.cacheBlocked 117 # Number of times an access to memory failed due to the cache being blocked 48611731Sjason@lowepower.comsystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 48711731Sjason@lowepower.comsystem.cpu.iew.iewSquashCycles 4288 # Number of cycles IEW is squashing 48811731Sjason@lowepower.comsystem.cpu.iew.iewBlockCycles 4913 # Number of cycles IEW is blocking 48911731Sjason@lowepower.comsystem.cpu.iew.iewUnblockCycles 272 # Number of cycles IEW is unblocking 49011731Sjason@lowepower.comsystem.cpu.iew.iewDispatchedInsts 273705 # Number of instructions dispatched to IQ 49111731Sjason@lowepower.comsystem.cpu.iew.iewDispSquashedInsts 3278 # Number of squashed instructions skipped by dispatch 49211731Sjason@lowepower.comsystem.cpu.iew.iewDispLoadInsts 62164 # Number of dispatched load instructions 49311731Sjason@lowepower.comsystem.cpu.iew.iewDispStoreInsts 43440 # Number of dispatched store instructions 49411731Sjason@lowepower.comsystem.cpu.iew.iewDispNonSpecInsts 150 # Number of dispatched non-speculative instructions 49511731Sjason@lowepower.comsystem.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall 49611731Sjason@lowepower.comsystem.cpu.iew.iewLSQFullEvents 265 # Number of times the LSQ has become full, causing a stall 49711731Sjason@lowepower.comsystem.cpu.iew.memOrderViolationEvents 40 # Number of memory order violations 49811731Sjason@lowepower.comsystem.cpu.iew.predictedTakenIncorrect 1281 # Number of branches that were predicted taken incorrectly 49911731Sjason@lowepower.comsystem.cpu.iew.predictedNotTakenIncorrect 3469 # Number of branches that were predicted not taken incorrectly 50011731Sjason@lowepower.comsystem.cpu.iew.branchMispredicts 4750 # Number of branch mispredicts detected at execute 50111731Sjason@lowepower.comsystem.cpu.iew.iewExecutedInsts 254156 # Number of executed instructions 50211731Sjason@lowepower.comsystem.cpu.iew.iewExecLoadInsts 58399 # Number of load instructions executed 50311731Sjason@lowepower.comsystem.cpu.iew.iewExecSquashedInsts 7541 # Number of squashed instructions skipped in execute 50411731Sjason@lowepower.comsystem.cpu.iew.exec_swp 0 # number of swp insts executed 50511731Sjason@lowepower.comsystem.cpu.iew.exec_nop 0 # number of nop insts executed 50611731Sjason@lowepower.comsystem.cpu.iew.exec_refs 98174 # number of memory reference insts executed 50711731Sjason@lowepower.comsystem.cpu.iew.exec_branches 57098 # Number of branches executed 50811731Sjason@lowepower.comsystem.cpu.iew.exec_stores 39775 # Number of stores executed 50911731Sjason@lowepower.comsystem.cpu.iew.exec_rate 1.120642 # Inst execution rate 51011731Sjason@lowepower.comsystem.cpu.iew.wb_sent 252228 # cumulative count of insts sent to commit 51111731Sjason@lowepower.comsystem.cpu.iew.wb_count 251000 # cumulative count of insts written-back 51211731Sjason@lowepower.comsystem.cpu.iew.wb_producers 95690 # num instructions producing a value 51311731Sjason@lowepower.comsystem.cpu.iew.wb_consumers 132115 # num instructions consuming a value 51411731Sjason@lowepower.comsystem.cpu.iew.wb_rate 1.106726 # insts written-back per cycle 51511731Sjason@lowepower.comsystem.cpu.iew.wb_fanout 0.724293 # average fanout of values written-back 51611731Sjason@lowepower.comsystem.cpu.commit.commitSquashedInsts 47577 # The number of squashed insts skipped by commit 51711731Sjason@lowepower.comsystem.cpu.commit.commitNonSpecStalls 117 # The number of times commit has been forced to stall to communicate backwards 51811731Sjason@lowepower.comsystem.cpu.commit.branchMispredicts 4142 # The number of times a branch was mispredicted 51911731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::samples 157673 # Number of insts commited each cycle 52011731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::mean 1.434355 # Number of insts commited each cycle 52111731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::stdev 2.158076 # Number of insts commited each cycle 52211731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 52311731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::0 82961 52.62% 52.62% # Number of insts commited each cycle 52411731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::1 25849 16.39% 69.01% # Number of insts commited each cycle 52511731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::2 14396 9.13% 78.14% # Number of insts commited each cycle 52611731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::3 11000 6.98% 85.12% # Number of insts commited each cycle 52711731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::4 5848 3.71% 88.83% # Number of insts commited each cycle 52811731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::5 5974 3.79% 92.61% # Number of insts commited each cycle 52911731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::6 3323 2.11% 94.72% # Number of insts commited each cycle 53011731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::7 1258 0.80% 95.52% # Number of insts commited each cycle 53111731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::8 7064 4.48% 100.00% # Number of insts commited each cycle 53211731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 53311731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 53411731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 53511731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::total 157673 # Number of insts commited each cycle 53611731Sjason@lowepower.comsystem.cpu.commit.committedInsts 226159 # Number of instructions committed 53711731Sjason@lowepower.comsystem.cpu.commit.committedOps 226159 # Number of ops (including micro ops) committed 53811731Sjason@lowepower.comsystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 53911731Sjason@lowepower.comsystem.cpu.commit.refs 88940 # Number of memory references committed 54011731Sjason@lowepower.comsystem.cpu.commit.loads 51711 # Number of loads committed 54111731Sjason@lowepower.comsystem.cpu.commit.membars 0 # Number of memory barriers committed 54211731Sjason@lowepower.comsystem.cpu.commit.branches 50405 # Number of branches committed 54311731Sjason@lowepower.comsystem.cpu.commit.fp_insts 862 # Number of committed floating point instructions. 54411731Sjason@lowepower.comsystem.cpu.commit.int_insts 225991 # Number of committed integer instructions. 54511731Sjason@lowepower.comsystem.cpu.commit.function_calls 16616 # Number of function calls committed. 54611731Sjason@lowepower.comsystem.cpu.commit.op_class_0::No_OpClass 2 0.00% 0.00% # Class of committed instruction 54711731Sjason@lowepower.comsystem.cpu.commit.op_class_0::IntAlu 136540 60.37% 60.37% # Class of committed instruction 54811731Sjason@lowepower.comsystem.cpu.commit.op_class_0::IntMult 325 0.14% 60.52% # Class of committed instruction 54911731Sjason@lowepower.comsystem.cpu.commit.op_class_0::IntDiv 40 0.02% 60.54% # Class of committed instruction 55011731Sjason@lowepower.comsystem.cpu.commit.op_class_0::FloatAdd 104 0.05% 60.58% # Class of committed instruction 55111731Sjason@lowepower.comsystem.cpu.commit.op_class_0::FloatCmp 119 0.05% 60.63% # Class of committed instruction 55211731Sjason@lowepower.comsystem.cpu.commit.op_class_0::FloatCvt 43 0.02% 60.65% # Class of committed instruction 55311731Sjason@lowepower.comsystem.cpu.commit.op_class_0::FloatMult 30 0.01% 60.67% # Class of committed instruction 55411731Sjason@lowepower.comsystem.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 60.67% # Class of committed instruction 55511731Sjason@lowepower.comsystem.cpu.commit.op_class_0::FloatDiv 11 0.00% 60.67% # Class of committed instruction 55611731Sjason@lowepower.comsystem.cpu.commit.op_class_0::FloatMisc 0 0.00% 60.67% # Class of committed instruction 55711731Sjason@lowepower.comsystem.cpu.commit.op_class_0::FloatSqrt 5 0.00% 60.67% # Class of committed instruction 55811731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 60.67% # Class of committed instruction 55911731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 60.67% # Class of committed instruction 56011731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 60.67% # Class of committed instruction 56111731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 60.67% # Class of committed instruction 56211731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 60.67% # Class of committed instruction 56311731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 60.67% # Class of committed instruction 56411731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 60.67% # Class of committed instruction 56511731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 60.67% # Class of committed instruction 56611731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 60.67% # Class of committed instruction 56711731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 60.67% # Class of committed instruction 56811731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 60.67% # Class of committed instruction 56911731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 60.67% # Class of committed instruction 57011731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 60.67% # Class of committed instruction 57111731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 60.67% # Class of committed instruction 57211731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 60.67% # Class of committed instruction 57311731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 60.67% # Class of committed instruction 57411731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 60.67% # Class of committed instruction 57511731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 60.67% # Class of committed instruction 57611731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 60.67% # Class of committed instruction 57711731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 60.67% # Class of committed instruction 57811731Sjason@lowepower.comsystem.cpu.commit.op_class_0::MemRead 51297 22.68% 83.36% # Class of committed instruction 57911731Sjason@lowepower.comsystem.cpu.commit.op_class_0::MemWrite 37093 16.40% 99.76% # Class of committed instruction 58011731Sjason@lowepower.comsystem.cpu.commit.op_class_0::FloatMemRead 414 0.18% 99.94% # Class of committed instruction 58111731Sjason@lowepower.comsystem.cpu.commit.op_class_0::FloatMemWrite 136 0.06% 100.00% # Class of committed instruction 58211731Sjason@lowepower.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 58311731Sjason@lowepower.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 58411731Sjason@lowepower.comsystem.cpu.commit.op_class_0::total 226159 # Class of committed instruction 58511731Sjason@lowepower.comsystem.cpu.commit.bw_lim_events 7064 # number cycles where commit BW limit reached 58611731Sjason@lowepower.comsystem.cpu.rob.rob_reads 422850 # The number of ROB reads 58711731Sjason@lowepower.comsystem.cpu.rob.rob_writes 556608 # The number of ROB writes 58811731Sjason@lowepower.comsystem.cpu.timesIdled 458 # Number of times that the entire CPU went into an idle state and unscheduled itself 58911731Sjason@lowepower.comsystem.cpu.idleCycles 60069 # Total number of cycles that the CPU has spent unscheduled due to idling 59011731Sjason@lowepower.comsystem.cpu.committedInsts 226159 # Number of Instructions Simulated 59111731Sjason@lowepower.comsystem.cpu.committedOps 226159 # Number of Ops (including micro ops) Simulated 59211731Sjason@lowepower.comsystem.cpu.cpi 1.002812 # CPI: Cycles Per Instruction 59311731Sjason@lowepower.comsystem.cpu.cpi_total 1.002812 # CPI: Total CPI of All Threads 59411731Sjason@lowepower.comsystem.cpu.ipc 0.997196 # IPC: Instructions Per Cycle 59511731Sjason@lowepower.comsystem.cpu.ipc_total 0.997196 # IPC: Total IPC of All Threads 59611731Sjason@lowepower.comsystem.cpu.int_regfile_reads 329004 # number of integer regfile reads 59711731Sjason@lowepower.comsystem.cpu.int_regfile_writes 174767 # number of integer regfile writes 59811731Sjason@lowepower.comsystem.cpu.fp_regfile_reads 880 # number of floating regfile reads 59911731Sjason@lowepower.comsystem.cpu.fp_regfile_writes 753 # number of floating regfile writes 60011731Sjason@lowepower.comsystem.cpu.misc_regfile_reads 448 # number of misc regfile reads 60111731Sjason@lowepower.comsystem.cpu.misc_regfile_writes 313 # number of misc regfile writes 60211731Sjason@lowepower.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states 60311731Sjason@lowepower.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 60411731Sjason@lowepower.comsystem.cpu.dcache.tags.tagsinuse 244.736374 # Cycle average of tags in use 60511731Sjason@lowepower.comsystem.cpu.dcache.tags.total_refs 87597 # Total number of references to valid blocks. 60611731Sjason@lowepower.comsystem.cpu.dcache.tags.sampled_refs 301 # Sample count of references to valid blocks. 60711731Sjason@lowepower.comsystem.cpu.dcache.tags.avg_refs 291.019934 # Average number of references to valid blocks. 60811731Sjason@lowepower.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 60911731Sjason@lowepower.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 244.736374 # Average occupied blocks per requestor 61011731Sjason@lowepower.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.059750 # Average percentage of cache occupancy 61111731Sjason@lowepower.comsystem.cpu.dcache.tags.occ_percent::total 0.059750 # Average percentage of cache occupancy 61211731Sjason@lowepower.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 301 # Occupied blocks per task id 61311731Sjason@lowepower.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id 61411731Sjason@lowepower.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id 61511731Sjason@lowepower.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 194 # Occupied blocks per task id 61611731Sjason@lowepower.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 0.073486 # Percentage of cache occupancy per task id 61711731Sjason@lowepower.comsystem.cpu.dcache.tags.tag_accesses 179361 # Number of tag accesses 61811731Sjason@lowepower.comsystem.cpu.dcache.tags.data_accesses 179361 # Number of data accesses 61911731Sjason@lowepower.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states 62011731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_hits::cpu.data 51858 # number of ReadReq hits 62111731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_hits::total 51858 # number of ReadReq hits 62211731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_hits::cpu.data 35739 # number of WriteReq hits 62311731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_hits::total 35739 # number of WriteReq hits 62411731Sjason@lowepower.comsystem.cpu.dcache.demand_hits::cpu.data 87597 # number of demand (read+write) hits 62511731Sjason@lowepower.comsystem.cpu.dcache.demand_hits::total 87597 # number of demand (read+write) hits 62611731Sjason@lowepower.comsystem.cpu.dcache.overall_hits::cpu.data 87597 # number of overall hits 62711731Sjason@lowepower.comsystem.cpu.dcache.overall_hits::total 87597 # number of overall hits 62811731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_misses::cpu.data 443 # number of ReadReq misses 62911731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_misses::total 443 # number of ReadReq misses 63011731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_misses::cpu.data 1490 # number of WriteReq misses 63111731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_misses::total 1490 # number of WriteReq misses 63211731Sjason@lowepower.comsystem.cpu.dcache.demand_misses::cpu.data 1933 # number of demand (read+write) misses 63311731Sjason@lowepower.comsystem.cpu.dcache.demand_misses::total 1933 # number of demand (read+write) misses 63411731Sjason@lowepower.comsystem.cpu.dcache.overall_misses::cpu.data 1933 # number of overall misses 63511731Sjason@lowepower.comsystem.cpu.dcache.overall_misses::total 1933 # number of overall misses 63611731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 36817500 # number of ReadReq miss cycles 63711731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_miss_latency::total 36817500 # number of ReadReq miss cycles 63811731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 96718425 # number of WriteReq miss cycles 63911731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_miss_latency::total 96718425 # number of WriteReq miss cycles 64011731Sjason@lowepower.comsystem.cpu.dcache.demand_miss_latency::cpu.data 133535925 # number of demand (read+write) miss cycles 64111731Sjason@lowepower.comsystem.cpu.dcache.demand_miss_latency::total 133535925 # number of demand (read+write) miss cycles 64211731Sjason@lowepower.comsystem.cpu.dcache.overall_miss_latency::cpu.data 133535925 # number of overall miss cycles 64311731Sjason@lowepower.comsystem.cpu.dcache.overall_miss_latency::total 133535925 # number of overall miss cycles 64411731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 52301 # number of ReadReq accesses(hits+misses) 64511731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_accesses::total 52301 # number of ReadReq accesses(hits+misses) 64611731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 37229 # number of WriteReq accesses(hits+misses) 64711731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_accesses::total 37229 # number of WriteReq accesses(hits+misses) 64811731Sjason@lowepower.comsystem.cpu.dcache.demand_accesses::cpu.data 89530 # number of demand (read+write) accesses 64911731Sjason@lowepower.comsystem.cpu.dcache.demand_accesses::total 89530 # number of demand (read+write) accesses 65011731Sjason@lowepower.comsystem.cpu.dcache.overall_accesses::cpu.data 89530 # number of overall (read+write) accesses 65111731Sjason@lowepower.comsystem.cpu.dcache.overall_accesses::total 89530 # number of overall (read+write) accesses 65211731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008470 # miss rate for ReadReq accesses 65311731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.008470 # miss rate for ReadReq accesses 65411731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.040023 # miss rate for WriteReq accesses 65511731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.040023 # miss rate for WriteReq accesses 65611731Sjason@lowepower.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.021591 # miss rate for demand accesses 65711731Sjason@lowepower.comsystem.cpu.dcache.demand_miss_rate::total 0.021591 # miss rate for demand accesses 65811731Sjason@lowepower.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.021591 # miss rate for overall accesses 65911731Sjason@lowepower.comsystem.cpu.dcache.overall_miss_rate::total 0.021591 # miss rate for overall accesses 66011731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 83109.480813 # average ReadReq miss latency 66111731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 83109.480813 # average ReadReq miss latency 66211731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64911.694631 # average WriteReq miss latency 66311731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 64911.694631 # average WriteReq miss latency 66411731Sjason@lowepower.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 69082.216762 # average overall miss latency 66511731Sjason@lowepower.comsystem.cpu.dcache.demand_avg_miss_latency::total 69082.216762 # average overall miss latency 66611731Sjason@lowepower.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 69082.216762 # average overall miss latency 66711731Sjason@lowepower.comsystem.cpu.dcache.overall_avg_miss_latency::total 69082.216762 # average overall miss latency 66811731Sjason@lowepower.comsystem.cpu.dcache.blocked_cycles::no_mshrs 5513 # number of cycles access was blocked 66911731Sjason@lowepower.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 67011731Sjason@lowepower.comsystem.cpu.dcache.blocked::no_mshrs 79 # number of cycles access was blocked 67111731Sjason@lowepower.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 67211731Sjason@lowepower.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 69.784810 # average number of cycles each access was blocked 67311731Sjason@lowepower.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 67411731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 346 # number of ReadReq MSHR hits 67511731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_hits::total 346 # number of ReadReq MSHR hits 67611731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 1286 # number of WriteReq MSHR hits 67711731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_hits::total 1286 # number of WriteReq MSHR hits 67811731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 1632 # number of demand (read+write) MSHR hits 67911731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_hits::total 1632 # number of demand (read+write) MSHR hits 68011731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 1632 # number of overall MSHR hits 68111731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_hits::total 1632 # number of overall MSHR hits 68211731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 97 # number of ReadReq MSHR misses 68311731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_misses::total 97 # number of ReadReq MSHR misses 68411731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 204 # number of WriteReq MSHR misses 68511731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_misses::total 204 # number of WriteReq MSHR misses 68611731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 301 # number of demand (read+write) MSHR misses 68711731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses 68811731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 301 # number of overall MSHR misses 68911731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_misses::total 301 # number of overall MSHR misses 69011731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8757000 # number of ReadReq MSHR miss cycles 69111731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 8757000 # number of ReadReq MSHR miss cycles 69211731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16055500 # number of WriteReq MSHR miss cycles 69311731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 16055500 # number of WriteReq MSHR miss cycles 69411731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 24812500 # number of demand (read+write) MSHR miss cycles 69511731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_miss_latency::total 24812500 # number of demand (read+write) MSHR miss cycles 69611731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 24812500 # number of overall MSHR miss cycles 69711731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_miss_latency::total 24812500 # number of overall MSHR miss cycles 69811731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001855 # mshr miss rate for ReadReq accesses 69911731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001855 # mshr miss rate for ReadReq accesses 70011731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005480 # mshr miss rate for WriteReq accesses 70111731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005480 # mshr miss rate for WriteReq accesses 70211731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003362 # mshr miss rate for demand accesses 70311731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.003362 # mshr miss rate for demand accesses 70411731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003362 # mshr miss rate for overall accesses 70511731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.003362 # mshr miss rate for overall accesses 70611731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 90278.350515 # average ReadReq mshr miss latency 70711731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 90278.350515 # average ReadReq mshr miss latency 70811731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78703.431373 # average WriteReq mshr miss latency 70911731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78703.431373 # average WriteReq mshr miss latency 71011731Sjason@lowepower.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82433.554817 # average overall mshr miss latency 71111731Sjason@lowepower.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 82433.554817 # average overall mshr miss latency 71211731Sjason@lowepower.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82433.554817 # average overall mshr miss latency 71311731Sjason@lowepower.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 82433.554817 # average overall mshr miss latency 71411731Sjason@lowepower.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states 71511731Sjason@lowepower.comsystem.cpu.icache.tags.replacements 69 # number of replacements 71611731Sjason@lowepower.comsystem.cpu.icache.tags.tagsinuse 535.650396 # Cycle average of tags in use 71711731Sjason@lowepower.comsystem.cpu.icache.tags.total_refs 59273 # Total number of references to valid blocks. 71811731Sjason@lowepower.comsystem.cpu.icache.tags.sampled_refs 1034 # Sample count of references to valid blocks. 71911731Sjason@lowepower.comsystem.cpu.icache.tags.avg_refs 57.323985 # Average number of references to valid blocks. 72011731Sjason@lowepower.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 72111731Sjason@lowepower.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 535.650396 # Average occupied blocks per requestor 72211731Sjason@lowepower.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.261548 # Average percentage of cache occupancy 72311731Sjason@lowepower.comsystem.cpu.icache.tags.occ_percent::total 0.261548 # Average percentage of cache occupancy 72411731Sjason@lowepower.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 965 # Occupied blocks per task id 72511731Sjason@lowepower.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id 72611731Sjason@lowepower.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 738 # Occupied blocks per task id 72711731Sjason@lowepower.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 120 # Occupied blocks per task id 72811731Sjason@lowepower.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.471191 # Percentage of cache occupancy per task id 72911731Sjason@lowepower.comsystem.cpu.icache.tags.tag_accesses 122286 # Number of tag accesses 73011731Sjason@lowepower.comsystem.cpu.icache.tags.data_accesses 122286 # Number of data accesses 73111731Sjason@lowepower.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states 73211731Sjason@lowepower.comsystem.cpu.icache.ReadReq_hits::cpu.inst 59273 # number of ReadReq hits 73311731Sjason@lowepower.comsystem.cpu.icache.ReadReq_hits::total 59273 # number of ReadReq hits 73411731Sjason@lowepower.comsystem.cpu.icache.demand_hits::cpu.inst 59273 # number of demand (read+write) hits 73511731Sjason@lowepower.comsystem.cpu.icache.demand_hits::total 59273 # number of demand (read+write) hits 73611731Sjason@lowepower.comsystem.cpu.icache.overall_hits::cpu.inst 59273 # number of overall hits 73711731Sjason@lowepower.comsystem.cpu.icache.overall_hits::total 59273 # number of overall hits 73811731Sjason@lowepower.comsystem.cpu.icache.ReadReq_misses::cpu.inst 1353 # number of ReadReq misses 73911731Sjason@lowepower.comsystem.cpu.icache.ReadReq_misses::total 1353 # number of ReadReq misses 74011731Sjason@lowepower.comsystem.cpu.icache.demand_misses::cpu.inst 1353 # number of demand (read+write) misses 74111731Sjason@lowepower.comsystem.cpu.icache.demand_misses::total 1353 # number of demand (read+write) misses 74211731Sjason@lowepower.comsystem.cpu.icache.overall_misses::cpu.inst 1353 # number of overall misses 74311731Sjason@lowepower.comsystem.cpu.icache.overall_misses::total 1353 # number of overall misses 74411731Sjason@lowepower.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 109130497 # number of ReadReq miss cycles 74511731Sjason@lowepower.comsystem.cpu.icache.ReadReq_miss_latency::total 109130497 # number of ReadReq miss cycles 74611731Sjason@lowepower.comsystem.cpu.icache.demand_miss_latency::cpu.inst 109130497 # number of demand (read+write) miss cycles 74711731Sjason@lowepower.comsystem.cpu.icache.demand_miss_latency::total 109130497 # number of demand (read+write) miss cycles 74811731Sjason@lowepower.comsystem.cpu.icache.overall_miss_latency::cpu.inst 109130497 # number of overall miss cycles 74911731Sjason@lowepower.comsystem.cpu.icache.overall_miss_latency::total 109130497 # number of overall miss cycles 75011731Sjason@lowepower.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 60626 # number of ReadReq accesses(hits+misses) 75111731Sjason@lowepower.comsystem.cpu.icache.ReadReq_accesses::total 60626 # number of ReadReq accesses(hits+misses) 75211731Sjason@lowepower.comsystem.cpu.icache.demand_accesses::cpu.inst 60626 # number of demand (read+write) accesses 75311731Sjason@lowepower.comsystem.cpu.icache.demand_accesses::total 60626 # number of demand (read+write) accesses 75411731Sjason@lowepower.comsystem.cpu.icache.overall_accesses::cpu.inst 60626 # number of overall (read+write) accesses 75511731Sjason@lowepower.comsystem.cpu.icache.overall_accesses::total 60626 # number of overall (read+write) accesses 75611731Sjason@lowepower.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.022317 # miss rate for ReadReq accesses 75711731Sjason@lowepower.comsystem.cpu.icache.ReadReq_miss_rate::total 0.022317 # miss rate for ReadReq accesses 75811731Sjason@lowepower.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.022317 # miss rate for demand accesses 75911731Sjason@lowepower.comsystem.cpu.icache.demand_miss_rate::total 0.022317 # miss rate for demand accesses 76011731Sjason@lowepower.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.022317 # miss rate for overall accesses 76111731Sjason@lowepower.comsystem.cpu.icache.overall_miss_rate::total 0.022317 # miss rate for overall accesses 76211731Sjason@lowepower.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80658.164819 # average ReadReq miss latency 76311731Sjason@lowepower.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 80658.164819 # average ReadReq miss latency 76411731Sjason@lowepower.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 80658.164819 # average overall miss latency 76511731Sjason@lowepower.comsystem.cpu.icache.demand_avg_miss_latency::total 80658.164819 # average overall miss latency 76611731Sjason@lowepower.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 80658.164819 # average overall miss latency 76711731Sjason@lowepower.comsystem.cpu.icache.overall_avg_miss_latency::total 80658.164819 # average overall miss latency 76811731Sjason@lowepower.comsystem.cpu.icache.blocked_cycles::no_mshrs 2365 # number of cycles access was blocked 76911731Sjason@lowepower.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 77011731Sjason@lowepower.comsystem.cpu.icache.blocked::no_mshrs 33 # number of cycles access was blocked 77111731Sjason@lowepower.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 77211731Sjason@lowepower.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 71.666667 # average number of cycles each access was blocked 77311731Sjason@lowepower.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 77411731Sjason@lowepower.comsystem.cpu.icache.writebacks::writebacks 69 # number of writebacks 77511731Sjason@lowepower.comsystem.cpu.icache.writebacks::total 69 # number of writebacks 77611731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 319 # number of ReadReq MSHR hits 77711731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_hits::total 319 # number of ReadReq MSHR hits 77811731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 319 # number of demand (read+write) MSHR hits 77911731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_hits::total 319 # number of demand (read+write) MSHR hits 78011731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 319 # number of overall MSHR hits 78111731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_hits::total 319 # number of overall MSHR hits 78211731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 1034 # number of ReadReq MSHR misses 78311731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_misses::total 1034 # number of ReadReq MSHR misses 78411731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 1034 # number of demand (read+write) MSHR misses 78511731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_misses::total 1034 # number of demand (read+write) MSHR misses 78611731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 1034 # number of overall MSHR misses 78711731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_misses::total 1034 # number of overall MSHR misses 78811731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 86838997 # number of ReadReq MSHR miss cycles 78911731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 86838997 # number of ReadReq MSHR miss cycles 79011731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 86838997 # number of demand (read+write) MSHR miss cycles 79111731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_miss_latency::total 86838997 # number of demand (read+write) MSHR miss cycles 79211731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 86838997 # number of overall MSHR miss cycles 79311731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_miss_latency::total 86838997 # number of overall MSHR miss cycles 79411731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.017055 # mshr miss rate for ReadReq accesses 79511731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.017055 # mshr miss rate for ReadReq accesses 79611731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.017055 # mshr miss rate for demand accesses 79711731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.017055 # mshr miss rate for demand accesses 79811731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.017055 # mshr miss rate for overall accesses 79911731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.017055 # mshr miss rate for overall accesses 80011731Sjason@lowepower.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83983.556093 # average ReadReq mshr miss latency 80111731Sjason@lowepower.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83983.556093 # average ReadReq mshr miss latency 80211731Sjason@lowepower.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83983.556093 # average overall mshr miss latency 80311731Sjason@lowepower.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 83983.556093 # average overall mshr miss latency 80411731Sjason@lowepower.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83983.556093 # average overall mshr miss latency 80511731Sjason@lowepower.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 83983.556093 # average overall mshr miss latency 80611731Sjason@lowepower.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states 80711731Sjason@lowepower.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 80811731Sjason@lowepower.comsystem.cpu.l2cache.tags.tagsinuse 808.401303 # Cycle average of tags in use 80911731Sjason@lowepower.comsystem.cpu.l2cache.tags.total_refs 71 # Total number of references to valid blocks. 81011731Sjason@lowepower.comsystem.cpu.l2cache.tags.sampled_refs 1330 # Sample count of references to valid blocks. 81111731Sjason@lowepower.comsystem.cpu.l2cache.tags.avg_refs 0.053383 # Average number of references to valid blocks. 81211731Sjason@lowepower.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 81311731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 563.637058 # Average occupied blocks per requestor 81411731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 244.764245 # Average occupied blocks per requestor 81511731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.017201 # Average percentage of cache occupancy 81611731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.007470 # Average percentage of cache occupancy 81711731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_percent::total 0.024670 # Average percentage of cache occupancy 81811731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 1330 # Occupied blocks per task id 81911731Sjason@lowepower.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id 82011731Sjason@lowepower.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 879 # Occupied blocks per task id 82111731Sjason@lowepower.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 337 # Occupied blocks per task id 82211731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.040588 # Percentage of cache occupancy per task id 82311731Sjason@lowepower.comsystem.cpu.l2cache.tags.tag_accesses 12538 # Number of tag accesses 82411731Sjason@lowepower.comsystem.cpu.l2cache.tags.data_accesses 12538 # Number of data accesses 82511731Sjason@lowepower.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states 82611731Sjason@lowepower.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 69 # number of WritebackClean hits 82711731Sjason@lowepower.comsystem.cpu.l2cache.WritebackClean_hits::total 69 # number of WritebackClean hits 82811731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits 82911731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits 83011731Sjason@lowepower.comsystem.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 83111731Sjason@lowepower.comsystem.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 83211731Sjason@lowepower.comsystem.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 83311731Sjason@lowepower.comsystem.cpu.l2cache.overall_hits::total 2 # number of overall hits 83411731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 204 # number of ReadExReq misses 83511731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_misses::total 204 # number of ReadExReq misses 83611731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1029 # number of ReadCleanReq misses 83711731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_misses::total 1029 # number of ReadCleanReq misses 83811731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 97 # number of ReadSharedReq misses 83911731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_misses::total 97 # number of ReadSharedReq misses 84011731Sjason@lowepower.comsystem.cpu.l2cache.demand_misses::cpu.inst 1029 # number of demand (read+write) misses 84111731Sjason@lowepower.comsystem.cpu.l2cache.demand_misses::cpu.data 301 # number of demand (read+write) misses 84211731Sjason@lowepower.comsystem.cpu.l2cache.demand_misses::total 1330 # number of demand (read+write) misses 84311731Sjason@lowepower.comsystem.cpu.l2cache.overall_misses::cpu.inst 1029 # number of overall misses 84411731Sjason@lowepower.comsystem.cpu.l2cache.overall_misses::cpu.data 301 # number of overall misses 84511731Sjason@lowepower.comsystem.cpu.l2cache.overall_misses::total 1330 # number of overall misses 84611731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15749000 # number of ReadExReq miss cycles 84711731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 15749000 # number of ReadExReq miss cycles 84811731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 85256500 # number of ReadCleanReq miss cycles 84911731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 85256500 # number of ReadCleanReq miss cycles 85011731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8611500 # number of ReadSharedReq miss cycles 85111731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 8611500 # number of ReadSharedReq miss cycles 85211731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 85256500 # number of demand (read+write) miss cycles 85311731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 24360500 # number of demand (read+write) miss cycles 85411731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_latency::total 109617000 # number of demand (read+write) miss cycles 85511731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 85256500 # number of overall miss cycles 85611731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 24360500 # number of overall miss cycles 85711731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_latency::total 109617000 # number of overall miss cycles 85811731Sjason@lowepower.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 69 # number of WritebackClean accesses(hits+misses) 85911731Sjason@lowepower.comsystem.cpu.l2cache.WritebackClean_accesses::total 69 # number of WritebackClean accesses(hits+misses) 86011731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 204 # number of ReadExReq accesses(hits+misses) 86111731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_accesses::total 204 # number of ReadExReq accesses(hits+misses) 86211731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1031 # number of ReadCleanReq accesses(hits+misses) 86311731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 1031 # number of ReadCleanReq accesses(hits+misses) 86411731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 97 # number of ReadSharedReq accesses(hits+misses) 86511731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 97 # number of ReadSharedReq accesses(hits+misses) 86611731Sjason@lowepower.comsystem.cpu.l2cache.demand_accesses::cpu.inst 1031 # number of demand (read+write) accesses 86711731Sjason@lowepower.comsystem.cpu.l2cache.demand_accesses::cpu.data 301 # number of demand (read+write) accesses 86811731Sjason@lowepower.comsystem.cpu.l2cache.demand_accesses::total 1332 # number of demand (read+write) accesses 86911731Sjason@lowepower.comsystem.cpu.l2cache.overall_accesses::cpu.inst 1031 # number of overall (read+write) accesses 87011731Sjason@lowepower.comsystem.cpu.l2cache.overall_accesses::cpu.data 301 # number of overall (read+write) accesses 87111731Sjason@lowepower.comsystem.cpu.l2cache.overall_accesses::total 1332 # number of overall (read+write) accesses 87211731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 87311731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 87411731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.998060 # miss rate for ReadCleanReq accesses 87511731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.998060 # miss rate for ReadCleanReq accesses 87611731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 87711731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 87811731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.998060 # miss rate for demand accesses 87911731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 88011731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_rate::total 0.998498 # miss rate for demand accesses 88111731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.998060 # miss rate for overall accesses 88211731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 88311731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_rate::total 0.998498 # miss rate for overall accesses 88411731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77200.980392 # average ReadExReq miss latency 88511731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 77200.980392 # average ReadExReq miss latency 88611731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82853.741497 # average ReadCleanReq miss latency 88711731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82853.741497 # average ReadCleanReq miss latency 88811731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88778.350515 # average ReadSharedReq miss latency 88911731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88778.350515 # average ReadSharedReq miss latency 89011731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82853.741497 # average overall miss latency 89111731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 80931.893688 # average overall miss latency 89211731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_miss_latency::total 82418.796992 # average overall miss latency 89311731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82853.741497 # average overall miss latency 89411731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 80931.893688 # average overall miss latency 89511731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_miss_latency::total 82418.796992 # average overall miss latency 89611731Sjason@lowepower.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 89711731Sjason@lowepower.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 89811731Sjason@lowepower.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 89911731Sjason@lowepower.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 90011731Sjason@lowepower.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 90111731Sjason@lowepower.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 90211731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 204 # number of ReadExReq MSHR misses 90311731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 204 # number of ReadExReq MSHR misses 90411731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1029 # number of ReadCleanReq MSHR misses 90511731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 1029 # number of ReadCleanReq MSHR misses 90611731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 97 # number of ReadSharedReq MSHR misses 90711731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 97 # number of ReadSharedReq MSHR misses 90811731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 1029 # number of demand (read+write) MSHR misses 90911731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 301 # number of demand (read+write) MSHR misses 91011731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_misses::total 1330 # number of demand (read+write) MSHR misses 91111731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 1029 # number of overall MSHR misses 91211731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 301 # number of overall MSHR misses 91311731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_misses::total 1330 # number of overall MSHR misses 91411731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13709000 # number of ReadExReq MSHR miss cycles 91511731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13709000 # number of ReadExReq MSHR miss cycles 91611731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 74966500 # number of ReadCleanReq MSHR miss cycles 91711731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 74966500 # number of ReadCleanReq MSHR miss cycles 91811731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7641500 # number of ReadSharedReq MSHR miss cycles 91911731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7641500 # number of ReadSharedReq MSHR miss cycles 92011731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 74966500 # number of demand (read+write) MSHR miss cycles 92111731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21350500 # number of demand (read+write) MSHR miss cycles 92211731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 96317000 # number of demand (read+write) MSHR miss cycles 92311731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 74966500 # number of overall MSHR miss cycles 92411731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21350500 # number of overall MSHR miss cycles 92511731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 96317000 # number of overall MSHR miss cycles 92611731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 92711731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 92811731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.998060 # mshr miss rate for ReadCleanReq accesses 92911731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.998060 # mshr miss rate for ReadCleanReq accesses 93011731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 93111731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 93211731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998060 # mshr miss rate for demand accesses 93311731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 93411731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.998498 # mshr miss rate for demand accesses 93511731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998060 # mshr miss rate for overall accesses 93611731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 93711731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.998498 # mshr miss rate for overall accesses 93811731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67200.980392 # average ReadExReq mshr miss latency 93911731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67200.980392 # average ReadExReq mshr miss latency 94011731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72853.741497 # average ReadCleanReq mshr miss latency 94111731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72853.741497 # average ReadCleanReq mshr miss latency 94211731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78778.350515 # average ReadSharedReq mshr miss latency 94311731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78778.350515 # average ReadSharedReq mshr miss latency 94411731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72853.741497 # average overall mshr miss latency 94511731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70931.893688 # average overall mshr miss latency 94611731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 72418.796992 # average overall mshr miss latency 94711731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72853.741497 # average overall mshr miss latency 94811731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70931.893688 # average overall mshr miss latency 94911731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 72418.796992 # average overall mshr miss latency 95011731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 1404 # Total number of requests made to the snoop filter. 95111731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 72 # Number of requests hitting in the snoop filter with a single holder of the requested data. 95211731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 95311731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 95411731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 95511731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 95611731Sjason@lowepower.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states 95711731Sjason@lowepower.comsystem.cpu.toL2Bus.trans_dist::ReadResp 1131 # Transaction distribution 95811731Sjason@lowepower.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 69 # Transaction distribution 95911731Sjason@lowepower.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 204 # Transaction distribution 96011731Sjason@lowepower.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 204 # Transaction distribution 96111731Sjason@lowepower.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 1034 # Transaction distribution 96211731Sjason@lowepower.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 97 # Transaction distribution 96311731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2134 # Packet count per connected master and slave (bytes) 96411731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 602 # Packet count per connected master and slave (bytes) 96511731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_count::total 2736 # Packet count per connected master and slave (bytes) 96611731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 70400 # Cumulative packet size per connected master and slave (bytes) 96711731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 19264 # Cumulative packet size per connected master and slave (bytes) 96811731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_size::total 89664 # Cumulative packet size per connected master and slave (bytes) 96911731Sjason@lowepower.comsystem.cpu.toL2Bus.snoops 3 # Total snoops (count) 97011731Sjason@lowepower.comsystem.cpu.toL2Bus.snoopTraffic 192 # Total snoop traffic (bytes) 97111731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::samples 1335 # Request fanout histogram 97211731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.002247 # Request fanout histogram 97311731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.047369 # Request fanout histogram 97411731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 97511731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::0 1332 99.78% 99.78% # Request fanout histogram 97611731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::1 3 0.22% 100.00% # Request fanout histogram 97711731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 97811731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 97911731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 98011731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 98111731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::total 1335 # Request fanout histogram 98211731Sjason@lowepower.comsystem.cpu.toL2Bus.reqLayer0.occupancy 771000 # Layer occupancy (ticks) 98311731Sjason@lowepower.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 98411731Sjason@lowepower.comsystem.cpu.toL2Bus.respLayer0.occupancy 1551000 # Layer occupancy (ticks) 98511731Sjason@lowepower.comsystem.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) 98611731Sjason@lowepower.comsystem.cpu.toL2Bus.respLayer1.occupancy 451500 # Layer occupancy (ticks) 98711731Sjason@lowepower.comsystem.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) 98811731Sjason@lowepower.comsystem.membus.snoop_filter.tot_requests 1330 # Total number of requests made to the snoop filter. 98911731Sjason@lowepower.comsystem.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 99011731Sjason@lowepower.comsystem.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 99111731Sjason@lowepower.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 99211731Sjason@lowepower.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 99311731Sjason@lowepower.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 99411731Sjason@lowepower.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states 99511731Sjason@lowepower.comsystem.membus.trans_dist::ReadResp 1126 # Transaction distribution 99611731Sjason@lowepower.comsystem.membus.trans_dist::ReadExReq 204 # Transaction distribution 99711731Sjason@lowepower.comsystem.membus.trans_dist::ReadExResp 204 # Transaction distribution 99811731Sjason@lowepower.comsystem.membus.trans_dist::ReadSharedReq 1126 # Transaction distribution 99911731Sjason@lowepower.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2660 # Packet count per connected master and slave (bytes) 100011731Sjason@lowepower.comsystem.membus.pkt_count::total 2660 # Packet count per connected master and slave (bytes) 100111731Sjason@lowepower.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 85120 # Cumulative packet size per connected master and slave (bytes) 100211731Sjason@lowepower.comsystem.membus.pkt_size::total 85120 # Cumulative packet size per connected master and slave (bytes) 100311731Sjason@lowepower.comsystem.membus.snoops 0 # Total snoops (count) 100411731Sjason@lowepower.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 100511731Sjason@lowepower.comsystem.membus.snoop_fanout::samples 1330 # Request fanout histogram 100611731Sjason@lowepower.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 100711731Sjason@lowepower.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 100811731Sjason@lowepower.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 100911731Sjason@lowepower.comsystem.membus.snoop_fanout::0 1330 100.00% 100.00% # Request fanout histogram 101011731Sjason@lowepower.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 101111731Sjason@lowepower.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 101211731Sjason@lowepower.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 101311731Sjason@lowepower.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 101411731Sjason@lowepower.comsystem.membus.snoop_fanout::total 1330 # Request fanout histogram 101511731Sjason@lowepower.comsystem.membus.reqLayer0.occupancy 1627500 # Layer occupancy (ticks) 101611731Sjason@lowepower.comsystem.membus.reqLayer0.utilization 1.4 # Layer utilization (%) 101711731Sjason@lowepower.comsystem.membus.respLayer1.occupancy 7008750 # Layer occupancy (ticks) 101811731Sjason@lowepower.comsystem.membus.respLayer1.utilization 6.2 # Layer utilization (%) 101911731Sjason@lowepower.com 102011731Sjason@lowepower.com---------- End Simulation Statistics ---------- 1021