simout revision 12137:d877205ec1bc 
1Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby/simout
2Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby/simerr
3gem5 Simulator System.  http://gem5.org
4gem5 is copyrighted software; use the --copyright option for details.
5
6gem5 compiled Jul 13 2017 17:09:45
7gem5 started Jul 13 2017 17:25:07
8gem5 executing on boldrock, pid 6003
9command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby
10
11Global frequency set at 1000000000 ticks per second
12c.lwsp: PASS
13c.ldsp: PASS
14c.fldsp: PASS
15c.swsp: PASS
16c.sdsp: PASS
17c.fsdsp: PASS
18c.lw, positive: PASS
19c.lw, negative: PASS
20c.ld: PASS
21c.fld: PASS
22c.sw: PASS
23c.sd: PASS
24c.fsd: PASS
25c.j: PASS
26c.jr: PASS
27c.jalr: PASS
28c.beqz, zero: PASS
29c.beqz, not zero: PASS
30c.bnez, not zero: PASS
31c.bnez, zero: PASS
32c.li: PASS
33c.li, sign extend: PASS
34c.lui: PASS
35c.addi: PASS
36c.addiw: PASS
37c.addiw, overflow: PASS
38c.addiw, truncate: PASS
39c.addi16sp: PASS
40c.addi4spn: PASS
41c.slli: PASS
42c.slli, overflow: PASS
43c.srli: PASS
44c.srli, overflow: PASS
45c.srli, -1: PASS
46c.srai: PASS
47c.srai, overflow: PASS
48c.srai, -1: PASS
49c.andi (0): PASS
50c.andi (1): PASS
51c.mv: PASS
52c.add: PASS
53c.and (0): PASS
54c.and (-1): PASS
55c.or (1): PASS
56c.or (A): PASS
57c.xor (1): PASS
58c.xor (0): PASS
59c.sub: PASS
60c.addw: PASS
61c.addw, overflow: PASS
62c.addw, truncate: PASS
63c.subw: PASS
64c.subw, "overflow": PASS
65c.subw, truncate: PASS
66Exiting @ tick 2280417 because exiting with last active thread context
67