xref: /gem5/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000139                       # Number of seconds simulated
sim_ticks                                   138549500                       # Number of ticks simulated
final_tick                                  138549500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 338688                       # Simulator instruction rate (inst/s)
host_op_rate                                   338651                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              708977788                       # Simulator tick rate (ticks/s)
host_mem_usage                                 242940                       # Number of bytes of host memory used
host_seconds                                     0.20                       # Real time elapsed on the host
sim_insts                                       66173                       # Number of instructions simulated
sim_ops                                         66173                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED    138549500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst             33600                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data             16064                       # Number of bytes read from this memory
system.physmem.bytes_read::total                49664                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        33600                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           33600                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst                525                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data                251                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   776                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst            242512604                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            115944121                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               358456725                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst       242512604                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total          242512604                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst           242512604                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           115944121                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              358456725                       # Total bandwidth to/from this memory (bytes/s)
system.pwrStateResidencyTicks::UNDEFINED    138549500                       # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                    9                       # Number of system calls
system.cpu.pwrStateResidencyTicks::ON       138549500                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                           277099                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                       66173                       # Number of instructions committed
system.cpu.committedOps                         66173                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses                 66174                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
system.cpu.num_func_calls                        5169                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts        10311                       # number of instructions that are conditional controls
system.cpu.num_int_insts                        66174                       # number of integer instructions
system.cpu.num_fp_insts                             0                       # number of float instructions
system.cpu.num_int_register_reads               89437                       # number of times the integer registers were read
system.cpu.num_int_register_writes              43419                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
system.cpu.num_mem_refs                         24255                       # number of memory refs
system.cpu.num_load_insts                       11810                       # Number of load instructions
system.cpu.num_store_insts                      12445                       # Number of store instructions
system.cpu.num_idle_cycles                          0                       # Number of idle cycles
system.cpu.num_busy_cycles                     277099                       # Number of busy cycles
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.Branches                             15480                       # Number of branches fetched
system.cpu.op_class::No_OpClass                     9      0.01%      0.01% # Class of executed instruction
system.cpu.op_class::IntAlu                     41896     63.30%     63.32% # Class of executed instruction
system.cpu.op_class::IntMult                       15      0.02%     63.34% # Class of executed instruction
system.cpu.op_class::IntDiv                         8      0.01%     63.35% # Class of executed instruction
system.cpu.op_class::FloatAdd                       0      0.00%     63.35% # Class of executed instruction
system.cpu.op_class::FloatCmp                       0      0.00%     63.35% # Class of executed instruction
system.cpu.op_class::FloatCvt                       0      0.00%     63.35% # Class of executed instruction
system.cpu.op_class::FloatMult                      0      0.00%     63.35% # Class of executed instruction
system.cpu.op_class::FloatMultAcc                   0      0.00%     63.35% # Class of executed instruction
system.cpu.op_class::FloatDiv                       0      0.00%     63.35% # Class of executed instruction
system.cpu.op_class::FloatMisc                      0      0.00%     63.35% # Class of executed instruction
system.cpu.op_class::FloatSqrt                      0      0.00%     63.35% # Class of executed instruction
system.cpu.op_class::SimdAdd                        0      0.00%     63.35% # Class of executed instruction
system.cpu.op_class::SimdAddAcc                     0      0.00%     63.35% # Class of executed instruction
system.cpu.op_class::SimdAlu                        0      0.00%     63.35% # Class of executed instruction
system.cpu.op_class::SimdCmp                        0      0.00%     63.35% # Class of executed instruction
system.cpu.op_class::SimdCvt                        0      0.00%     63.35% # Class of executed instruction
system.cpu.op_class::SimdMisc                       0      0.00%     63.35% # Class of executed instruction
system.cpu.op_class::SimdMult                       0      0.00%     63.35% # Class of executed instruction
system.cpu.op_class::SimdMultAcc                    0      0.00%     63.35% # Class of executed instruction
system.cpu.op_class::SimdShift                      0      0.00%     63.35% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc                   0      0.00%     63.35% # Class of executed instruction
system.cpu.op_class::SimdSqrt                       0      0.00%     63.35% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd                   0      0.00%     63.35% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu                   0      0.00%     63.35% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp                   0      0.00%     63.35% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt                   0      0.00%     63.35% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv                   0      0.00%     63.35% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc                  0      0.00%     63.35% # Class of executed instruction
system.cpu.op_class::SimdFloatMult                  0      0.00%     63.35% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc               0      0.00%     63.35% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt                  0      0.00%     63.35% # Class of executed instruction
system.cpu.op_class::MemRead                    11810     17.84%     81.20% # Class of executed instruction
system.cpu.op_class::MemWrite                   12445     18.80%    100.00% # Class of executed instruction
system.cpu.op_class::FloatMemRead                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::FloatMemWrite                  0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::total                      66183                       # Class of executed instruction
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED    138549500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements                 0                       # number of replacements
system.cpu.dcache.tags.tagsinuse           195.060322                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs               24002                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs               251                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             95.625498                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   195.060322                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.047622                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.047622                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          251                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0            4                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           52                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          195                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.061279                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses             48757                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses            48757                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED    138549500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data        11758                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total           11758                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data        12243                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total          12243                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data            1                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total            1                       # number of LoadLockedReq hits
system.cpu.dcache.demand_hits::cpu.data         24001                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total            24001                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data        24001                       # number of overall hits
system.cpu.dcache.overall_hits::total           24001                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data           51                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total            51                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data          200                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total          200                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data          251                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total            251                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data          251                       # number of overall misses
system.cpu.dcache.overall_misses::total           251                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data      3213000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total      3213000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data     12600000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total     12600000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data     15813000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total     15813000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data     15813000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total     15813000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data        11809                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total        11809                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data        12443                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total        12443                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data            1                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total            1                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data        24252                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total        24252                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data        24252                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total        24252                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004319                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.004319                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.016073                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.016073                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.010350                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.010350                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.010350                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.010350                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        63000                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total        63000                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        63000                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total        63000                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data        63000                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total        63000                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data        63000                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total        63000                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.ReadReq_mshr_misses::cpu.data           51                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total           51                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data          200                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total          200                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data          251                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total          251                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data          251                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total          251                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      3162000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total      3162000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     12400000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total     12400000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data     15562000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total     15562000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data     15562000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total     15562000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.004319                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.004319                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.016073                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.016073                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.010350                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.010350                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.010350                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.010350                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        62000                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        62000                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        62000                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        62000                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        62000                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total        62000                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        62000                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total        62000                       # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED    138549500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements                10                       # number of replacements
system.cpu.icache.tags.tagsinuse           190.684855                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs               65659                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               525                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs            125.064762                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   190.684855                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.093108                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.093108                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          515                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          346                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          103                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.251465                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses            132893                       # Number of tag accesses
system.cpu.icache.tags.data_accesses           132893                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED    138549500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst        65659                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total           65659                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst         65659                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total            65659                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst        65659                       # number of overall hits
system.cpu.icache.overall_hits::total           65659                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          525                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           525                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          525                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            525                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          525                       # number of overall misses
system.cpu.icache.overall_misses::total           525                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     33076500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     33076500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     33076500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     33076500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     33076500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     33076500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst        66184                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total        66184                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst        66184                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total        66184                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst        66184                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total        66184                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.007932                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.007932                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.007932                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.007932                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.007932                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.007932                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63002.857143                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 63002.857143                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 63002.857143                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 63002.857143                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 63002.857143                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 63002.857143                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks           10                       # number of writebacks
system.cpu.icache.writebacks::total                10                       # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          525                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          525                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          525                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          525                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          525                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          525                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     32551500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     32551500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     32551500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     32551500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     32551500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     32551500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.007932                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.007932                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.007932                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.007932                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.007932                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.007932                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62002.857143                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62002.857143                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62002.857143                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 62002.857143                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62002.857143                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 62002.857143                       # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED    138549500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse          386.887852                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs                 10                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs              776                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             0.012887                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst   191.808508                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data   195.079344                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005854                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.005953                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.011807                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024          776                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           70                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          405                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          301                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.023682                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses             7064                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses            7064                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED    138549500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackClean_hits::writebacks           10                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total           10                       # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_misses::cpu.data          200                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total          200                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          525                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total          525                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data           51                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total           51                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst          525                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data          251                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total           776                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          525                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data          251                       # number of overall misses
system.cpu.l2cache.overall_misses::total          776                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     12100000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total     12100000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     31763500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total     31763500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      3085500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total      3085500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     31763500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data     15185500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total     46949000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     31763500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data     15185500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total     46949000                       # number of overall miss cycles
system.cpu.l2cache.WritebackClean_accesses::writebacks           10                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total           10                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data          200                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total          200                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          525                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total          525                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data           51                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total           51                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          525                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data          251                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total          776                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          525                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data          251                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total          776                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst            1                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total            1                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total            1                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total            1                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        60500                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total        60500                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.904762                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.904762                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data        60500                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total        60500                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.904762                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data        60500                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 60501.288660                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.904762                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data        60500                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 60501.288660                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          200                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total          200                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          525                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total          525                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           51                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total           51                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          525                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data          251                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total          776                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          525                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data          251                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total          776                       # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     10100000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     10100000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     26513500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     26513500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      2575500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      2575500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     26513500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     12675500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total     39189000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     26513500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     12675500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total     39189000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        50500                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        50500                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.904762                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.904762                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        50500                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        50500                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.904762                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        50500                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.288660                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.904762                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        50500                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.288660                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests          786                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests           10                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED    138549500                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp           576                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean           10                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq          200                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp          200                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq          525                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq           51                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1060                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          502                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total              1562                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        34240                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        16064                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total              50304                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples          776                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean               0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                776    100.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total            776                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy         403000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy        787500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.6                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy        376500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.3                       # Layer utilization (%)
system.membus.snoop_filter.tot_requests           776                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED    138549500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp                576                       # Transaction distribution
system.membus.trans_dist::ReadExReq               200                       # Transaction distribution
system.membus.trans_dist::ReadExResp              200                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq           576                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         1552                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                   1552                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        49664                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                   49664                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples               776                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                     776    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total                 776                       # Request fanout histogram
system.membus.reqLayer0.occupancy              777000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.6                       # Layer utilization (%)
system.membus.respLayer1.occupancy            3880000                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              2.8                       # Layer utilization (%)

---------- End Simulation Statistics   ----------