stats.txt revision 9729:e2fafd224f43
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000028 # Number of seconds simulated 4sim_ticks 28358000 # Number of ticks simulated 5final_tick 28358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 90736 # Simulator instruction rate (inst/s) 8host_op_rate 164316 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 477859669 # Simulator tick rate (ticks/s) 10host_mem_usage 289160 # Number of bytes of host memory used 11host_seconds 0.06 # Real time elapsed on the host 12sim_insts 5381 # Number of instructions simulated 13sim_ops 9748 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory 16system.physmem.bytes_read::total 23104 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 14528 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 14528 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 361 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 512306933 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 302419070 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 814726003 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 512306933 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 512306933 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 512306933 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 302419070 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 814726003 # Total bandwidth to/from this memory (bytes/s) 30system.membus.throughput 814726003 # Throughput (bytes/s) 31system.membus.trans_dist::ReadReq 282 # Transaction distribution 32system.membus.trans_dist::ReadResp 282 # Transaction distribution 33system.membus.trans_dist::ReadExReq 79 # Transaction distribution 34system.membus.trans_dist::ReadExResp 79 # Transaction distribution 35system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes) 36system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes) 37system.membus.pkt_count::system.physmem.port 722 # Packet count per connected master and slave (bytes) 38system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes) 39system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes) 40system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes) 41system.membus.tot_pkt_size::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes) 42system.membus.tot_pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes) 43system.membus.data_through_bus 23104 # Total data (bytes) 44system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 45system.membus.reqLayer0.occupancy 361000 # Layer occupancy (ticks) 46system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) 47system.membus.respLayer1.occupancy 3249000 # Layer occupancy (ticks) 48system.membus.respLayer1.utilization 11.5 # Layer utilization (%) 49system.cpu.workload.num_syscalls 11 # Number of system calls 50system.cpu.numCycles 56716 # number of cpu cycles simulated 51system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 52system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 53system.cpu.committedInsts 5381 # Number of instructions committed 54system.cpu.committedOps 9748 # Number of ops (including micro ops) committed 55system.cpu.num_int_alu_accesses 9655 # Number of integer alu accesses 56system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 57system.cpu.num_func_calls 209 # number of times a function call or return occured 58system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls 59system.cpu.num_int_insts 9655 # number of integer instructions 60system.cpu.num_fp_insts 0 # number of float instructions 61system.cpu.num_int_register_reads 24822 # number of times the integer registers were read 62system.cpu.num_int_register_writes 11063 # number of times the integer registers were written 63system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 64system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 65system.cpu.num_mem_refs 1988 # number of memory refs 66system.cpu.num_load_insts 1053 # Number of load instructions 67system.cpu.num_store_insts 935 # Number of store instructions 68system.cpu.num_idle_cycles 0 # Number of idle cycles 69system.cpu.num_busy_cycles 56716 # Number of busy cycles 70system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 71system.cpu.idle_fraction 0 # Percentage of idle cycles 72system.cpu.icache.replacements 0 # number of replacements 73system.cpu.icache.tagsinuse 105.550219 # Cycle average of tags in use 74system.cpu.icache.total_refs 6637 # Total number of references to valid blocks. 75system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks. 76system.cpu.icache.avg_refs 29.109649 # Average number of references to valid blocks. 77system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 78system.cpu.icache.occ_blocks::cpu.inst 105.550219 # Average occupied blocks per requestor 79system.cpu.icache.occ_percent::cpu.inst 0.051538 # Average percentage of cache occupancy 80system.cpu.icache.occ_percent::total 0.051538 # Average percentage of cache occupancy 81system.cpu.icache.ReadReq_hits::cpu.inst 6637 # number of ReadReq hits 82system.cpu.icache.ReadReq_hits::total 6637 # number of ReadReq hits 83system.cpu.icache.demand_hits::cpu.inst 6637 # number of demand (read+write) hits 84system.cpu.icache.demand_hits::total 6637 # number of demand (read+write) hits 85system.cpu.icache.overall_hits::cpu.inst 6637 # number of overall hits 86system.cpu.icache.overall_hits::total 6637 # number of overall hits 87system.cpu.icache.ReadReq_misses::cpu.inst 228 # number of ReadReq misses 88system.cpu.icache.ReadReq_misses::total 228 # number of ReadReq misses 89system.cpu.icache.demand_misses::cpu.inst 228 # number of demand (read+write) misses 90system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses 91system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses 92system.cpu.icache.overall_misses::total 228 # number of overall misses 93system.cpu.icache.ReadReq_miss_latency::cpu.inst 12498000 # number of ReadReq miss cycles 94system.cpu.icache.ReadReq_miss_latency::total 12498000 # number of ReadReq miss cycles 95system.cpu.icache.demand_miss_latency::cpu.inst 12498000 # number of demand (read+write) miss cycles 96system.cpu.icache.demand_miss_latency::total 12498000 # number of demand (read+write) miss cycles 97system.cpu.icache.overall_miss_latency::cpu.inst 12498000 # number of overall miss cycles 98system.cpu.icache.overall_miss_latency::total 12498000 # number of overall miss cycles 99system.cpu.icache.ReadReq_accesses::cpu.inst 6865 # number of ReadReq accesses(hits+misses) 100system.cpu.icache.ReadReq_accesses::total 6865 # number of ReadReq accesses(hits+misses) 101system.cpu.icache.demand_accesses::cpu.inst 6865 # number of demand (read+write) accesses 102system.cpu.icache.demand_accesses::total 6865 # number of demand (read+write) accesses 103system.cpu.icache.overall_accesses::cpu.inst 6865 # number of overall (read+write) accesses 104system.cpu.icache.overall_accesses::total 6865 # number of overall (read+write) accesses 105system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.033212 # miss rate for ReadReq accesses 106system.cpu.icache.ReadReq_miss_rate::total 0.033212 # miss rate for ReadReq accesses 107system.cpu.icache.demand_miss_rate::cpu.inst 0.033212 # miss rate for demand accesses 108system.cpu.icache.demand_miss_rate::total 0.033212 # miss rate for demand accesses 109system.cpu.icache.overall_miss_rate::cpu.inst 0.033212 # miss rate for overall accesses 110system.cpu.icache.overall_miss_rate::total 0.033212 # miss rate for overall accesses 111system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54815.789474 # average ReadReq miss latency 112system.cpu.icache.ReadReq_avg_miss_latency::total 54815.789474 # average ReadReq miss latency 113system.cpu.icache.demand_avg_miss_latency::cpu.inst 54815.789474 # average overall miss latency 114system.cpu.icache.demand_avg_miss_latency::total 54815.789474 # average overall miss latency 115system.cpu.icache.overall_avg_miss_latency::cpu.inst 54815.789474 # average overall miss latency 116system.cpu.icache.overall_avg_miss_latency::total 54815.789474 # average overall miss latency 117system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 118system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 119system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 120system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 121system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 122system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 123system.cpu.icache.fast_writes 0 # number of fast writes performed 124system.cpu.icache.cache_copies 0 # number of cache copies performed 125system.cpu.icache.ReadReq_mshr_misses::cpu.inst 228 # number of ReadReq MSHR misses 126system.cpu.icache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses 127system.cpu.icache.demand_mshr_misses::cpu.inst 228 # number of demand (read+write) MSHR misses 128system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses 129system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses 130system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses 131system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12042000 # number of ReadReq MSHR miss cycles 132system.cpu.icache.ReadReq_mshr_miss_latency::total 12042000 # number of ReadReq MSHR miss cycles 133system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12042000 # number of demand (read+write) MSHR miss cycles 134system.cpu.icache.demand_mshr_miss_latency::total 12042000 # number of demand (read+write) MSHR miss cycles 135system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12042000 # number of overall MSHR miss cycles 136system.cpu.icache.overall_mshr_miss_latency::total 12042000 # number of overall MSHR miss cycles 137system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for ReadReq accesses 138system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033212 # mshr miss rate for ReadReq accesses 139system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for demand accesses 140system.cpu.icache.demand_mshr_miss_rate::total 0.033212 # mshr miss rate for demand accesses 141system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for overall accesses 142system.cpu.icache.overall_mshr_miss_rate::total 0.033212 # mshr miss rate for overall accesses 143system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52815.789474 # average ReadReq mshr miss latency 144system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52815.789474 # average ReadReq mshr miss latency 145system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency 146system.cpu.icache.demand_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency 147system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency 148system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency 149system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 150system.cpu.l2cache.replacements 0 # number of replacements 151system.cpu.l2cache.tagsinuse 134.034140 # Cycle average of tags in use 152system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. 153system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks. 154system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks. 155system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 156system.cpu.l2cache.occ_blocks::cpu.inst 105.558330 # Average occupied blocks per requestor 157system.cpu.l2cache.occ_blocks::cpu.data 28.475810 # Average occupied blocks per requestor 158system.cpu.l2cache.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy 159system.cpu.l2cache.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy 160system.cpu.l2cache.occ_percent::total 0.004090 # Average percentage of cache occupancy 161system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 162system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 163system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 164system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 165system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 166system.cpu.l2cache.overall_hits::total 1 # number of overall hits 167system.cpu.l2cache.ReadReq_misses::cpu.inst 227 # number of ReadReq misses 168system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses 169system.cpu.l2cache.ReadReq_misses::total 282 # number of ReadReq misses 170system.cpu.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses 171system.cpu.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses 172system.cpu.l2cache.demand_misses::cpu.inst 227 # number of demand (read+write) misses 173system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses 174system.cpu.l2cache.demand_misses::total 361 # number of demand (read+write) misses 175system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses 176system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses 177system.cpu.l2cache.overall_misses::total 361 # number of overall misses 178system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11804000 # number of ReadReq miss cycles 179system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2860000 # number of ReadReq miss cycles 180system.cpu.l2cache.ReadReq_miss_latency::total 14664000 # number of ReadReq miss cycles 181system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4108000 # number of ReadExReq miss cycles 182system.cpu.l2cache.ReadExReq_miss_latency::total 4108000 # number of ReadExReq miss cycles 183system.cpu.l2cache.demand_miss_latency::cpu.inst 11804000 # number of demand (read+write) miss cycles 184system.cpu.l2cache.demand_miss_latency::cpu.data 6968000 # number of demand (read+write) miss cycles 185system.cpu.l2cache.demand_miss_latency::total 18772000 # number of demand (read+write) miss cycles 186system.cpu.l2cache.overall_miss_latency::cpu.inst 11804000 # number of overall miss cycles 187system.cpu.l2cache.overall_miss_latency::cpu.data 6968000 # number of overall miss cycles 188system.cpu.l2cache.overall_miss_latency::total 18772000 # number of overall miss cycles 189system.cpu.l2cache.ReadReq_accesses::cpu.inst 228 # number of ReadReq accesses(hits+misses) 190system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) 191system.cpu.l2cache.ReadReq_accesses::total 283 # number of ReadReq accesses(hits+misses) 192system.cpu.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) 193system.cpu.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) 194system.cpu.l2cache.demand_accesses::cpu.inst 228 # number of demand (read+write) accesses 195system.cpu.l2cache.demand_accesses::cpu.data 134 # number of demand (read+write) accesses 196system.cpu.l2cache.demand_accesses::total 362 # number of demand (read+write) accesses 197system.cpu.l2cache.overall_accesses::cpu.inst 228 # number of overall (read+write) accesses 198system.cpu.l2cache.overall_accesses::cpu.data 134 # number of overall (read+write) accesses 199system.cpu.l2cache.overall_accesses::total 362 # number of overall (read+write) accesses 200system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.995614 # miss rate for ReadReq accesses 201system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 202system.cpu.l2cache.ReadReq_miss_rate::total 0.996466 # miss rate for ReadReq accesses 203system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 204system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 205system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995614 # miss rate for demand accesses 206system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 207system.cpu.l2cache.demand_miss_rate::total 0.997238 # miss rate for demand accesses 208system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses 209system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 210system.cpu.l2cache.overall_miss_rate::total 0.997238 # miss rate for overall accesses 211system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 212system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 213system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 214system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 215system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 216system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 217system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 218system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 219system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 220system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 221system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency 222system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 223system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 224system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 225system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 226system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 227system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 228system.cpu.l2cache.fast_writes 0 # number of fast writes performed 229system.cpu.l2cache.cache_copies 0 # number of cache copies performed 230system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 227 # number of ReadReq MSHR misses 231system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses 232system.cpu.l2cache.ReadReq_mshr_misses::total 282 # number of ReadReq MSHR misses 233system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses 234system.cpu.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses 235system.cpu.l2cache.demand_mshr_misses::cpu.inst 227 # number of demand (read+write) MSHR misses 236system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses 237system.cpu.l2cache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses 238system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses 239system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses 240system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses 241system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9080000 # number of ReadReq MSHR miss cycles 242system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2200000 # number of ReadReq MSHR miss cycles 243system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11280000 # number of ReadReq MSHR miss cycles 244system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3160000 # number of ReadExReq MSHR miss cycles 245system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3160000 # number of ReadExReq MSHR miss cycles 246system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9080000 # number of demand (read+write) MSHR miss cycles 247system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles 248system.cpu.l2cache.demand_mshr_miss_latency::total 14440000 # number of demand (read+write) MSHR miss cycles 249system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9080000 # number of overall MSHR miss cycles 250system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles 251system.cpu.l2cache.overall_mshr_miss_latency::total 14440000 # number of overall MSHR miss cycles 252system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadReq accesses 253system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 254system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.996466 # mshr miss rate for ReadReq accesses 255system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 256system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 257system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for demand accesses 258system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 259system.cpu.l2cache.demand_mshr_miss_rate::total 0.997238 # mshr miss rate for demand accesses 260system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses 261system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 262system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 # mshr miss rate for overall accesses 263system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 264system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 265system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 266system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 267system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 268system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 269system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 270system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 271system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 272system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 273system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 274system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 275system.cpu.dcache.replacements 0 # number of replacements 276system.cpu.dcache.tagsinuse 80.797237 # Cycle average of tags in use 277system.cpu.dcache.total_refs 1854 # Total number of references to valid blocks. 278system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks. 279system.cpu.dcache.avg_refs 13.835821 # Average number of references to valid blocks. 280system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 281system.cpu.dcache.occ_blocks::cpu.data 80.797237 # Average occupied blocks per requestor 282system.cpu.dcache.occ_percent::cpu.data 0.019726 # Average percentage of cache occupancy 283system.cpu.dcache.occ_percent::total 0.019726 # Average percentage of cache occupancy 284system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits 285system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits 286system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits 287system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits 288system.cpu.dcache.demand_hits::cpu.data 1854 # number of demand (read+write) hits 289system.cpu.dcache.demand_hits::total 1854 # number of demand (read+write) hits 290system.cpu.dcache.overall_hits::cpu.data 1854 # number of overall hits 291system.cpu.dcache.overall_hits::total 1854 # number of overall hits 292system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses 293system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses 294system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses 295system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses 296system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses 297system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses 298system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses 299system.cpu.dcache.overall_misses::total 134 # number of overall misses 300system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles 301system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles 302system.cpu.dcache.WriteReq_miss_latency::cpu.data 4345000 # number of WriteReq miss cycles 303system.cpu.dcache.WriteReq_miss_latency::total 4345000 # number of WriteReq miss cycles 304system.cpu.dcache.demand_miss_latency::cpu.data 7370000 # number of demand (read+write) miss cycles 305system.cpu.dcache.demand_miss_latency::total 7370000 # number of demand (read+write) miss cycles 306system.cpu.dcache.overall_miss_latency::cpu.data 7370000 # number of overall miss cycles 307system.cpu.dcache.overall_miss_latency::total 7370000 # number of overall miss cycles 308system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses) 309system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses) 310system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) 311system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) 312system.cpu.dcache.demand_accesses::cpu.data 1988 # number of demand (read+write) accesses 313system.cpu.dcache.demand_accesses::total 1988 # number of demand (read+write) accesses 314system.cpu.dcache.overall_accesses::cpu.data 1988 # number of overall (read+write) accesses 315system.cpu.dcache.overall_accesses::total 1988 # number of overall (read+write) accesses 316system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052232 # miss rate for ReadReq accesses 317system.cpu.dcache.ReadReq_miss_rate::total 0.052232 # miss rate for ReadReq accesses 318system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses 319system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses 320system.cpu.dcache.demand_miss_rate::cpu.data 0.067404 # miss rate for demand accesses 321system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses 322system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses 323system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses 324system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency 325system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency 326system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency 327system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency 328system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency 329system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency 330system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency 331system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency 332system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 333system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 334system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 335system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 336system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 337system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 338system.cpu.dcache.fast_writes 0 # number of fast writes performed 339system.cpu.dcache.cache_copies 0 # number of cache copies performed 340system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses 341system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses 342system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses 343system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses 344system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses 345system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses 346system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses 347system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses 348system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles 349system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles 350system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4187000 # number of WriteReq MSHR miss cycles 351system.cpu.dcache.WriteReq_mshr_miss_latency::total 4187000 # number of WriteReq MSHR miss cycles 352system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7102000 # number of demand (read+write) MSHR miss cycles 353system.cpu.dcache.demand_mshr_miss_latency::total 7102000 # number of demand (read+write) MSHR miss cycles 354system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7102000 # number of overall MSHR miss cycles 355system.cpu.dcache.overall_mshr_miss_latency::total 7102000 # number of overall MSHR miss cycles 356system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses 357system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses 358system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses 359system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses 360system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for demand accesses 361system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses 362system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses 363system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses 364system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency 365system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency 366system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 367system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 368system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 369system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 370system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 371system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 372system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 373system.cpu.toL2Bus.throughput 816982862 # Throughput (bytes/s) 374system.cpu.toL2Bus.trans_dist::ReadReq 283 # Transaction distribution 375system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution 376system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution 377system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution 378system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 456 # Packet count per connected master and slave (bytes) 379system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 268 # Packet count per connected master and slave (bytes) 380system.cpu.toL2Bus.pkt_count 724 # Packet count per connected master and slave (bytes) 381system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 14592 # Cumulative packet size per connected master and slave (bytes) 382system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8576 # Cumulative packet size per connected master and slave (bytes) 383system.cpu.toL2Bus.tot_pkt_size 23168 # Cumulative packet size per connected master and slave (bytes) 384system.cpu.toL2Bus.data_through_bus 23168 # Total data (bytes) 385system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 386system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks) 387system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 388system.cpu.toL2Bus.respLayer0.occupancy 342000 # Layer occupancy (ticks) 389system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%) 390system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks) 391system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) 392 393---------- End Simulation Statistics ---------- 394