stats.txt revision 9702:094d0280e481
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000028 # Number of seconds simulated 4sim_ticks 28358000 # Number of ticks simulated 5final_tick 28358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 90736 # Simulator instruction rate (inst/s) 8host_op_rate 164316 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 477859669 # Simulator tick rate (ticks/s) 10host_mem_usage 289160 # Number of bytes of host memory used 11host_seconds 0.06 # Real time elapsed on the host 12sim_insts 5381 # Number of instructions simulated 13sim_ops 9748 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory 16system.physmem.bytes_read::total 23104 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 14528 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 14528 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 361 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 512306933 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 302419070 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 814726003 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 512306933 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 512306933 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 512306933 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 302419070 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 814726003 # Total bandwidth to/from this memory (bytes/s) 30system.cpu.workload.num_syscalls 11 # Number of system calls 31system.cpu.numCycles 56716 # number of cpu cycles simulated 32system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 33system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 34system.cpu.committedInsts 5381 # Number of instructions committed 35system.cpu.committedOps 9748 # Number of ops (including micro ops) committed 36system.cpu.num_int_alu_accesses 9655 # Number of integer alu accesses 37system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 38system.cpu.num_func_calls 209 # number of times a function call or return occured 39system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls 40system.cpu.num_int_insts 9655 # number of integer instructions 41system.cpu.num_fp_insts 0 # number of float instructions 42system.cpu.num_int_register_reads 24822 # number of times the integer registers were read 43system.cpu.num_int_register_writes 11063 # number of times the integer registers were written 44system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 45system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 46system.cpu.num_mem_refs 1988 # number of memory refs 47system.cpu.num_load_insts 1053 # Number of load instructions 48system.cpu.num_store_insts 935 # Number of store instructions 49system.cpu.num_idle_cycles 0 # Number of idle cycles 50system.cpu.num_busy_cycles 56716 # Number of busy cycles 51system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 52system.cpu.idle_fraction 0 # Percentage of idle cycles 53system.cpu.icache.replacements 0 # number of replacements 54system.cpu.icache.tagsinuse 105.550219 # Cycle average of tags in use 55system.cpu.icache.total_refs 6637 # Total number of references to valid blocks. 56system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks. 57system.cpu.icache.avg_refs 29.109649 # Average number of references to valid blocks. 58system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 59system.cpu.icache.occ_blocks::cpu.inst 105.550219 # Average occupied blocks per requestor 60system.cpu.icache.occ_percent::cpu.inst 0.051538 # Average percentage of cache occupancy 61system.cpu.icache.occ_percent::total 0.051538 # Average percentage of cache occupancy 62system.cpu.icache.ReadReq_hits::cpu.inst 6637 # number of ReadReq hits 63system.cpu.icache.ReadReq_hits::total 6637 # number of ReadReq hits 64system.cpu.icache.demand_hits::cpu.inst 6637 # number of demand (read+write) hits 65system.cpu.icache.demand_hits::total 6637 # number of demand (read+write) hits 66system.cpu.icache.overall_hits::cpu.inst 6637 # number of overall hits 67system.cpu.icache.overall_hits::total 6637 # number of overall hits 68system.cpu.icache.ReadReq_misses::cpu.inst 228 # number of ReadReq misses 69system.cpu.icache.ReadReq_misses::total 228 # number of ReadReq misses 70system.cpu.icache.demand_misses::cpu.inst 228 # number of demand (read+write) misses 71system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses 72system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses 73system.cpu.icache.overall_misses::total 228 # number of overall misses 74system.cpu.icache.ReadReq_miss_latency::cpu.inst 12498000 # number of ReadReq miss cycles 75system.cpu.icache.ReadReq_miss_latency::total 12498000 # number of ReadReq miss cycles 76system.cpu.icache.demand_miss_latency::cpu.inst 12498000 # number of demand (read+write) miss cycles 77system.cpu.icache.demand_miss_latency::total 12498000 # number of demand (read+write) miss cycles 78system.cpu.icache.overall_miss_latency::cpu.inst 12498000 # number of overall miss cycles 79system.cpu.icache.overall_miss_latency::total 12498000 # number of overall miss cycles 80system.cpu.icache.ReadReq_accesses::cpu.inst 6865 # number of ReadReq accesses(hits+misses) 81system.cpu.icache.ReadReq_accesses::total 6865 # number of ReadReq accesses(hits+misses) 82system.cpu.icache.demand_accesses::cpu.inst 6865 # number of demand (read+write) accesses 83system.cpu.icache.demand_accesses::total 6865 # number of demand (read+write) accesses 84system.cpu.icache.overall_accesses::cpu.inst 6865 # number of overall (read+write) accesses 85system.cpu.icache.overall_accesses::total 6865 # number of overall (read+write) accesses 86system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.033212 # miss rate for ReadReq accesses 87system.cpu.icache.ReadReq_miss_rate::total 0.033212 # miss rate for ReadReq accesses 88system.cpu.icache.demand_miss_rate::cpu.inst 0.033212 # miss rate for demand accesses 89system.cpu.icache.demand_miss_rate::total 0.033212 # miss rate for demand accesses 90system.cpu.icache.overall_miss_rate::cpu.inst 0.033212 # miss rate for overall accesses 91system.cpu.icache.overall_miss_rate::total 0.033212 # miss rate for overall accesses 92system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54815.789474 # average ReadReq miss latency 93system.cpu.icache.ReadReq_avg_miss_latency::total 54815.789474 # average ReadReq miss latency 94system.cpu.icache.demand_avg_miss_latency::cpu.inst 54815.789474 # average overall miss latency 95system.cpu.icache.demand_avg_miss_latency::total 54815.789474 # average overall miss latency 96system.cpu.icache.overall_avg_miss_latency::cpu.inst 54815.789474 # average overall miss latency 97system.cpu.icache.overall_avg_miss_latency::total 54815.789474 # average overall miss latency 98system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 99system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 100system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 101system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 102system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 103system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 104system.cpu.icache.fast_writes 0 # number of fast writes performed 105system.cpu.icache.cache_copies 0 # number of cache copies performed 106system.cpu.icache.ReadReq_mshr_misses::cpu.inst 228 # number of ReadReq MSHR misses 107system.cpu.icache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses 108system.cpu.icache.demand_mshr_misses::cpu.inst 228 # number of demand (read+write) MSHR misses 109system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses 110system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses 111system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses 112system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12042000 # number of ReadReq MSHR miss cycles 113system.cpu.icache.ReadReq_mshr_miss_latency::total 12042000 # number of ReadReq MSHR miss cycles 114system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12042000 # number of demand (read+write) MSHR miss cycles 115system.cpu.icache.demand_mshr_miss_latency::total 12042000 # number of demand (read+write) MSHR miss cycles 116system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12042000 # number of overall MSHR miss cycles 117system.cpu.icache.overall_mshr_miss_latency::total 12042000 # number of overall MSHR miss cycles 118system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for ReadReq accesses 119system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033212 # mshr miss rate for ReadReq accesses 120system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for demand accesses 121system.cpu.icache.demand_mshr_miss_rate::total 0.033212 # mshr miss rate for demand accesses 122system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for overall accesses 123system.cpu.icache.overall_mshr_miss_rate::total 0.033212 # mshr miss rate for overall accesses 124system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52815.789474 # average ReadReq mshr miss latency 125system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52815.789474 # average ReadReq mshr miss latency 126system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency 127system.cpu.icache.demand_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency 128system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency 129system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency 130system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 131system.cpu.l2cache.replacements 0 # number of replacements 132system.cpu.l2cache.tagsinuse 134.034140 # Cycle average of tags in use 133system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. 134system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks. 135system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks. 136system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 137system.cpu.l2cache.occ_blocks::cpu.inst 105.558330 # Average occupied blocks per requestor 138system.cpu.l2cache.occ_blocks::cpu.data 28.475810 # Average occupied blocks per requestor 139system.cpu.l2cache.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy 140system.cpu.l2cache.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy 141system.cpu.l2cache.occ_percent::total 0.004090 # Average percentage of cache occupancy 142system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 143system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 144system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 145system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 146system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 147system.cpu.l2cache.overall_hits::total 1 # number of overall hits 148system.cpu.l2cache.ReadReq_misses::cpu.inst 227 # number of ReadReq misses 149system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses 150system.cpu.l2cache.ReadReq_misses::total 282 # number of ReadReq misses 151system.cpu.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses 152system.cpu.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses 153system.cpu.l2cache.demand_misses::cpu.inst 227 # number of demand (read+write) misses 154system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses 155system.cpu.l2cache.demand_misses::total 361 # number of demand (read+write) misses 156system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses 157system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses 158system.cpu.l2cache.overall_misses::total 361 # number of overall misses 159system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11804000 # number of ReadReq miss cycles 160system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2860000 # number of ReadReq miss cycles 161system.cpu.l2cache.ReadReq_miss_latency::total 14664000 # number of ReadReq miss cycles 162system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4108000 # number of ReadExReq miss cycles 163system.cpu.l2cache.ReadExReq_miss_latency::total 4108000 # number of ReadExReq miss cycles 164system.cpu.l2cache.demand_miss_latency::cpu.inst 11804000 # number of demand (read+write) miss cycles 165system.cpu.l2cache.demand_miss_latency::cpu.data 6968000 # number of demand (read+write) miss cycles 166system.cpu.l2cache.demand_miss_latency::total 18772000 # number of demand (read+write) miss cycles 167system.cpu.l2cache.overall_miss_latency::cpu.inst 11804000 # number of overall miss cycles 168system.cpu.l2cache.overall_miss_latency::cpu.data 6968000 # number of overall miss cycles 169system.cpu.l2cache.overall_miss_latency::total 18772000 # number of overall miss cycles 170system.cpu.l2cache.ReadReq_accesses::cpu.inst 228 # number of ReadReq accesses(hits+misses) 171system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) 172system.cpu.l2cache.ReadReq_accesses::total 283 # number of ReadReq accesses(hits+misses) 173system.cpu.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) 174system.cpu.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) 175system.cpu.l2cache.demand_accesses::cpu.inst 228 # number of demand (read+write) accesses 176system.cpu.l2cache.demand_accesses::cpu.data 134 # number of demand (read+write) accesses 177system.cpu.l2cache.demand_accesses::total 362 # number of demand (read+write) accesses 178system.cpu.l2cache.overall_accesses::cpu.inst 228 # number of overall (read+write) accesses 179system.cpu.l2cache.overall_accesses::cpu.data 134 # number of overall (read+write) accesses 180system.cpu.l2cache.overall_accesses::total 362 # number of overall (read+write) accesses 181system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.995614 # miss rate for ReadReq accesses 182system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 183system.cpu.l2cache.ReadReq_miss_rate::total 0.996466 # miss rate for ReadReq accesses 184system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 185system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 186system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995614 # miss rate for demand accesses 187system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 188system.cpu.l2cache.demand_miss_rate::total 0.997238 # miss rate for demand accesses 189system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses 190system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 191system.cpu.l2cache.overall_miss_rate::total 0.997238 # miss rate for overall accesses 192system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 193system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 194system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 195system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 196system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 197system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 198system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 199system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 200system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 201system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 202system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency 203system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 204system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 205system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 206system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 207system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 208system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 209system.cpu.l2cache.fast_writes 0 # number of fast writes performed 210system.cpu.l2cache.cache_copies 0 # number of cache copies performed 211system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 227 # number of ReadReq MSHR misses 212system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses 213system.cpu.l2cache.ReadReq_mshr_misses::total 282 # number of ReadReq MSHR misses 214system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses 215system.cpu.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses 216system.cpu.l2cache.demand_mshr_misses::cpu.inst 227 # number of demand (read+write) MSHR misses 217system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses 218system.cpu.l2cache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses 219system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses 220system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses 221system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses 222system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9080000 # number of ReadReq MSHR miss cycles 223system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2200000 # number of ReadReq MSHR miss cycles 224system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11280000 # number of ReadReq MSHR miss cycles 225system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3160000 # number of ReadExReq MSHR miss cycles 226system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3160000 # number of ReadExReq MSHR miss cycles 227system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9080000 # number of demand (read+write) MSHR miss cycles 228system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles 229system.cpu.l2cache.demand_mshr_miss_latency::total 14440000 # number of demand (read+write) MSHR miss cycles 230system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9080000 # number of overall MSHR miss cycles 231system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles 232system.cpu.l2cache.overall_mshr_miss_latency::total 14440000 # number of overall MSHR miss cycles 233system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadReq accesses 234system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 235system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.996466 # mshr miss rate for ReadReq accesses 236system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 237system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 238system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for demand accesses 239system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 240system.cpu.l2cache.demand_mshr_miss_rate::total 0.997238 # mshr miss rate for demand accesses 241system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses 242system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 243system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 # mshr miss rate for overall accesses 244system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 245system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 246system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 247system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 248system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 249system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 250system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 251system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 252system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 253system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 254system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 255system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 256system.cpu.dcache.replacements 0 # number of replacements 257system.cpu.dcache.tagsinuse 80.797237 # Cycle average of tags in use 258system.cpu.dcache.total_refs 1854 # Total number of references to valid blocks. 259system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks. 260system.cpu.dcache.avg_refs 13.835821 # Average number of references to valid blocks. 261system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 262system.cpu.dcache.occ_blocks::cpu.data 80.797237 # Average occupied blocks per requestor 263system.cpu.dcache.occ_percent::cpu.data 0.019726 # Average percentage of cache occupancy 264system.cpu.dcache.occ_percent::total 0.019726 # Average percentage of cache occupancy 265system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits 266system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits 267system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits 268system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits 269system.cpu.dcache.demand_hits::cpu.data 1854 # number of demand (read+write) hits 270system.cpu.dcache.demand_hits::total 1854 # number of demand (read+write) hits 271system.cpu.dcache.overall_hits::cpu.data 1854 # number of overall hits 272system.cpu.dcache.overall_hits::total 1854 # number of overall hits 273system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses 274system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses 275system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses 276system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses 277system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses 278system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses 279system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses 280system.cpu.dcache.overall_misses::total 134 # number of overall misses 281system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles 282system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles 283system.cpu.dcache.WriteReq_miss_latency::cpu.data 4345000 # number of WriteReq miss cycles 284system.cpu.dcache.WriteReq_miss_latency::total 4345000 # number of WriteReq miss cycles 285system.cpu.dcache.demand_miss_latency::cpu.data 7370000 # number of demand (read+write) miss cycles 286system.cpu.dcache.demand_miss_latency::total 7370000 # number of demand (read+write) miss cycles 287system.cpu.dcache.overall_miss_latency::cpu.data 7370000 # number of overall miss cycles 288system.cpu.dcache.overall_miss_latency::total 7370000 # number of overall miss cycles 289system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses) 290system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses) 291system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) 292system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) 293system.cpu.dcache.demand_accesses::cpu.data 1988 # number of demand (read+write) accesses 294system.cpu.dcache.demand_accesses::total 1988 # number of demand (read+write) accesses 295system.cpu.dcache.overall_accesses::cpu.data 1988 # number of overall (read+write) accesses 296system.cpu.dcache.overall_accesses::total 1988 # number of overall (read+write) accesses 297system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052232 # miss rate for ReadReq accesses 298system.cpu.dcache.ReadReq_miss_rate::total 0.052232 # miss rate for ReadReq accesses 299system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses 300system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses 301system.cpu.dcache.demand_miss_rate::cpu.data 0.067404 # miss rate for demand accesses 302system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses 303system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses 304system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses 305system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency 306system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency 307system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency 308system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency 309system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency 310system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency 311system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency 312system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency 313system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 314system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 315system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 316system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 317system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 318system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 319system.cpu.dcache.fast_writes 0 # number of fast writes performed 320system.cpu.dcache.cache_copies 0 # number of cache copies performed 321system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses 322system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses 323system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses 324system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses 325system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses 326system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses 327system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses 328system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses 329system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles 330system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles 331system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4187000 # number of WriteReq MSHR miss cycles 332system.cpu.dcache.WriteReq_mshr_miss_latency::total 4187000 # number of WriteReq MSHR miss cycles 333system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7102000 # number of demand (read+write) MSHR miss cycles 334system.cpu.dcache.demand_mshr_miss_latency::total 7102000 # number of demand (read+write) MSHR miss cycles 335system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7102000 # number of overall MSHR miss cycles 336system.cpu.dcache.overall_mshr_miss_latency::total 7102000 # number of overall MSHR miss cycles 337system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses 338system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses 339system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses 340system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses 341system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for demand accesses 342system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses 343system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses 344system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses 345system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency 346system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency 347system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 348system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 349system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 350system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 351system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 352system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 353system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 354 355---------- End Simulation Statistics ---------- 356