stats.txt revision 10409:8c80b91944c5
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000028 # Number of seconds simulated 4sim_ticks 28358000 # Number of ticks simulated 5final_tick 28358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 307468 # Simulator instruction rate (inst/s) 8host_op_rate 556583 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1618053178 # Simulator tick rate (ticks/s) 10host_mem_usage 302528 # Number of bytes of host memory used 11host_seconds 0.02 # Real time elapsed on the host 12sim_insts 5381 # Number of instructions simulated 13sim_ops 9748 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory 18system.physmem.bytes_read::total 23104 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 14528 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 14528 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 361 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 512306933 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 302419070 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 814726003 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 512306933 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 512306933 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 512306933 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 302419070 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 814726003 # Total bandwidth to/from this memory (bytes/s) 32system.membus.trans_dist::ReadReq 282 # Transaction distribution 33system.membus.trans_dist::ReadResp 282 # Transaction distribution 34system.membus.trans_dist::ReadExReq 79 # Transaction distribution 35system.membus.trans_dist::ReadExResp 79 # Transaction distribution 36system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes) 37system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes) 38system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes) 39system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes) 40system.membus.pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes) 41system.membus.pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes) 42system.membus.snoops 0 # Total snoops (count) 43system.membus.snoop_fanout::samples 361 # Request fanout histogram 44system.membus.snoop_fanout::mean 0 # Request fanout histogram 45system.membus.snoop_fanout::stdev 0 # Request fanout histogram 46system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 47system.membus.snoop_fanout::0 361 100.00% 100.00% # Request fanout histogram 48system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 49system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 50system.membus.snoop_fanout::min_value 0 # Request fanout histogram 51system.membus.snoop_fanout::max_value 0 # Request fanout histogram 52system.membus.snoop_fanout::total 361 # Request fanout histogram 53system.membus.reqLayer0.occupancy 361000 # Layer occupancy (ticks) 54system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) 55system.membus.respLayer1.occupancy 3249000 # Layer occupancy (ticks) 56system.membus.respLayer1.utilization 11.5 # Layer utilization (%) 57system.cpu_clk_domain.clock 500 # Clock period in ticks 58system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 59system.cpu.workload.num_syscalls 11 # Number of system calls 60system.cpu.numCycles 56716 # number of cpu cycles simulated 61system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 62system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 63system.cpu.committedInsts 5381 # Number of instructions committed 64system.cpu.committedOps 9748 # Number of ops (including micro ops) committed 65system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses 66system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 67system.cpu.num_func_calls 209 # number of times a function call or return occured 68system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls 69system.cpu.num_int_insts 9654 # number of integer instructions 70system.cpu.num_fp_insts 0 # number of float instructions 71system.cpu.num_int_register_reads 18335 # number of times the integer registers were read 72system.cpu.num_int_register_writes 7527 # number of times the integer registers were written 73system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 74system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 75system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read 76system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written 77system.cpu.num_mem_refs 1988 # number of memory refs 78system.cpu.num_load_insts 1053 # Number of load instructions 79system.cpu.num_store_insts 935 # Number of store instructions 80system.cpu.num_idle_cycles 0 # Number of idle cycles 81system.cpu.num_busy_cycles 56716 # Number of busy cycles 82system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 83system.cpu.idle_fraction 0 # Percentage of idle cycles 84system.cpu.Branches 1208 # Number of branches fetched 85system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction 86system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction 87system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction 88system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction 89system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction 90system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction 91system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction 92system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction 93system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction 94system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction 95system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction 96system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction 97system.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction 98system.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction 99system.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction 100system.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction 101system.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction 102system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction 103system.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction 104system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction 105system.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction 106system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction 107system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction 108system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction 109system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction 110system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction 111system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction 112system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction 113system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction 114system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction 115system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction 116system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction 117system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 118system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 119system.cpu.op_class::total 9748 # Class of executed instruction 120system.cpu.icache.tags.replacements 0 # number of replacements 121system.cpu.icache.tags.tagsinuse 105.550219 # Cycle average of tags in use 122system.cpu.icache.tags.total_refs 6637 # Total number of references to valid blocks. 123system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. 124system.cpu.icache.tags.avg_refs 29.109649 # Average number of references to valid blocks. 125system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 126system.cpu.icache.tags.occ_blocks::cpu.inst 105.550219 # Average occupied blocks per requestor 127system.cpu.icache.tags.occ_percent::cpu.inst 0.051538 # Average percentage of cache occupancy 128system.cpu.icache.tags.occ_percent::total 0.051538 # Average percentage of cache occupancy 129system.cpu.icache.tags.occ_task_id_blocks::1024 228 # Occupied blocks per task id 130system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id 131system.cpu.icache.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id 132system.cpu.icache.tags.occ_task_id_percent::1024 0.111328 # Percentage of cache occupancy per task id 133system.cpu.icache.tags.tag_accesses 13958 # Number of tag accesses 134system.cpu.icache.tags.data_accesses 13958 # Number of data accesses 135system.cpu.icache.ReadReq_hits::cpu.inst 6637 # number of ReadReq hits 136system.cpu.icache.ReadReq_hits::total 6637 # number of ReadReq hits 137system.cpu.icache.demand_hits::cpu.inst 6637 # number of demand (read+write) hits 138system.cpu.icache.demand_hits::total 6637 # number of demand (read+write) hits 139system.cpu.icache.overall_hits::cpu.inst 6637 # number of overall hits 140system.cpu.icache.overall_hits::total 6637 # number of overall hits 141system.cpu.icache.ReadReq_misses::cpu.inst 228 # number of ReadReq misses 142system.cpu.icache.ReadReq_misses::total 228 # number of ReadReq misses 143system.cpu.icache.demand_misses::cpu.inst 228 # number of demand (read+write) misses 144system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses 145system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses 146system.cpu.icache.overall_misses::total 228 # number of overall misses 147system.cpu.icache.ReadReq_miss_latency::cpu.inst 12498000 # number of ReadReq miss cycles 148system.cpu.icache.ReadReq_miss_latency::total 12498000 # number of ReadReq miss cycles 149system.cpu.icache.demand_miss_latency::cpu.inst 12498000 # number of demand (read+write) miss cycles 150system.cpu.icache.demand_miss_latency::total 12498000 # number of demand (read+write) miss cycles 151system.cpu.icache.overall_miss_latency::cpu.inst 12498000 # number of overall miss cycles 152system.cpu.icache.overall_miss_latency::total 12498000 # number of overall miss cycles 153system.cpu.icache.ReadReq_accesses::cpu.inst 6865 # number of ReadReq accesses(hits+misses) 154system.cpu.icache.ReadReq_accesses::total 6865 # number of ReadReq accesses(hits+misses) 155system.cpu.icache.demand_accesses::cpu.inst 6865 # number of demand (read+write) accesses 156system.cpu.icache.demand_accesses::total 6865 # number of demand (read+write) accesses 157system.cpu.icache.overall_accesses::cpu.inst 6865 # number of overall (read+write) accesses 158system.cpu.icache.overall_accesses::total 6865 # number of overall (read+write) accesses 159system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.033212 # miss rate for ReadReq accesses 160system.cpu.icache.ReadReq_miss_rate::total 0.033212 # miss rate for ReadReq accesses 161system.cpu.icache.demand_miss_rate::cpu.inst 0.033212 # miss rate for demand accesses 162system.cpu.icache.demand_miss_rate::total 0.033212 # miss rate for demand accesses 163system.cpu.icache.overall_miss_rate::cpu.inst 0.033212 # miss rate for overall accesses 164system.cpu.icache.overall_miss_rate::total 0.033212 # miss rate for overall accesses 165system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54815.789474 # average ReadReq miss latency 166system.cpu.icache.ReadReq_avg_miss_latency::total 54815.789474 # average ReadReq miss latency 167system.cpu.icache.demand_avg_miss_latency::cpu.inst 54815.789474 # average overall miss latency 168system.cpu.icache.demand_avg_miss_latency::total 54815.789474 # average overall miss latency 169system.cpu.icache.overall_avg_miss_latency::cpu.inst 54815.789474 # average overall miss latency 170system.cpu.icache.overall_avg_miss_latency::total 54815.789474 # average overall miss latency 171system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 172system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 173system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 174system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 175system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 176system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 177system.cpu.icache.fast_writes 0 # number of fast writes performed 178system.cpu.icache.cache_copies 0 # number of cache copies performed 179system.cpu.icache.ReadReq_mshr_misses::cpu.inst 228 # number of ReadReq MSHR misses 180system.cpu.icache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses 181system.cpu.icache.demand_mshr_misses::cpu.inst 228 # number of demand (read+write) MSHR misses 182system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses 183system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses 184system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses 185system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12042000 # number of ReadReq MSHR miss cycles 186system.cpu.icache.ReadReq_mshr_miss_latency::total 12042000 # number of ReadReq MSHR miss cycles 187system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12042000 # number of demand (read+write) MSHR miss cycles 188system.cpu.icache.demand_mshr_miss_latency::total 12042000 # number of demand (read+write) MSHR miss cycles 189system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12042000 # number of overall MSHR miss cycles 190system.cpu.icache.overall_mshr_miss_latency::total 12042000 # number of overall MSHR miss cycles 191system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for ReadReq accesses 192system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033212 # mshr miss rate for ReadReq accesses 193system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for demand accesses 194system.cpu.icache.demand_mshr_miss_rate::total 0.033212 # mshr miss rate for demand accesses 195system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for overall accesses 196system.cpu.icache.overall_mshr_miss_rate::total 0.033212 # mshr miss rate for overall accesses 197system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52815.789474 # average ReadReq mshr miss latency 198system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52815.789474 # average ReadReq mshr miss latency 199system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency 200system.cpu.icache.demand_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency 201system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency 202system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency 203system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 204system.cpu.l2cache.tags.replacements 0 # number of replacements 205system.cpu.l2cache.tags.tagsinuse 134.034140 # Cycle average of tags in use 206system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 207system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks. 208system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks. 209system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 210system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.558330 # Average occupied blocks per requestor 211system.cpu.l2cache.tags.occ_blocks::cpu.data 28.475810 # Average occupied blocks per requestor 212system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy 213system.cpu.l2cache.tags.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy 214system.cpu.l2cache.tags.occ_percent::total 0.004090 # Average percentage of cache occupancy 215system.cpu.l2cache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id 216system.cpu.l2cache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id 217system.cpu.l2cache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id 218system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008606 # Percentage of cache occupancy per task id 219system.cpu.l2cache.tags.tag_accesses 3257 # Number of tag accesses 220system.cpu.l2cache.tags.data_accesses 3257 # Number of data accesses 221system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 222system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 223system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 224system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 225system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 226system.cpu.l2cache.overall_hits::total 1 # number of overall hits 227system.cpu.l2cache.ReadReq_misses::cpu.inst 227 # number of ReadReq misses 228system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses 229system.cpu.l2cache.ReadReq_misses::total 282 # number of ReadReq misses 230system.cpu.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses 231system.cpu.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses 232system.cpu.l2cache.demand_misses::cpu.inst 227 # number of demand (read+write) misses 233system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses 234system.cpu.l2cache.demand_misses::total 361 # number of demand (read+write) misses 235system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses 236system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses 237system.cpu.l2cache.overall_misses::total 361 # number of overall misses 238system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11804000 # number of ReadReq miss cycles 239system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2860000 # number of ReadReq miss cycles 240system.cpu.l2cache.ReadReq_miss_latency::total 14664000 # number of ReadReq miss cycles 241system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4108000 # number of ReadExReq miss cycles 242system.cpu.l2cache.ReadExReq_miss_latency::total 4108000 # number of ReadExReq miss cycles 243system.cpu.l2cache.demand_miss_latency::cpu.inst 11804000 # number of demand (read+write) miss cycles 244system.cpu.l2cache.demand_miss_latency::cpu.data 6968000 # number of demand (read+write) miss cycles 245system.cpu.l2cache.demand_miss_latency::total 18772000 # number of demand (read+write) miss cycles 246system.cpu.l2cache.overall_miss_latency::cpu.inst 11804000 # number of overall miss cycles 247system.cpu.l2cache.overall_miss_latency::cpu.data 6968000 # number of overall miss cycles 248system.cpu.l2cache.overall_miss_latency::total 18772000 # number of overall miss cycles 249system.cpu.l2cache.ReadReq_accesses::cpu.inst 228 # number of ReadReq accesses(hits+misses) 250system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) 251system.cpu.l2cache.ReadReq_accesses::total 283 # number of ReadReq accesses(hits+misses) 252system.cpu.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) 253system.cpu.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) 254system.cpu.l2cache.demand_accesses::cpu.inst 228 # number of demand (read+write) accesses 255system.cpu.l2cache.demand_accesses::cpu.data 134 # number of demand (read+write) accesses 256system.cpu.l2cache.demand_accesses::total 362 # number of demand (read+write) accesses 257system.cpu.l2cache.overall_accesses::cpu.inst 228 # number of overall (read+write) accesses 258system.cpu.l2cache.overall_accesses::cpu.data 134 # number of overall (read+write) accesses 259system.cpu.l2cache.overall_accesses::total 362 # number of overall (read+write) accesses 260system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.995614 # miss rate for ReadReq accesses 261system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 262system.cpu.l2cache.ReadReq_miss_rate::total 0.996466 # miss rate for ReadReq accesses 263system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 264system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 265system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995614 # miss rate for demand accesses 266system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 267system.cpu.l2cache.demand_miss_rate::total 0.997238 # miss rate for demand accesses 268system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses 269system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 270system.cpu.l2cache.overall_miss_rate::total 0.997238 # miss rate for overall accesses 271system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 272system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 273system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 274system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 275system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 276system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 277system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 278system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 279system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 280system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 281system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency 282system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 283system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 284system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 285system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 286system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 287system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 288system.cpu.l2cache.fast_writes 0 # number of fast writes performed 289system.cpu.l2cache.cache_copies 0 # number of cache copies performed 290system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 227 # number of ReadReq MSHR misses 291system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses 292system.cpu.l2cache.ReadReq_mshr_misses::total 282 # number of ReadReq MSHR misses 293system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses 294system.cpu.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses 295system.cpu.l2cache.demand_mshr_misses::cpu.inst 227 # number of demand (read+write) MSHR misses 296system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses 297system.cpu.l2cache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses 298system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses 299system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses 300system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses 301system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9080000 # number of ReadReq MSHR miss cycles 302system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2200000 # number of ReadReq MSHR miss cycles 303system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11280000 # number of ReadReq MSHR miss cycles 304system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3160000 # number of ReadExReq MSHR miss cycles 305system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3160000 # number of ReadExReq MSHR miss cycles 306system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9080000 # number of demand (read+write) MSHR miss cycles 307system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles 308system.cpu.l2cache.demand_mshr_miss_latency::total 14440000 # number of demand (read+write) MSHR miss cycles 309system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9080000 # number of overall MSHR miss cycles 310system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles 311system.cpu.l2cache.overall_mshr_miss_latency::total 14440000 # number of overall MSHR miss cycles 312system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadReq accesses 313system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 314system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.996466 # mshr miss rate for ReadReq accesses 315system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 316system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 317system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for demand accesses 318system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 319system.cpu.l2cache.demand_mshr_miss_rate::total 0.997238 # mshr miss rate for demand accesses 320system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses 321system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 322system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 # mshr miss rate for overall accesses 323system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 324system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 325system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 326system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 327system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 328system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 329system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 330system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 331system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 332system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 333system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 334system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 335system.cpu.dcache.tags.replacements 0 # number of replacements 336system.cpu.dcache.tags.tagsinuse 80.797237 # Cycle average of tags in use 337system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. 338system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. 339system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. 340system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 341system.cpu.dcache.tags.occ_blocks::cpu.data 80.797237 # Average occupied blocks per requestor 342system.cpu.dcache.tags.occ_percent::cpu.data 0.019726 # Average percentage of cache occupancy 343system.cpu.dcache.tags.occ_percent::total 0.019726 # Average percentage of cache occupancy 344system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id 345system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id 346system.cpu.dcache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id 347system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id 348system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses 349system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses 350system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits 351system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits 352system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits 353system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits 354system.cpu.dcache.demand_hits::cpu.data 1854 # number of demand (read+write) hits 355system.cpu.dcache.demand_hits::total 1854 # number of demand (read+write) hits 356system.cpu.dcache.overall_hits::cpu.data 1854 # number of overall hits 357system.cpu.dcache.overall_hits::total 1854 # number of overall hits 358system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses 359system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses 360system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses 361system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses 362system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses 363system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses 364system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses 365system.cpu.dcache.overall_misses::total 134 # number of overall misses 366system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles 367system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles 368system.cpu.dcache.WriteReq_miss_latency::cpu.data 4345000 # number of WriteReq miss cycles 369system.cpu.dcache.WriteReq_miss_latency::total 4345000 # number of WriteReq miss cycles 370system.cpu.dcache.demand_miss_latency::cpu.data 7370000 # number of demand (read+write) miss cycles 371system.cpu.dcache.demand_miss_latency::total 7370000 # number of demand (read+write) miss cycles 372system.cpu.dcache.overall_miss_latency::cpu.data 7370000 # number of overall miss cycles 373system.cpu.dcache.overall_miss_latency::total 7370000 # number of overall miss cycles 374system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses) 375system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses) 376system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) 377system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) 378system.cpu.dcache.demand_accesses::cpu.data 1988 # number of demand (read+write) accesses 379system.cpu.dcache.demand_accesses::total 1988 # number of demand (read+write) accesses 380system.cpu.dcache.overall_accesses::cpu.data 1988 # number of overall (read+write) accesses 381system.cpu.dcache.overall_accesses::total 1988 # number of overall (read+write) accesses 382system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052232 # miss rate for ReadReq accesses 383system.cpu.dcache.ReadReq_miss_rate::total 0.052232 # miss rate for ReadReq accesses 384system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses 385system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses 386system.cpu.dcache.demand_miss_rate::cpu.data 0.067404 # miss rate for demand accesses 387system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses 388system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses 389system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses 390system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency 391system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency 392system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency 393system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency 394system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency 395system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency 396system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency 397system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency 398system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 399system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 400system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 401system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 402system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 403system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 404system.cpu.dcache.fast_writes 0 # number of fast writes performed 405system.cpu.dcache.cache_copies 0 # number of cache copies performed 406system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses 407system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses 408system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses 409system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses 410system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses 411system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses 412system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses 413system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses 414system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles 415system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles 416system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4187000 # number of WriteReq MSHR miss cycles 417system.cpu.dcache.WriteReq_mshr_miss_latency::total 4187000 # number of WriteReq MSHR miss cycles 418system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7102000 # number of demand (read+write) MSHR miss cycles 419system.cpu.dcache.demand_mshr_miss_latency::total 7102000 # number of demand (read+write) MSHR miss cycles 420system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7102000 # number of overall MSHR miss cycles 421system.cpu.dcache.overall_mshr_miss_latency::total 7102000 # number of overall MSHR miss cycles 422system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses 423system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses 424system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses 425system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses 426system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for demand accesses 427system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses 428system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses 429system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses 430system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency 431system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency 432system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 433system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 434system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 435system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 436system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 437system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 438system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 439system.cpu.toL2Bus.trans_dist::ReadReq 283 # Transaction distribution 440system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution 441system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution 442system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution 443system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 456 # Packet count per connected master and slave (bytes) 444system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 268 # Packet count per connected master and slave (bytes) 445system.cpu.toL2Bus.pkt_count::total 724 # Packet count per connected master and slave (bytes) 446system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14592 # Cumulative packet size per connected master and slave (bytes) 447system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8576 # Cumulative packet size per connected master and slave (bytes) 448system.cpu.toL2Bus.pkt_size::total 23168 # Cumulative packet size per connected master and slave (bytes) 449system.cpu.toL2Bus.snoops 0 # Total snoops (count) 450system.cpu.toL2Bus.snoop_fanout::samples 362 # Request fanout histogram 451system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram 452system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 453system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 454system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 455system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 456system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 457system.cpu.toL2Bus.snoop_fanout::3 362 100.00% 100.00% # Request fanout histogram 458system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 459system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 460system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 461system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 462system.cpu.toL2Bus.snoop_fanout::total 362 # Request fanout histogram 463system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks) 464system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 465system.cpu.toL2Bus.respLayer0.occupancy 342000 # Layer occupancy (ticks) 466system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%) 467system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks) 468system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) 469 470---------- End Simulation Statistics ---------- 471