stats.txt revision 10628:c9b7e0c69f88
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000107 # Number of seconds simulated 4sim_ticks 107237 # Number of ticks simulated 5final_tick 107237 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000 # Frequency of simulated ticks 7host_inst_rate 59170 # Simulator instruction rate (inst/s) 8host_op_rate 107175 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1178869 # Simulator tick rate (ticks/s) 10host_mem_usage 466480 # Number of bytes of host memory used 11host_seconds 0.09 # Real time elapsed on the host 12sim_insts 5381 # Number of instructions simulated 13sim_ops 9748 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1 # Clock period in ticks 16system.mem_ctrls.bytes_read::ruby.dir_cntrl0 88128 # Number of bytes read from this memory 17system.mem_ctrls.bytes_read::total 88128 # Number of bytes read from this memory 18system.mem_ctrls.bytes_written::ruby.dir_cntrl0 87872 # Number of bytes written to this memory 19system.mem_ctrls.bytes_written::total 87872 # Number of bytes written to this memory 20system.mem_ctrls.num_reads::ruby.dir_cntrl0 1377 # Number of read requests responded to by this memory 21system.mem_ctrls.num_reads::total 1377 # Number of read requests responded to by this memory 22system.mem_ctrls.num_writes::ruby.dir_cntrl0 1373 # Number of write requests responded to by this memory 23system.mem_ctrls.num_writes::total 1373 # Number of write requests responded to by this memory 24system.mem_ctrls.bw_read::ruby.dir_cntrl0 821805907 # Total read bandwidth from this memory (bytes/s) 25system.mem_ctrls.bw_read::total 821805907 # Total read bandwidth from this memory (bytes/s) 26system.mem_ctrls.bw_write::ruby.dir_cntrl0 819418671 # Write bandwidth from this memory (bytes/s) 27system.mem_ctrls.bw_write::total 819418671 # Write bandwidth from this memory (bytes/s) 28system.mem_ctrls.bw_total::ruby.dir_cntrl0 1641224577 # Total bandwidth to/from this memory (bytes/s) 29system.mem_ctrls.bw_total::total 1641224577 # Total bandwidth to/from this memory (bytes/s) 30system.mem_ctrls.readReqs 1377 # Number of read requests accepted 31system.mem_ctrls.writeReqs 1373 # Number of write requests accepted 32system.mem_ctrls.readBursts 1377 # Number of DRAM read bursts, including those serviced by the write queue 33system.mem_ctrls.writeBursts 1373 # Number of DRAM write bursts, including those merged in the write queue 34system.mem_ctrls.bytesReadDRAM 42624 # Total number of bytes read from DRAM 35system.mem_ctrls.bytesReadWrQ 45504 # Total number of bytes read from write queue 36system.mem_ctrls.bytesWritten 42752 # Total number of bytes written to DRAM 37system.mem_ctrls.bytesReadSys 88128 # Total read bytes from the system interface side 38system.mem_ctrls.bytesWrittenSys 87872 # Total written bytes from the system interface side 39system.mem_ctrls.servicedByWrQ 711 # Number of DRAM read bursts serviced by the write queue 40system.mem_ctrls.mergedWrBursts 686 # Number of DRAM write bursts merged with an existing one 41system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 42system.mem_ctrls.perBankRdBursts::0 57 # Per bank write bursts 43system.mem_ctrls.perBankRdBursts::1 1 # Per bank write bursts 44system.mem_ctrls.perBankRdBursts::2 6 # Per bank write bursts 45system.mem_ctrls.perBankRdBursts::3 10 # Per bank write bursts 46system.mem_ctrls.perBankRdBursts::4 51 # Per bank write bursts 47system.mem_ctrls.perBankRdBursts::5 57 # Per bank write bursts 48system.mem_ctrls.perBankRdBursts::6 42 # Per bank write bursts 49system.mem_ctrls.perBankRdBursts::7 64 # Per bank write bursts 50system.mem_ctrls.perBankRdBursts::8 27 # Per bank write bursts 51system.mem_ctrls.perBankRdBursts::9 134 # Per bank write bursts 52system.mem_ctrls.perBankRdBursts::10 126 # Per bank write bursts 53system.mem_ctrls.perBankRdBursts::11 22 # Per bank write bursts 54system.mem_ctrls.perBankRdBursts::12 2 # Per bank write bursts 55system.mem_ctrls.perBankRdBursts::13 28 # Per bank write bursts 56system.mem_ctrls.perBankRdBursts::14 7 # Per bank write bursts 57system.mem_ctrls.perBankRdBursts::15 32 # Per bank write bursts 58system.mem_ctrls.perBankWrBursts::0 50 # Per bank write bursts 59system.mem_ctrls.perBankWrBursts::1 1 # Per bank write bursts 60system.mem_ctrls.perBankWrBursts::2 6 # Per bank write bursts 61system.mem_ctrls.perBankWrBursts::3 10 # Per bank write bursts 62system.mem_ctrls.perBankWrBursts::4 52 # Per bank write bursts 63system.mem_ctrls.perBankWrBursts::5 55 # Per bank write bursts 64system.mem_ctrls.perBankWrBursts::6 44 # Per bank write bursts 65system.mem_ctrls.perBankWrBursts::7 66 # Per bank write bursts 66system.mem_ctrls.perBankWrBursts::8 28 # Per bank write bursts 67system.mem_ctrls.perBankWrBursts::9 133 # Per bank write bursts 68system.mem_ctrls.perBankWrBursts::10 129 # Per bank write bursts 69system.mem_ctrls.perBankWrBursts::11 22 # Per bank write bursts 70system.mem_ctrls.perBankWrBursts::12 2 # Per bank write bursts 71system.mem_ctrls.perBankWrBursts::13 30 # Per bank write bursts 72system.mem_ctrls.perBankWrBursts::14 7 # Per bank write bursts 73system.mem_ctrls.perBankWrBursts::15 33 # Per bank write bursts 74system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry 75system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry 76system.mem_ctrls.totGap 107133 # Total gap between requests 77system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) 78system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) 79system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) 80system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) 81system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) 82system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) 83system.mem_ctrls.readPktSize::6 1377 # Read request sizes (log2) 84system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) 85system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) 86system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) 87system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) 88system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) 89system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) 90system.mem_ctrls.writePktSize::6 1373 # Write request sizes (log2) 91system.mem_ctrls.rdQLenPdf::0 666 # What read queue length does an incoming req see 92system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see 93system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see 94system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see 95system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see 96system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see 97system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see 98system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see 99system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see 100system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see 101system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see 102system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see 103system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see 104system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see 105system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see 106system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see 107system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see 108system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see 109system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see 110system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see 111system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see 112system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see 113system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see 114system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see 115system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see 116system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see 117system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see 118system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see 119system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see 120system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see 121system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see 122system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see 123system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see 124system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see 125system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see 126system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see 127system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see 128system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see 129system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see 130system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see 131system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see 132system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see 133system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see 134system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see 135system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see 136system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see 137system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see 138system.mem_ctrls.wrQLenPdf::15 6 # What write queue length does an incoming req see 139system.mem_ctrls.wrQLenPdf::16 7 # What write queue length does an incoming req see 140system.mem_ctrls.wrQLenPdf::17 39 # What write queue length does an incoming req see 141system.mem_ctrls.wrQLenPdf::18 43 # What write queue length does an incoming req see 142system.mem_ctrls.wrQLenPdf::19 42 # What write queue length does an incoming req see 143system.mem_ctrls.wrQLenPdf::20 41 # What write queue length does an incoming req see 144system.mem_ctrls.wrQLenPdf::21 43 # What write queue length does an incoming req see 145system.mem_ctrls.wrQLenPdf::22 41 # What write queue length does an incoming req see 146system.mem_ctrls.wrQLenPdf::23 41 # What write queue length does an incoming req see 147system.mem_ctrls.wrQLenPdf::24 41 # What write queue length does an incoming req see 148system.mem_ctrls.wrQLenPdf::25 41 # What write queue length does an incoming req see 149system.mem_ctrls.wrQLenPdf::26 41 # What write queue length does an incoming req see 150system.mem_ctrls.wrQLenPdf::27 41 # What write queue length does an incoming req see 151system.mem_ctrls.wrQLenPdf::28 41 # What write queue length does an incoming req see 152system.mem_ctrls.wrQLenPdf::29 41 # What write queue length does an incoming req see 153system.mem_ctrls.wrQLenPdf::30 41 # What write queue length does an incoming req see 154system.mem_ctrls.wrQLenPdf::31 41 # What write queue length does an incoming req see 155system.mem_ctrls.wrQLenPdf::32 41 # What write queue length does an incoming req see 156system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see 157system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see 158system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see 159system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see 160system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see 161system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see 162system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see 163system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see 164system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see 165system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see 166system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see 167system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see 168system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see 169system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see 170system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see 171system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see 172system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see 173system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see 174system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see 175system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see 176system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see 177system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see 178system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see 179system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see 180system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see 181system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see 182system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see 183system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see 184system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see 185system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see 186system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see 187system.mem_ctrls.bytesPerActivate::samples 272 # Bytes accessed per row activation 188system.mem_ctrls.bytesPerActivate::mean 306.823529 # Bytes accessed per row activation 189system.mem_ctrls.bytesPerActivate::gmean 199.088320 # Bytes accessed per row activation 190system.mem_ctrls.bytesPerActivate::stdev 295.785748 # Bytes accessed per row activation 191system.mem_ctrls.bytesPerActivate::0-127 71 26.10% 26.10% # Bytes accessed per row activation 192system.mem_ctrls.bytesPerActivate::128-255 86 31.62% 57.72% # Bytes accessed per row activation 193system.mem_ctrls.bytesPerActivate::256-383 34 12.50% 70.22% # Bytes accessed per row activation 194system.mem_ctrls.bytesPerActivate::384-511 20 7.35% 77.57% # Bytes accessed per row activation 195system.mem_ctrls.bytesPerActivate::512-639 17 6.25% 83.82% # Bytes accessed per row activation 196system.mem_ctrls.bytesPerActivate::640-767 9 3.31% 87.13% # Bytes accessed per row activation 197system.mem_ctrls.bytesPerActivate::768-895 11 4.04% 91.18% # Bytes accessed per row activation 198system.mem_ctrls.bytesPerActivate::896-1023 3 1.10% 92.28% # Bytes accessed per row activation 199system.mem_ctrls.bytesPerActivate::1024-1151 21 7.72% 100.00% # Bytes accessed per row activation 200system.mem_ctrls.bytesPerActivate::total 272 # Bytes accessed per row activation 201system.mem_ctrls.rdPerTurnAround::samples 41 # Reads before turning the bus around for writes 202system.mem_ctrls.rdPerTurnAround::mean 16.121951 # Reads before turning the bus around for writes 203system.mem_ctrls.rdPerTurnAround::gmean 15.902045 # Reads before turning the bus around for writes 204system.mem_ctrls.rdPerTurnAround::stdev 3.325621 # Reads before turning the bus around for writes 205system.mem_ctrls.rdPerTurnAround::12-13 2 4.88% 4.88% # Reads before turning the bus around for writes 206system.mem_ctrls.rdPerTurnAround::14-15 18 43.90% 48.78% # Reads before turning the bus around for writes 207system.mem_ctrls.rdPerTurnAround::16-17 18 43.90% 92.68% # Reads before turning the bus around for writes 208system.mem_ctrls.rdPerTurnAround::20-21 2 4.88% 97.56% # Reads before turning the bus around for writes 209system.mem_ctrls.rdPerTurnAround::34-35 1 2.44% 100.00% # Reads before turning the bus around for writes 210system.mem_ctrls.rdPerTurnAround::total 41 # Reads before turning the bus around for writes 211system.mem_ctrls.wrPerTurnAround::samples 41 # Writes before turning the bus around for reads 212system.mem_ctrls.wrPerTurnAround::mean 16.292683 # Writes before turning the bus around for reads 213system.mem_ctrls.wrPerTurnAround::gmean 16.274345 # Writes before turning the bus around for reads 214system.mem_ctrls.wrPerTurnAround::stdev 0.813754 # Writes before turning the bus around for reads 215system.mem_ctrls.wrPerTurnAround::16 36 87.80% 87.80% # Writes before turning the bus around for reads 216system.mem_ctrls.wrPerTurnAround::18 3 7.32% 95.12% # Writes before turning the bus around for reads 217system.mem_ctrls.wrPerTurnAround::19 2 4.88% 100.00% # Writes before turning the bus around for reads 218system.mem_ctrls.wrPerTurnAround::total 41 # Writes before turning the bus around for reads 219system.mem_ctrls.totQLat 9844 # Total ticks spent queuing 220system.mem_ctrls.totMemAccLat 22498 # Total ticks spent from burst creation until serviced by the DRAM 221system.mem_ctrls.totBusLat 3330 # Total ticks spent in databus transfers 222system.mem_ctrls.avgQLat 14.78 # Average queueing delay per DRAM burst 223system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst 224system.mem_ctrls.avgMemAccLat 33.78 # Average memory access latency per DRAM burst 225system.mem_ctrls.avgRdBW 397.47 # Average DRAM read bandwidth in MiByte/s 226system.mem_ctrls.avgWrBW 398.67 # Average achieved write bandwidth in MiByte/s 227system.mem_ctrls.avgRdBWSys 821.81 # Average system read bandwidth in MiByte/s 228system.mem_ctrls.avgWrBWSys 819.42 # Average system write bandwidth in MiByte/s 229system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 230system.mem_ctrls.busUtil 6.22 # Data bus utilization in percentage 231system.mem_ctrls.busUtilRead 3.11 # Data bus utilization in percentage for reads 232system.mem_ctrls.busUtilWrite 3.11 # Data bus utilization in percentage for writes 233system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing 234system.mem_ctrls.avgWrQLen 26.04 # Average write queue length when enqueuing 235system.mem_ctrls.readRowHits 427 # Number of row buffer hits during reads 236system.mem_ctrls.writeRowHits 625 # Number of row buffer hits during writes 237system.mem_ctrls.readRowHitRate 64.11 # Row buffer hit rate for reads 238system.mem_ctrls.writeRowHitRate 90.98 # Row buffer hit rate for writes 239system.mem_ctrls.avgGap 38.96 # Average gap between requests 240system.mem_ctrls.pageHitRate 77.75 # Row buffer hit rate, read and write combined 241system.mem_ctrls_0.actEnergy 695520 # Energy for activate commands per rank (pJ) 242system.mem_ctrls_0.preEnergy 386400 # Energy for precharge commands per rank (pJ) 243system.mem_ctrls_0.readEnergy 3219840 # Energy for read commands per rank (pJ) 244system.mem_ctrls_0.writeEnergy 2623104 # Energy for write commands per rank (pJ) 245system.mem_ctrls_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) 246system.mem_ctrls_0.actBackEnergy 57895812 # Energy for active background per rank (pJ) 247system.mem_ctrls_0.preBackEnergy 10101000 # Energy for precharge background per rank (pJ) 248system.mem_ctrls_0.totalEnergy 81532956 # Total energy per rank (pJ) 249system.mem_ctrls_0.averagePower 803.454502 # Core power per rank (mW) 250system.mem_ctrls_0.memoryStateTime::IDLE 16443 # Time in different power states 251system.mem_ctrls_0.memoryStateTime::REF 3380 # Time in different power states 252system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states 253system.mem_ctrls_0.memoryStateTime::ACT 81669 # Time in different power states 254system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states 255system.mem_ctrls_1.actEnergy 1270080 # Energy for activate commands per rank (pJ) 256system.mem_ctrls_1.preEnergy 705600 # Energy for precharge commands per rank (pJ) 257system.mem_ctrls_1.readEnergy 4605120 # Energy for read commands per rank (pJ) 258system.mem_ctrls_1.writeEnergy 3784320 # Energy for write commands per rank (pJ) 259system.mem_ctrls_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) 260system.mem_ctrls_1.actBackEnergy 62916372 # Energy for active background per rank (pJ) 261system.mem_ctrls_1.preBackEnergy 5697000 # Energy for precharge background per rank (pJ) 262system.mem_ctrls_1.totalEnergy 85589772 # Total energy per rank (pJ) 263system.mem_ctrls_1.averagePower 843.431798 # Core power per rank (mW) 264system.mem_ctrls_1.memoryStateTime::IDLE 9164 # Time in different power states 265system.mem_ctrls_1.memoryStateTime::REF 3380 # Time in different power states 266system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states 267system.mem_ctrls_1.memoryStateTime::ACT 89065 # Time in different power states 268system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states 269system.cpu.clk_domain.clock 1 # Clock period in ticks 270system.cpu.apic_clk_domain.clock 16 # Clock period in ticks 271system.cpu.workload.num_syscalls 11 # Number of system calls 272system.cpu.numCycles 107237 # number of cpu cycles simulated 273system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 274system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 275system.cpu.committedInsts 5381 # Number of instructions committed 276system.cpu.committedOps 9748 # Number of ops (including micro ops) committed 277system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses 278system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 279system.cpu.num_func_calls 209 # number of times a function call or return occured 280system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls 281system.cpu.num_int_insts 9654 # number of integer instructions 282system.cpu.num_fp_insts 0 # number of float instructions 283system.cpu.num_int_register_reads 18335 # number of times the integer registers were read 284system.cpu.num_int_register_writes 7527 # number of times the integer registers were written 285system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 286system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 287system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read 288system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written 289system.cpu.num_mem_refs 1988 # number of memory refs 290system.cpu.num_load_insts 1053 # Number of load instructions 291system.cpu.num_store_insts 935 # Number of store instructions 292system.cpu.num_idle_cycles 0.999991 # Number of idle cycles 293system.cpu.num_busy_cycles 107236.000009 # Number of busy cycles 294system.cpu.not_idle_fraction 0.999991 # Percentage of non-idle cycles 295system.cpu.idle_fraction 0.000009 # Percentage of idle cycles 296system.cpu.Branches 1208 # Number of branches fetched 297system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction 298system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction 299system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction 300system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction 301system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction 302system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction 303system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction 304system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction 305system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction 306system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction 307system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction 308system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction 309system.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction 310system.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction 311system.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction 312system.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction 313system.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction 314system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction 315system.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction 316system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction 317system.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction 318system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction 319system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction 320system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction 321system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction 322system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction 323system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction 324system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction 325system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction 326system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction 327system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction 328system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction 329system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 330system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 331system.cpu.op_class::total 9748 # Class of executed instruction 332system.ruby.clk_domain.clock 1 # Clock period in ticks 333system.ruby.delayHist::bucket_size 1 # delay histogram for all message 334system.ruby.delayHist::max_bucket 9 # delay histogram for all message 335system.ruby.delayHist::samples 2750 # delay histogram for all message 336system.ruby.delayHist | 2750 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message 337system.ruby.delayHist::total 2750 # delay histogram for all message 338system.ruby.outstanding_req_hist::bucket_size 1 339system.ruby.outstanding_req_hist::max_bucket 9 340system.ruby.outstanding_req_hist::samples 8852 341system.ruby.outstanding_req_hist::mean 1 342system.ruby.outstanding_req_hist::gmean 1 343system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8852 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 344system.ruby.outstanding_req_hist::total 8852 345system.ruby.latency_hist::bucket_size 64 346system.ruby.latency_hist::max_bucket 639 347system.ruby.latency_hist::samples 8852 348system.ruby.latency_hist::mean 11.114437 349system.ruby.latency_hist::gmean 4.638310 350system.ruby.latency_hist::stdev 22.979355 351system.ruby.latency_hist | 8594 97.09% 97.09% | 215 2.43% 99.51% | 29 0.33% 99.84% | 6 0.07% 99.91% | 6 0.07% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 352system.ruby.latency_hist::total 8852 353system.ruby.hit_latency_hist::bucket_size 1 354system.ruby.hit_latency_hist::max_bucket 9 355system.ruby.hit_latency_hist::samples 7475 356system.ruby.hit_latency_hist::mean 3 357system.ruby.hit_latency_hist::gmean 3.000000 358system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7475 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 359system.ruby.hit_latency_hist::total 7475 360system.ruby.miss_latency_hist::bucket_size 64 361system.ruby.miss_latency_hist::max_bucket 639 362system.ruby.miss_latency_hist::samples 1377 363system.ruby.miss_latency_hist::mean 55.163399 364system.ruby.miss_latency_hist::gmean 49.389540 365system.ruby.miss_latency_hist::stdev 33.124416 366system.ruby.miss_latency_hist | 1119 81.26% 81.26% | 215 15.61% 96.88% | 29 2.11% 98.98% | 6 0.44% 99.42% | 6 0.44% 99.85% | 2 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 367system.ruby.miss_latency_hist::total 1377 368system.ruby.Directory.incomplete_times 1376 369system.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 # Number of cache demand hits 370system.ruby.l1_cntrl0.cacheMemory.demand_misses 1377 # Number of cache demand misses 371system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8852 # Number of cache demand accesses 372system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks 373system.ruby.network.routers0.percent_links_utilized 6.411034 374system.ruby.network.routers0.msg_count.Control::2 1377 375system.ruby.network.routers0.msg_count.Data::2 1373 376system.ruby.network.routers0.msg_count.Response_Data::4 1377 377system.ruby.network.routers0.msg_count.Writeback_Control::3 1373 378system.ruby.network.routers0.msg_bytes.Control::2 11016 379system.ruby.network.routers0.msg_bytes.Data::2 98856 380system.ruby.network.routers0.msg_bytes.Response_Data::4 99144 381system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10984 382system.ruby.network.routers1.percent_links_utilized 6.411034 383system.ruby.network.routers1.msg_count.Control::2 1377 384system.ruby.network.routers1.msg_count.Data::2 1373 385system.ruby.network.routers1.msg_count.Response_Data::4 1377 386system.ruby.network.routers1.msg_count.Writeback_Control::3 1373 387system.ruby.network.routers1.msg_bytes.Control::2 11016 388system.ruby.network.routers1.msg_bytes.Data::2 98856 389system.ruby.network.routers1.msg_bytes.Response_Data::4 99144 390system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10984 391system.ruby.network.routers2.percent_links_utilized 6.411034 392system.ruby.network.routers2.msg_count.Control::2 1377 393system.ruby.network.routers2.msg_count.Data::2 1373 394system.ruby.network.routers2.msg_count.Response_Data::4 1377 395system.ruby.network.routers2.msg_count.Writeback_Control::3 1373 396system.ruby.network.routers2.msg_bytes.Control::2 11016 397system.ruby.network.routers2.msg_bytes.Data::2 98856 398system.ruby.network.routers2.msg_bytes.Response_Data::4 99144 399system.ruby.network.routers2.msg_bytes.Writeback_Control::3 10984 400system.ruby.network.msg_count.Control 4131 401system.ruby.network.msg_count.Data 4119 402system.ruby.network.msg_count.Response_Data 4131 403system.ruby.network.msg_count.Writeback_Control 4119 404system.ruby.network.msg_byte.Control 33048 405system.ruby.network.msg_byte.Data 296568 406system.ruby.network.msg_byte.Response_Data 297432 407system.ruby.network.msg_byte.Writeback_Control 32952 408system.ruby.network.routers0.throttle0.link_utilization 6.418494 409system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1377 410system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1373 411system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 99144 412system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 10984 413system.ruby.network.routers0.throttle1.link_utilization 6.403573 414system.ruby.network.routers0.throttle1.msg_count.Control::2 1377 415system.ruby.network.routers0.throttle1.msg_count.Data::2 1373 416system.ruby.network.routers0.throttle1.msg_bytes.Control::2 11016 417system.ruby.network.routers0.throttle1.msg_bytes.Data::2 98856 418system.ruby.network.routers1.throttle0.link_utilization 6.403573 419system.ruby.network.routers1.throttle0.msg_count.Control::2 1377 420system.ruby.network.routers1.throttle0.msg_count.Data::2 1373 421system.ruby.network.routers1.throttle0.msg_bytes.Control::2 11016 422system.ruby.network.routers1.throttle0.msg_bytes.Data::2 98856 423system.ruby.network.routers1.throttle1.link_utilization 6.418494 424system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1377 425system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1373 426system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 99144 427system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 10984 428system.ruby.network.routers2.throttle0.link_utilization 6.418494 429system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1377 430system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1373 431system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 99144 432system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 10984 433system.ruby.network.routers2.throttle1.link_utilization 6.403573 434system.ruby.network.routers2.throttle1.msg_count.Control::2 1377 435system.ruby.network.routers2.throttle1.msg_count.Data::2 1373 436system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11016 437system.ruby.network.routers2.throttle1.msg_bytes.Data::2 98856 438system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 439system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 440system.ruby.delayVCHist.vnet_1::samples 1377 # delay histogram for vnet_1 441system.ruby.delayVCHist.vnet_1 | 1377 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 442system.ruby.delayVCHist.vnet_1::total 1377 # delay histogram for vnet_1 443system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 444system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 445system.ruby.delayVCHist.vnet_2::samples 1373 # delay histogram for vnet_2 446system.ruby.delayVCHist.vnet_2 | 1373 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 447system.ruby.delayVCHist.vnet_2::total 1373 # delay histogram for vnet_2 448system.ruby.LD.latency_hist::bucket_size 32 449system.ruby.LD.latency_hist::max_bucket 319 450system.ruby.LD.latency_hist::samples 1045 451system.ruby.LD.latency_hist::mean 24.819139 452system.ruby.LD.latency_hist::gmean 10.890845 453system.ruby.LD.latency_hist::stdev 28.082269 454system.ruby.LD.latency_hist | 546 52.25% 52.25% | 414 39.62% 91.87% | 77 7.37% 99.23% | 1 0.10% 99.33% | 2 0.19% 99.52% | 4 0.38% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 455system.ruby.LD.latency_hist::total 1045 456system.ruby.LD.hit_latency_hist::bucket_size 1 457system.ruby.LD.hit_latency_hist::max_bucket 9 458system.ruby.LD.hit_latency_hist::samples 546 459system.ruby.LD.hit_latency_hist::mean 3 460system.ruby.LD.hit_latency_hist::gmean 3.000000 461system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 546 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 462system.ruby.LD.hit_latency_hist::total 546 463system.ruby.LD.miss_latency_hist::bucket_size 32 464system.ruby.LD.miss_latency_hist::max_bucket 319 465system.ruby.LD.miss_latency_hist::samples 499 466system.ruby.LD.miss_latency_hist::mean 48.693387 467system.ruby.LD.miss_latency_hist::gmean 44.641812 468system.ruby.LD.miss_latency_hist::stdev 23.667547 469system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 414 82.97% 82.97% | 77 15.43% 98.40% | 1 0.20% 98.60% | 2 0.40% 99.00% | 4 0.80% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 470system.ruby.LD.miss_latency_hist::total 499 471system.ruby.ST.latency_hist::bucket_size 64 472system.ruby.ST.latency_hist::max_bucket 639 473system.ruby.ST.latency_hist::samples 935 474system.ruby.ST.latency_hist::mean 16.765775 475system.ruby.ST.latency_hist::gmean 6.381495 476system.ruby.ST.latency_hist::stdev 28.609452 477system.ruby.ST.latency_hist | 895 95.72% 95.72% | 35 3.74% 99.47% | 1 0.11% 99.57% | 2 0.21% 99.79% | 1 0.11% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 478system.ruby.ST.latency_hist::total 935 479system.ruby.ST.hit_latency_hist::bucket_size 1 480system.ruby.ST.hit_latency_hist::max_bucket 9 481system.ruby.ST.hit_latency_hist::samples 681 482system.ruby.ST.hit_latency_hist::mean 3 483system.ruby.ST.hit_latency_hist::gmean 3.000000 484system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 681 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 485system.ruby.ST.hit_latency_hist::total 681 486system.ruby.ST.miss_latency_hist::bucket_size 64 487system.ruby.ST.miss_latency_hist::max_bucket 639 488system.ruby.ST.miss_latency_hist::samples 254 489system.ruby.ST.miss_latency_hist::mean 53.673228 490system.ruby.ST.miss_latency_hist::gmean 48.282634 491system.ruby.ST.miss_latency_hist::stdev 33.823763 492system.ruby.ST.miss_latency_hist | 214 84.25% 84.25% | 35 13.78% 98.03% | 1 0.39% 98.43% | 2 0.79% 99.21% | 1 0.39% 99.61% | 1 0.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 493system.ruby.ST.miss_latency_hist::total 254 494system.ruby.IFETCH.latency_hist::bucket_size 64 495system.ruby.IFETCH.latency_hist::max_bucket 639 496system.ruby.IFETCH.latency_hist::samples 6864 497system.ruby.IFETCH.latency_hist::mean 8.263112 498system.ruby.IFETCH.latency_hist::gmean 3.900453 499system.ruby.IFETCH.latency_hist::stdev 20.209679 500system.ruby.IFETCH.latency_hist | 6731 98.06% 98.06% | 102 1.49% 99.55% | 22 0.32% 99.87% | 3 0.04% 99.91% | 5 0.07% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 501system.ruby.IFETCH.latency_hist::total 6864 502system.ruby.IFETCH.hit_latency_hist::bucket_size 1 503system.ruby.IFETCH.hit_latency_hist::max_bucket 9 504system.ruby.IFETCH.hit_latency_hist::samples 6241 505system.ruby.IFETCH.hit_latency_hist::mean 3 506system.ruby.IFETCH.hit_latency_hist::gmean 3.000000 507system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6241 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 508system.ruby.IFETCH.hit_latency_hist::total 6241 509system.ruby.IFETCH.miss_latency_hist::bucket_size 64 510system.ruby.IFETCH.miss_latency_hist::max_bucket 639 511system.ruby.IFETCH.miss_latency_hist::samples 623 512system.ruby.IFETCH.miss_latency_hist::mean 60.987159 513system.ruby.IFETCH.miss_latency_hist::gmean 54.083593 514system.ruby.IFETCH.miss_latency_hist::stdev 38.003932 515system.ruby.IFETCH.miss_latency_hist | 490 78.65% 78.65% | 102 16.37% 95.02% | 22 3.53% 98.56% | 3 0.48% 99.04% | 5 0.80% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 516system.ruby.IFETCH.miss_latency_hist::total 623 517system.ruby.RMW_Read.latency_hist::bucket_size 4 518system.ruby.RMW_Read.latency_hist::max_bucket 39 519system.ruby.RMW_Read.latency_hist::samples 8 520system.ruby.RMW_Read.latency_hist::mean 6.875000 521system.ruby.RMW_Read.latency_hist::gmean 4.063647 522system.ruby.RMW_Read.latency_hist::stdev 10.960155 523system.ruby.RMW_Read.latency_hist | 7 87.50% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 1 12.50% 100.00% | 0 0.00% 100.00% 524system.ruby.RMW_Read.latency_hist::total 8 525system.ruby.RMW_Read.hit_latency_hist::bucket_size 1 526system.ruby.RMW_Read.hit_latency_hist::max_bucket 9 527system.ruby.RMW_Read.hit_latency_hist::samples 7 528system.ruby.RMW_Read.hit_latency_hist::mean 3 529system.ruby.RMW_Read.hit_latency_hist::gmean 3.000000 530system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 531system.ruby.RMW_Read.hit_latency_hist::total 7 532system.ruby.RMW_Read.miss_latency_hist::bucket_size 4 533system.ruby.RMW_Read.miss_latency_hist::max_bucket 39 534system.ruby.RMW_Read.miss_latency_hist::samples 1 535system.ruby.RMW_Read.miss_latency_hist::mean 34 536system.ruby.RMW_Read.miss_latency_hist::gmean 34.000000 537system.ruby.RMW_Read.miss_latency_hist::stdev nan 538system.ruby.RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% 539system.ruby.RMW_Read.miss_latency_hist::total 1 540system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 541system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 542system.ruby.Directory.miss_mach_latency_hist::samples 1377 543system.ruby.Directory.miss_mach_latency_hist::mean 55.163399 544system.ruby.Directory.miss_mach_latency_hist::gmean 49.389540 545system.ruby.Directory.miss_mach_latency_hist::stdev 33.124416 546system.ruby.Directory.miss_mach_latency_hist | 1119 81.26% 81.26% | 215 15.61% 96.88% | 29 2.11% 98.98% | 6 0.44% 99.42% | 6 0.44% 99.85% | 2 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 547system.ruby.Directory.miss_mach_latency_hist::total 1377 548system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 549system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 550system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 1 551system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev nan 552system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 553system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 1 554system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 1 555system.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 9 556system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 1 557system.ruby.Directory.miss_latency_hist.initial_to_forward::stdev nan 558system.ruby.Directory.miss_latency_hist.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 559system.ruby.Directory.miss_latency_hist.initial_to_forward::total 1 560system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 1 561system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 9 562system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 1 563system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev nan 564system.ruby.Directory.miss_latency_hist.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 565system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 1 566system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 8 567system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 79 568system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1 569system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 75 570system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 75.000000 571system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan 572system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% 573system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1 574system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32 575system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319 576system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 499 577system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 48.693387 578system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 44.641812 579system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 23.667547 580system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 414 82.97% 82.97% | 77 15.43% 98.40% | 1 0.20% 98.60% | 2 0.40% 99.00% | 4 0.80% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 581system.ruby.LD.Directory.miss_type_mach_latency_hist::total 499 582system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 64 583system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 639 584system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 254 585system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 53.673228 586system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 48.282634 587system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 33.823763 588system.ruby.ST.Directory.miss_type_mach_latency_hist | 214 84.25% 84.25% | 35 13.78% 98.03% | 1 0.39% 98.43% | 2 0.79% 99.21% | 1 0.39% 99.61% | 1 0.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 589system.ruby.ST.Directory.miss_type_mach_latency_hist::total 254 590system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 591system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 592system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 623 593system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 60.987159 594system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 54.083593 595system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 38.003932 596system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 490 78.65% 78.65% | 102 16.37% 95.02% | 22 3.53% 98.56% | 3 0.48% 99.04% | 5 0.80% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 597system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 623 598system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::bucket_size 4 599system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::max_bucket 39 600system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::samples 1 601system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::mean 34 602system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::gmean 34.000000 603system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::stdev nan 604system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% 605system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::total 1 606system.ruby.Directory_Controller.GETX 1377 0.00% 0.00% 607system.ruby.Directory_Controller.PUTX 1373 0.00% 0.00% 608system.ruby.Directory_Controller.Memory_Data 1377 0.00% 0.00% 609system.ruby.Directory_Controller.Memory_Ack 1373 0.00% 0.00% 610system.ruby.Directory_Controller.I.GETX 1377 0.00% 0.00% 611system.ruby.Directory_Controller.M.PUTX 1373 0.00% 0.00% 612system.ruby.Directory_Controller.IM.Memory_Data 1377 0.00% 0.00% 613system.ruby.Directory_Controller.MI.Memory_Ack 1373 0.00% 0.00% 614system.ruby.L1Cache_Controller.Load 1045 0.00% 0.00% 615system.ruby.L1Cache_Controller.Ifetch 6864 0.00% 0.00% 616system.ruby.L1Cache_Controller.Store 943 0.00% 0.00% 617system.ruby.L1Cache_Controller.Data 1377 0.00% 0.00% 618system.ruby.L1Cache_Controller.Replacement 1373 0.00% 0.00% 619system.ruby.L1Cache_Controller.Writeback_Ack 1373 0.00% 0.00% 620system.ruby.L1Cache_Controller.I.Load 499 0.00% 0.00% 621system.ruby.L1Cache_Controller.I.Ifetch 623 0.00% 0.00% 622system.ruby.L1Cache_Controller.I.Store 255 0.00% 0.00% 623system.ruby.L1Cache_Controller.M.Load 546 0.00% 0.00% 624system.ruby.L1Cache_Controller.M.Ifetch 6241 0.00% 0.00% 625system.ruby.L1Cache_Controller.M.Store 688 0.00% 0.00% 626system.ruby.L1Cache_Controller.M.Replacement 1373 0.00% 0.00% 627system.ruby.L1Cache_Controller.MI.Writeback_Ack 1373 0.00% 0.00% 628system.ruby.L1Cache_Controller.IS.Data 1122 0.00% 0.00% 629system.ruby.L1Cache_Controller.IM.Data 255 0.00% 0.00% 630 631---------- End Simulation Statistics ---------- 632