stats.txt revision 11312
16167SN/A 26167SN/A---------- Begin Simulation Statistics ---------- 311023Sjthestness@gmail.comsim_seconds 0.000088 # Number of seconds simulated 411023Sjthestness@gmail.comsim_ticks 87948 # Number of ticks simulated 511023Sjthestness@gmail.comfinal_tick 87948 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68673SN/Asim_freq 1000000000 # Frequency of simulated ticks 711312Santhony.gutierrez@amd.comhost_inst_rate 28860 # Simulator instruction rate (inst/s) 811312Santhony.gutierrez@amd.comhost_op_rate 52275 # Simulator op (including micro ops) rate (op/s) 911312Santhony.gutierrez@amd.comhost_tick_rate 471584 # Simulator tick rate (ticks/s) 1011312Santhony.gutierrez@amd.comhost_mem_usage 411784 # Number of bytes of host memory used 1111268Satgutier@umich.eduhost_seconds 0.19 # Real time elapsed on the host 129150SAli.Saidi@ARM.comsim_insts 5381 # Number of instructions simulated 139583Snilay@cs.wisc.edusim_ops 9748 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1 # Clock period in ticks 1610526Snilay@cs.wisc.edusystem.mem_ctrls.bytes_read::ruby.dir_cntrl0 88128 # Number of bytes read from this memory 1710526Snilay@cs.wisc.edusystem.mem_ctrls.bytes_read::total 88128 # Number of bytes read from this memory 1810526Snilay@cs.wisc.edusystem.mem_ctrls.bytes_written::ruby.dir_cntrl0 87872 # Number of bytes written to this memory 1910526Snilay@cs.wisc.edusystem.mem_ctrls.bytes_written::total 87872 # Number of bytes written to this memory 2010526Snilay@cs.wisc.edusystem.mem_ctrls.num_reads::ruby.dir_cntrl0 1377 # Number of read requests responded to by this memory 2110526Snilay@cs.wisc.edusystem.mem_ctrls.num_reads::total 1377 # Number of read requests responded to by this memory 2210526Snilay@cs.wisc.edusystem.mem_ctrls.num_writes::ruby.dir_cntrl0 1373 # Number of write requests responded to by this memory 2310526Snilay@cs.wisc.edusystem.mem_ctrls.num_writes::total 1373 # Number of write requests responded to by this memory 2411023Sjthestness@gmail.comsystem.mem_ctrls.bw_read::ruby.dir_cntrl0 1002046664 # Total read bandwidth from this memory (bytes/s) 2511023Sjthestness@gmail.comsystem.mem_ctrls.bw_read::total 1002046664 # Total read bandwidth from this memory (bytes/s) 2611023Sjthestness@gmail.comsystem.mem_ctrls.bw_write::ruby.dir_cntrl0 999135853 # Write bandwidth from this memory (bytes/s) 2711023Sjthestness@gmail.comsystem.mem_ctrls.bw_write::total 999135853 # Write bandwidth from this memory (bytes/s) 2811023Sjthestness@gmail.comsystem.mem_ctrls.bw_total::ruby.dir_cntrl0 2001182517 # Total bandwidth to/from this memory (bytes/s) 2911023Sjthestness@gmail.comsystem.mem_ctrls.bw_total::total 2001182517 # Total bandwidth to/from this memory (bytes/s) 3010526Snilay@cs.wisc.edusystem.mem_ctrls.readReqs 1377 # Number of read requests accepted 3110526Snilay@cs.wisc.edusystem.mem_ctrls.writeReqs 1373 # Number of write requests accepted 3210526Snilay@cs.wisc.edusystem.mem_ctrls.readBursts 1377 # Number of DRAM read bursts, including those serviced by the write queue 3310526Snilay@cs.wisc.edusystem.mem_ctrls.writeBursts 1373 # Number of DRAM write bursts, including those merged in the write queue 3411023Sjthestness@gmail.comsystem.mem_ctrls.bytesReadDRAM 40320 # Total number of bytes read from DRAM 3511023Sjthestness@gmail.comsystem.mem_ctrls.bytesReadWrQ 47808 # Total number of bytes read from write queue 3611023Sjthestness@gmail.comsystem.mem_ctrls.bytesWritten 39936 # Total number of bytes written to DRAM 3710526Snilay@cs.wisc.edusystem.mem_ctrls.bytesReadSys 88128 # Total read bytes from the system interface side 3810526Snilay@cs.wisc.edusystem.mem_ctrls.bytesWrittenSys 87872 # Total written bytes from the system interface side 3911023Sjthestness@gmail.comsystem.mem_ctrls.servicedByWrQ 747 # Number of DRAM read bursts serviced by the write queue 4011023Sjthestness@gmail.comsystem.mem_ctrls.mergedWrBursts 722 # Number of DRAM write bursts merged with an existing one 4110526Snilay@cs.wisc.edusystem.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 4211023Sjthestness@gmail.comsystem.mem_ctrls.perBankRdBursts::0 59 # Per bank write bursts 4310526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::1 1 # Per bank write bursts 4410526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::2 6 # Per bank write bursts 4511023Sjthestness@gmail.comsystem.mem_ctrls.perBankRdBursts::3 9 # Per bank write bursts 4611023Sjthestness@gmail.comsystem.mem_ctrls.perBankRdBursts::4 52 # Per bank write bursts 4711023Sjthestness@gmail.comsystem.mem_ctrls.perBankRdBursts::5 55 # Per bank write bursts 4811023Sjthestness@gmail.comsystem.mem_ctrls.perBankRdBursts::6 37 # Per bank write bursts 4911023Sjthestness@gmail.comsystem.mem_ctrls.perBankRdBursts::7 64 # Per bank write bursts 5011023Sjthestness@gmail.comsystem.mem_ctrls.perBankRdBursts::8 25 # Per bank write bursts 5111023Sjthestness@gmail.comsystem.mem_ctrls.perBankRdBursts::9 119 # Per bank write bursts 5211023Sjthestness@gmail.comsystem.mem_ctrls.perBankRdBursts::10 121 # Per bank write bursts 5310892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::11 21 # Per bank write bursts 5410526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::12 2 # Per bank write bursts 5511023Sjthestness@gmail.comsystem.mem_ctrls.perBankRdBursts::13 21 # Per bank write bursts 5610892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::14 8 # Per bank write bursts 5711023Sjthestness@gmail.comsystem.mem_ctrls.perBankRdBursts::15 30 # Per bank write bursts 5811023Sjthestness@gmail.comsystem.mem_ctrls.perBankWrBursts::0 51 # Per bank write bursts 5910526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::1 1 # Per bank write bursts 6010526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::2 6 # Per bank write bursts 6111023Sjthestness@gmail.comsystem.mem_ctrls.perBankWrBursts::3 7 # Per bank write bursts 6211023Sjthestness@gmail.comsystem.mem_ctrls.perBankWrBursts::4 52 # Per bank write bursts 6311023Sjthestness@gmail.comsystem.mem_ctrls.perBankWrBursts::5 50 # Per bank write bursts 6411023Sjthestness@gmail.comsystem.mem_ctrls.perBankWrBursts::6 36 # Per bank write bursts 6511023Sjthestness@gmail.comsystem.mem_ctrls.perBankWrBursts::7 66 # Per bank write bursts 6611023Sjthestness@gmail.comsystem.mem_ctrls.perBankWrBursts::8 25 # Per bank write bursts 6711023Sjthestness@gmail.comsystem.mem_ctrls.perBankWrBursts::9 120 # Per bank write bursts 6811023Sjthestness@gmail.comsystem.mem_ctrls.perBankWrBursts::10 125 # Per bank write bursts 6911023Sjthestness@gmail.comsystem.mem_ctrls.perBankWrBursts::11 23 # Per bank write bursts 7010526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::12 2 # Per bank write bursts 7111023Sjthestness@gmail.comsystem.mem_ctrls.perBankWrBursts::13 21 # Per bank write bursts 7210892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::14 8 # Per bank write bursts 7311023Sjthestness@gmail.comsystem.mem_ctrls.perBankWrBursts::15 31 # Per bank write bursts 7410526Snilay@cs.wisc.edusystem.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry 7510526Snilay@cs.wisc.edusystem.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry 7611023Sjthestness@gmail.comsystem.mem_ctrls.totGap 87868 # Total gap between requests 7710526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) 7810526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) 7910526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) 8010526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) 8110526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) 8210526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) 8310526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::6 1377 # Read request sizes (log2) 8410526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) 8510526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) 8610526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) 8710526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) 8810526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) 8910526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) 9010526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::6 1373 # Write request sizes (log2) 9111023Sjthestness@gmail.comsystem.mem_ctrls.rdQLenPdf::0 630 # What read queue length does an incoming req see 9210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see 9310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see 9410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see 9510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see 9610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see 9710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see 9810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see 9910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see 10010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see 10110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see 10210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see 10310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see 10410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see 10510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see 10610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see 10710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see 10810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see 10910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see 11010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see 11110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see 11210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see 11310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see 11410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see 11510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see 11610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see 11710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see 11810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see 11910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see 12010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see 12110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see 12210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see 12310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see 12410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see 12510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see 12610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see 12710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see 12810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see 12910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see 13010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see 13110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see 13210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see 13310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see 13410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see 13510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see 13610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see 13710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see 13811023Sjthestness@gmail.comsystem.mem_ctrls.wrQLenPdf::15 6 # What write queue length does an incoming req see 13911023Sjthestness@gmail.comsystem.mem_ctrls.wrQLenPdf::16 8 # What write queue length does an incoming req see 14011023Sjthestness@gmail.comsystem.mem_ctrls.wrQLenPdf::17 41 # What write queue length does an incoming req see 14111023Sjthestness@gmail.comsystem.mem_ctrls.wrQLenPdf::18 40 # What write queue length does an incoming req see 14211023Sjthestness@gmail.comsystem.mem_ctrls.wrQLenPdf::19 39 # What write queue length does an incoming req see 14311023Sjthestness@gmail.comsystem.mem_ctrls.wrQLenPdf::20 40 # What write queue length does an incoming req see 14411023Sjthestness@gmail.comsystem.mem_ctrls.wrQLenPdf::21 39 # What write queue length does an incoming req see 14511023Sjthestness@gmail.comsystem.mem_ctrls.wrQLenPdf::22 39 # What write queue length does an incoming req see 14611023Sjthestness@gmail.comsystem.mem_ctrls.wrQLenPdf::23 39 # What write queue length does an incoming req see 14711023Sjthestness@gmail.comsystem.mem_ctrls.wrQLenPdf::24 39 # What write queue length does an incoming req see 14811023Sjthestness@gmail.comsystem.mem_ctrls.wrQLenPdf::25 39 # What write queue length does an incoming req see 14911023Sjthestness@gmail.comsystem.mem_ctrls.wrQLenPdf::26 39 # What write queue length does an incoming req see 15011023Sjthestness@gmail.comsystem.mem_ctrls.wrQLenPdf::27 38 # What write queue length does an incoming req see 15111023Sjthestness@gmail.comsystem.mem_ctrls.wrQLenPdf::28 38 # What write queue length does an incoming req see 15211023Sjthestness@gmail.comsystem.mem_ctrls.wrQLenPdf::29 38 # What write queue length does an incoming req see 15311023Sjthestness@gmail.comsystem.mem_ctrls.wrQLenPdf::30 38 # What write queue length does an incoming req see 15411023Sjthestness@gmail.comsystem.mem_ctrls.wrQLenPdf::31 38 # What write queue length does an incoming req see 15511023Sjthestness@gmail.comsystem.mem_ctrls.wrQLenPdf::32 38 # What write queue length does an incoming req see 15610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see 15710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see 15810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see 15910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see 16010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see 16110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see 16210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see 16310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see 16410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see 16510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see 16610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see 16710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see 16810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see 16910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see 17010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see 17110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see 17210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see 17310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see 17410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see 17510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see 17610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see 17710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see 17810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see 17910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see 18010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see 18110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see 18210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see 18310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see 18410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see 18510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see 18610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see 18711023Sjthestness@gmail.comsystem.mem_ctrls.bytesPerActivate::samples 271 # Bytes accessed per row activation 18811023Sjthestness@gmail.comsystem.mem_ctrls.bytesPerActivate::mean 293.313653 # Bytes accessed per row activation 18911023Sjthestness@gmail.comsystem.mem_ctrls.bytesPerActivate::gmean 193.377642 # Bytes accessed per row activation 19011023Sjthestness@gmail.comsystem.mem_ctrls.bytesPerActivate::stdev 283.497497 # Bytes accessed per row activation 19111023Sjthestness@gmail.comsystem.mem_ctrls.bytesPerActivate::0-127 72 26.57% 26.57% # Bytes accessed per row activation 19211023Sjthestness@gmail.comsystem.mem_ctrls.bytesPerActivate::128-255 83 30.63% 57.20% # Bytes accessed per row activation 19311023Sjthestness@gmail.comsystem.mem_ctrls.bytesPerActivate::256-383 37 13.65% 70.85% # Bytes accessed per row activation 19411023Sjthestness@gmail.comsystem.mem_ctrls.bytesPerActivate::384-511 23 8.49% 79.34% # Bytes accessed per row activation 19511023Sjthestness@gmail.comsystem.mem_ctrls.bytesPerActivate::512-639 21 7.75% 87.08% # Bytes accessed per row activation 19611023Sjthestness@gmail.comsystem.mem_ctrls.bytesPerActivate::640-767 5 1.85% 88.93% # Bytes accessed per row activation 19711023Sjthestness@gmail.comsystem.mem_ctrls.bytesPerActivate::768-895 7 2.58% 91.51% # Bytes accessed per row activation 19811023Sjthestness@gmail.comsystem.mem_ctrls.bytesPerActivate::896-1023 3 1.11% 92.62% # Bytes accessed per row activation 19911023Sjthestness@gmail.comsystem.mem_ctrls.bytesPerActivate::1024-1151 20 7.38% 100.00% # Bytes accessed per row activation 20011023Sjthestness@gmail.comsystem.mem_ctrls.bytesPerActivate::total 271 # Bytes accessed per row activation 20111023Sjthestness@gmail.comsystem.mem_ctrls.rdPerTurnAround::samples 38 # Reads before turning the bus around for writes 20211023Sjthestness@gmail.comsystem.mem_ctrls.rdPerTurnAround::mean 16.289474 # Reads before turning the bus around for writes 20311023Sjthestness@gmail.comsystem.mem_ctrls.rdPerTurnAround::gmean 16.048466 # Reads before turning the bus around for writes 20411023Sjthestness@gmail.comsystem.mem_ctrls.rdPerTurnAround::stdev 3.463383 # Reads before turning the bus around for writes 20511023Sjthestness@gmail.comsystem.mem_ctrls.rdPerTurnAround::12-13 1 2.63% 2.63% # Reads before turning the bus around for writes 20611023Sjthestness@gmail.comsystem.mem_ctrls.rdPerTurnAround::14-15 15 39.47% 42.11% # Reads before turning the bus around for writes 20711023Sjthestness@gmail.comsystem.mem_ctrls.rdPerTurnAround::16-17 16 42.11% 84.21% # Reads before turning the bus around for writes 20811023Sjthestness@gmail.comsystem.mem_ctrls.rdPerTurnAround::18-19 4 10.53% 94.74% # Reads before turning the bus around for writes 20911023Sjthestness@gmail.comsystem.mem_ctrls.rdPerTurnAround::20-21 1 2.63% 97.37% # Reads before turning the bus around for writes 21011023Sjthestness@gmail.comsystem.mem_ctrls.rdPerTurnAround::34-35 1 2.63% 100.00% # Reads before turning the bus around for writes 21111023Sjthestness@gmail.comsystem.mem_ctrls.rdPerTurnAround::total 38 # Reads before turning the bus around for writes 21211023Sjthestness@gmail.comsystem.mem_ctrls.wrPerTurnAround::samples 38 # Writes before turning the bus around for reads 21311023Sjthestness@gmail.comsystem.mem_ctrls.wrPerTurnAround::mean 16.421053 # Writes before turning the bus around for reads 21411023Sjthestness@gmail.comsystem.mem_ctrls.wrPerTurnAround::gmean 16.397539 # Writes before turning the bus around for reads 21511023Sjthestness@gmail.comsystem.mem_ctrls.wrPerTurnAround::stdev 0.919212 # Writes before turning the bus around for reads 21611023Sjthestness@gmail.comsystem.mem_ctrls.wrPerTurnAround::16 31 81.58% 81.58% # Writes before turning the bus around for reads 21711023Sjthestness@gmail.comsystem.mem_ctrls.wrPerTurnAround::18 5 13.16% 94.74% # Writes before turning the bus around for reads 21811023Sjthestness@gmail.comsystem.mem_ctrls.wrPerTurnAround::19 2 5.26% 100.00% # Writes before turning the bus around for reads 21911023Sjthestness@gmail.comsystem.mem_ctrls.wrPerTurnAround::total 38 # Writes before turning the bus around for reads 22011023Sjthestness@gmail.comsystem.mem_ctrls.totQLat 9303 # Total ticks spent queuing 22111023Sjthestness@gmail.comsystem.mem_ctrls.totMemAccLat 21273 # Total ticks spent from burst creation until serviced by the DRAM 22211023Sjthestness@gmail.comsystem.mem_ctrls.totBusLat 3150 # Total ticks spent in databus transfers 22311023Sjthestness@gmail.comsystem.mem_ctrls.avgQLat 14.77 # Average queueing delay per DRAM burst 22410526Snilay@cs.wisc.edusystem.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst 22511023Sjthestness@gmail.comsystem.mem_ctrls.avgMemAccLat 33.77 # Average memory access latency per DRAM burst 22611023Sjthestness@gmail.comsystem.mem_ctrls.avgRdBW 458.45 # Average DRAM read bandwidth in MiByte/s 22711023Sjthestness@gmail.comsystem.mem_ctrls.avgWrBW 454.09 # Average achieved write bandwidth in MiByte/s 22811023Sjthestness@gmail.comsystem.mem_ctrls.avgRdBWSys 1002.05 # Average system read bandwidth in MiByte/s 22911023Sjthestness@gmail.comsystem.mem_ctrls.avgWrBWSys 999.14 # Average system write bandwidth in MiByte/s 23010526Snilay@cs.wisc.edusystem.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 23111023Sjthestness@gmail.comsystem.mem_ctrls.busUtil 7.13 # Data bus utilization in percentage 23211023Sjthestness@gmail.comsystem.mem_ctrls.busUtilRead 3.58 # Data bus utilization in percentage for reads 23311023Sjthestness@gmail.comsystem.mem_ctrls.busUtilWrite 3.55 # Data bus utilization in percentage for writes 23410526Snilay@cs.wisc.edusystem.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing 23511023Sjthestness@gmail.comsystem.mem_ctrls.avgWrQLen 25.04 # Average write queue length when enqueuing 23611023Sjthestness@gmail.comsystem.mem_ctrls.readRowHits 420 # Number of row buffer hits during reads 23711023Sjthestness@gmail.comsystem.mem_ctrls.writeRowHits 556 # Number of row buffer hits during writes 23811023Sjthestness@gmail.comsystem.mem_ctrls.readRowHitRate 66.67 # Row buffer hit rate for reads 23911023Sjthestness@gmail.comsystem.mem_ctrls.writeRowHitRate 85.41 # Row buffer hit rate for writes 24011023Sjthestness@gmail.comsystem.mem_ctrls.avgGap 31.95 # Average gap between requests 24111023Sjthestness@gmail.comsystem.mem_ctrls.pageHitRate 76.19 # Row buffer hit rate, read and write combined 24211023Sjthestness@gmail.comsystem.mem_ctrls_0.actEnergy 657720 # Energy for activate commands per rank (pJ) 24311023Sjthestness@gmail.comsystem.mem_ctrls_0.preEnergy 365400 # Energy for precharge commands per rank (pJ) 24411023Sjthestness@gmail.comsystem.mem_ctrls_0.readEnergy 3407040 # Energy for read commands per rank (pJ) 24511023Sjthestness@gmail.comsystem.mem_ctrls_0.writeEnergy 2623104 # Energy for write commands per rank (pJ) 24611023Sjthestness@gmail.comsystem.mem_ctrls_0.refreshEnergy 5594160 # Energy for refresh commands per rank (pJ) 24711023Sjthestness@gmail.comsystem.mem_ctrls_0.actBackEnergy 51093432 # Energy for active background per rank (pJ) 24811023Sjthestness@gmail.comsystem.mem_ctrls_0.preBackEnergy 6724800 # Energy for precharge background per rank (pJ) 24911023Sjthestness@gmail.comsystem.mem_ctrls_0.totalEnergy 70465656 # Total energy per rank (pJ) 25011023Sjthestness@gmail.comsystem.mem_ctrls_0.averagePower 820.264661 # Core power per rank (mW) 25111023Sjthestness@gmail.comsystem.mem_ctrls_0.memoryStateTime::IDLE 10886 # Time in different power states 25211023Sjthestness@gmail.comsystem.mem_ctrls_0.memoryStateTime::REF 2860 # Time in different power states 25310628Sandreas.hansson@arm.comsystem.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states 25411023Sjthestness@gmail.comsystem.mem_ctrls_0.memoryStateTime::ACT 72174 # Time in different power states 25510628Sandreas.hansson@arm.comsystem.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states 25611023Sjthestness@gmail.comsystem.mem_ctrls_1.actEnergy 1368360 # Energy for activate commands per rank (pJ) 25711023Sjthestness@gmail.comsystem.mem_ctrls_1.preEnergy 760200 # Energy for precharge commands per rank (pJ) 25811023Sjthestness@gmail.comsystem.mem_ctrls_1.readEnergy 4268160 # Energy for read commands per rank (pJ) 25911023Sjthestness@gmail.comsystem.mem_ctrls_1.writeEnergy 3680640 # Energy for write commands per rank (pJ) 26011023Sjthestness@gmail.comsystem.mem_ctrls_1.refreshEnergy 5594160 # Energy for refresh commands per rank (pJ) 26111023Sjthestness@gmail.comsystem.mem_ctrls_1.actBackEnergy 54919728 # Energy for active background per rank (pJ) 26211023Sjthestness@gmail.comsystem.mem_ctrls_1.preBackEnergy 3368400 # Energy for precharge background per rank (pJ) 26311023Sjthestness@gmail.comsystem.mem_ctrls_1.totalEnergy 73959648 # Total energy per rank (pJ) 26411023Sjthestness@gmail.comsystem.mem_ctrls_1.averagePower 860.936931 # Core power per rank (mW) 26511023Sjthestness@gmail.comsystem.mem_ctrls_1.memoryStateTime::IDLE 5575 # Time in different power states 26611023Sjthestness@gmail.comsystem.mem_ctrls_1.memoryStateTime::REF 2860 # Time in different power states 26710628Sandreas.hansson@arm.comsystem.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states 26811023Sjthestness@gmail.comsystem.mem_ctrls_1.memoryStateTime::ACT 77782 # Time in different power states 26910628Sandreas.hansson@arm.comsystem.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states 27010526Snilay@cs.wisc.edusystem.cpu.clk_domain.clock 1 # Clock period in ticks 27110036SAli.Saidi@ARM.comsystem.cpu.apic_clk_domain.clock 16 # Clock period in ticks 2728673SN/Asystem.cpu.workload.num_syscalls 11 # Number of system calls 27311023Sjthestness@gmail.comsystem.cpu.numCycles 87948 # number of cpu cycles simulated 2748673SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2757935SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 2769150SAli.Saidi@ARM.comsystem.cpu.committedInsts 5381 # Number of instructions committed 2779583Snilay@cs.wisc.edusystem.cpu.committedOps 9748 # Number of ops (including micro ops) committed 2789924Ssteve.reinhardt@amd.comsystem.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses 2798673SN/Asystem.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 2809702Snilay@cs.wisc.edusystem.cpu.num_func_calls 209 # number of times a function call or return occured 2819150SAli.Saidi@ARM.comsystem.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls 2829924Ssteve.reinhardt@amd.comsystem.cpu.num_int_insts 9654 # number of integer instructions 2837935SN/Asystem.cpu.num_fp_insts 0 # number of float instructions 2849924Ssteve.reinhardt@amd.comsystem.cpu.num_int_register_reads 18335 # number of times the integer registers were read 2859924Ssteve.reinhardt@amd.comsystem.cpu.num_int_register_writes 7527 # number of times the integer registers were written 2867935SN/Asystem.cpu.num_fp_register_reads 0 # number of times the floating registers were read 2877935SN/Asystem.cpu.num_fp_register_writes 0 # number of times the floating registers were written 2889924Ssteve.reinhardt@amd.comsystem.cpu.num_cc_register_reads 6487 # number of times the CC registers were read 2899924Ssteve.reinhardt@amd.comsystem.cpu.num_cc_register_writes 3536 # number of times the CC registers were written 2909583Snilay@cs.wisc.edusystem.cpu.num_mem_refs 1988 # number of memory refs 2919583Snilay@cs.wisc.edusystem.cpu.num_load_insts 1053 # Number of load instructions 2929373Snilay@cs.wisc.edusystem.cpu.num_store_insts 935 # Number of store instructions 29311023Sjthestness@gmail.comsystem.cpu.num_idle_cycles 0.999989 # Number of idle cycles 29411023Sjthestness@gmail.comsystem.cpu.num_busy_cycles 87947.000011 # Number of busy cycles 29511023Sjthestness@gmail.comsystem.cpu.not_idle_fraction 0.999989 # Percentage of non-idle cycles 29611023Sjthestness@gmail.comsystem.cpu.idle_fraction 0.000011 # Percentage of idle cycles 29710063Snilay@cs.wisc.edusystem.cpu.Branches 1208 # Number of branches fetched 29810220Sandreas.hansson@arm.comsystem.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction 29910220Sandreas.hansson@arm.comsystem.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction 30010220Sandreas.hansson@arm.comsystem.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction 30110220Sandreas.hansson@arm.comsystem.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction 30210220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction 30310220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction 30410220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction 30510220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction 30610220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction 30710220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction 30810220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction 30910220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction 31010220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction 31110220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction 31210220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction 31310220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction 31410220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction 31510220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction 31610220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction 31710220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction 31810220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction 31910220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction 32010220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction 32110220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction 32210220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction 32310220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction 32410220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction 32510220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction 32610220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction 32710220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction 32810220Sandreas.hansson@arm.comsystem.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction 32910220Sandreas.hansson@arm.comsystem.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction 33010220Sandreas.hansson@arm.comsystem.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 33110220Sandreas.hansson@arm.comsystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 33210220Sandreas.hansson@arm.comsystem.cpu.op_class::total 9748 # Class of executed instruction 33310628Sandreas.hansson@arm.comsystem.ruby.clk_domain.clock 1 # Clock period in ticks 33410628Sandreas.hansson@arm.comsystem.ruby.delayHist::bucket_size 1 # delay histogram for all message 33510628Sandreas.hansson@arm.comsystem.ruby.delayHist::max_bucket 9 # delay histogram for all message 33610628Sandreas.hansson@arm.comsystem.ruby.delayHist::samples 2750 # delay histogram for all message 33710628Sandreas.hansson@arm.comsystem.ruby.delayHist | 2750 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message 33810628Sandreas.hansson@arm.comsystem.ruby.delayHist::total 2750 # delay histogram for all message 33911312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::bucket_size 1 34011312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::max_bucket 9 34111312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::samples 8852 34211312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::mean 1 34311312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::gmean 1 34411312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8852 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 34511312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::total 8852 34611312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_seqr::bucket_size 64 34711312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_seqr::max_bucket 639 34811312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_seqr::samples 8852 34911312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_seqr::mean 8.935382 35011312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_seqr::gmean 1.815175 35111312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_seqr::stdev 22.675647 35211312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_seqr | 8624 97.42% 97.42% | 191 2.16% 99.58% | 24 0.27% 99.85% | 5 0.06% 99.91% | 2 0.02% 99.93% | 6 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 35311312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_seqr::total 8852 35411312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr::bucket_size 1 35511312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr::max_bucket 9 35611312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr::samples 7475 35711312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr::mean 1 35811312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr::gmean 1 35911312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 7475 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 36011312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr::total 7475 36111312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr::bucket_size 64 36211312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr::max_bucket 639 36311312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr::samples 1377 36411312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr::mean 52.012346 36511312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr::gmean 46.179478 36611312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr::stdev 33.292581 36711312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr | 1149 83.44% 83.44% | 191 13.87% 97.31% | 24 1.74% 99.06% | 5 0.36% 99.42% | 2 0.15% 99.56% | 6 0.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 36811312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr::total 1377 36911312Santhony.gutierrez@amd.comsystem.ruby.Directory.incomplete_times_seqr 1376 37010628Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 # Number of cache demand hits 37110628Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.cacheMemory.demand_misses 1377 # Number of cache demand misses 37210628Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.cacheMemory.demand_accesses 8852 # Number of cache demand accesses 37310628Sandreas.hansson@arm.comsystem.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks 37411023Sjthestness@gmail.comsystem.ruby.network.routers0.percent_links_utilized 7.817119 37510628Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Control::2 1377 37610628Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Data::2 1373 37710628Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Response_Data::4 1377 37810628Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Writeback_Control::3 1373 37910628Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Control::2 11016 38010628Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Data::2 98856 38110628Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Response_Data::4 99144 38210628Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Writeback_Control::3 10984 38311023Sjthestness@gmail.comsystem.ruby.network.routers1.percent_links_utilized 7.817119 38410628Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Control::2 1377 38510628Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Data::2 1373 38610628Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Response_Data::4 1377 38710628Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Writeback_Control::3 1373 38810628Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Control::2 11016 38910628Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Data::2 98856 39010628Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Response_Data::4 99144 39110628Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Writeback_Control::3 10984 39211023Sjthestness@gmail.comsystem.ruby.network.routers2.percent_links_utilized 7.817119 39310628Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Control::2 1377 39410628Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Data::2 1373 39510628Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Response_Data::4 1377 39610628Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Writeback_Control::3 1373 39710628Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Control::2 11016 39810628Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Data::2 98856 39910628Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Response_Data::4 99144 40010628Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Writeback_Control::3 10984 40110628Sandreas.hansson@arm.comsystem.ruby.network.msg_count.Control 4131 40210628Sandreas.hansson@arm.comsystem.ruby.network.msg_count.Data 4119 40310628Sandreas.hansson@arm.comsystem.ruby.network.msg_count.Response_Data 4131 40410628Sandreas.hansson@arm.comsystem.ruby.network.msg_count.Writeback_Control 4119 40510628Sandreas.hansson@arm.comsystem.ruby.network.msg_byte.Control 33048 40610628Sandreas.hansson@arm.comsystem.ruby.network.msg_byte.Data 296568 40710628Sandreas.hansson@arm.comsystem.ruby.network.msg_byte.Response_Data 297432 40810628Sandreas.hansson@arm.comsystem.ruby.network.msg_byte.Writeback_Control 32952 40911023Sjthestness@gmail.comsystem.ruby.network.routers0.throttle0.link_utilization 7.826215 4109864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1377 4119864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1373 4129864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 99144 4139864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 10984 41411023Sjthestness@gmail.comsystem.ruby.network.routers0.throttle1.link_utilization 7.808023 4159864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Control::2 1377 4169864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Data::2 1373 4179864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Control::2 11016 4189864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Data::2 98856 41911023Sjthestness@gmail.comsystem.ruby.network.routers1.throttle0.link_utilization 7.808023 4209864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_count.Control::2 1377 4219864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_count.Data::2 1373 4229864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_bytes.Control::2 11016 4239864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_bytes.Data::2 98856 42411023Sjthestness@gmail.comsystem.ruby.network.routers1.throttle1.link_utilization 7.826215 4259864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1377 4269864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1373 4279864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 99144 4289864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 10984 42911023Sjthestness@gmail.comsystem.ruby.network.routers2.throttle0.link_utilization 7.826215 4309864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1377 4319864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1373 4329864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 99144 4339864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 10984 43411023Sjthestness@gmail.comsystem.ruby.network.routers2.throttle1.link_utilization 7.808023 4359864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_count.Control::2 1377 4369864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_count.Data::2 1373 4379864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_bytes.Control::2 11016 4389864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_bytes.Data::2 98856 43910013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 44010013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 44110013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::samples 1377 # delay histogram for vnet_1 44210013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1 | 1377 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 44310013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::total 1377 # delay histogram for vnet_1 44410013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 44510013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 44610013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::samples 1373 # delay histogram for vnet_2 44710013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2 | 1373 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 44810013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::total 1373 # delay histogram for vnet_2 44911312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_seqr::bucket_size 32 45011312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_seqr::max_bucket 319 45111312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_seqr::samples 1045 45211312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_seqr::mean 22.607656 45311312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_seqr::gmean 5.952637 45411312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_seqr::stdev 28.358291 45511312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_seqr | 546 52.25% 52.25% | 420 40.19% 92.44% | 70 6.70% 99.14% | 2 0.19% 99.33% | 2 0.19% 99.52% | 4 0.38% 99.90% | 0 0.00% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 45611312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_seqr::total 1045 45711312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr::bucket_size 1 45811312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr::max_bucket 9 45911312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr::samples 546 46011312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr::mean 1 46111312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr::gmean 1 46211312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 546 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 46311312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr::total 546 46411312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_seqr::bucket_size 32 46511312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_seqr::max_bucket 319 46611312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_seqr::samples 499 46711312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_seqr::mean 46.250501 46811312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_seqr::gmean 41.916728 46911312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_seqr::stdev 24.776985 47011312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 420 84.17% 84.17% | 70 14.03% 98.20% | 2 0.40% 98.60% | 2 0.40% 99.00% | 4 0.80% 99.80% | 0 0.00% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 47111312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_seqr::total 499 47211312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_seqr::bucket_size 64 47311312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_seqr::max_bucket 639 47411312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_seqr::samples 935 47511312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_seqr::mean 15.124064 47611312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_seqr::gmean 2.829099 47711312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_seqr::stdev 31.003309 47811312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_seqr | 897 95.94% 95.94% | 28 2.99% 98.93% | 5 0.53% 99.47% | 3 0.32% 99.79% | 0 0.00% 99.79% | 2 0.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 47911312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_seqr::total 935 48011312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::bucket_size 1 48111312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::max_bucket 9 48211312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::samples 681 48311312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::mean 1 48411312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::gmean 1 48511312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 681 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 48611312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::total 681 48711312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr::bucket_size 64 48811312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr::max_bucket 639 48911312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr::samples 254 49011312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr::mean 52.992126 49111312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr::gmean 45.979346 49211312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr::stdev 39.646660 49311312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr | 216 85.04% 85.04% | 28 11.02% 96.06% | 5 1.97% 98.03% | 3 1.18% 99.21% | 0 0.00% 99.21% | 2 0.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 49411312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr::total 254 49511312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist_seqr::bucket_size 64 49611312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist_seqr::max_bucket 639 49711312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist_seqr::samples 6864 49811312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist_seqr::mean 6.015589 49911312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist_seqr::gmean 1.426336 50011312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist_seqr::stdev 19.173758 50111312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist_seqr | 6753 98.38% 98.38% | 91 1.33% 99.71% | 13 0.19% 99.90% | 1 0.01% 99.91% | 2 0.03% 99.94% | 4 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 50211312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist_seqr::total 6864 50311312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 50411312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 50511312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::samples 6241 50611312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::mean 1 50711312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 50811312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 6241 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 50911312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::total 6241 51011312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 51111312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 51211312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::samples 623 51311312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::mean 56.260032 51411312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::gmean 50.022291 51511312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::stdev 35.712767 51611312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr | 512 82.18% 82.18% | 91 14.61% 96.79% | 13 2.09% 98.88% | 1 0.16% 99.04% | 2 0.32% 99.36% | 4 0.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 51711312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::total 623 51811312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist_seqr::bucket_size 4 51911312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist_seqr::max_bucket 39 52011312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist_seqr::samples 8 52111312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist_seqr::mean 4.875000 52211312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist_seqr::gmean 1.542211 52311312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist_seqr::stdev 10.960155 52411312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist_seqr | 7 87.50% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 1 12.50% 100.00% | 0 0.00% 100.00% 52511312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist_seqr::total 8 52611312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist_seqr::bucket_size 1 52711312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist_seqr::max_bucket 9 52811312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist_seqr::samples 7 52911312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist_seqr::mean 1 53011312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist_seqr::gmean 1 53111312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist_seqr | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 53211312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist_seqr::total 7 53311312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr::bucket_size 4 53411312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr::max_bucket 39 53511312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr::samples 1 53611312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr::mean 32 53711312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr::gmean 32 53811312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr::stdev nan 53911312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% 54011312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr::total 1 54111312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 54211312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 54311312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_mach_latency_hist_seqr::samples 1377 54411312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_mach_latency_hist_seqr::mean 52.012346 54511312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_mach_latency_hist_seqr::gmean 46.179478 54611312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_mach_latency_hist_seqr::stdev 33.292581 54711312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_mach_latency_hist_seqr | 1149 83.44% 83.44% | 191 13.87% 97.31% | 24 1.74% 99.06% | 5 0.36% 99.42% | 2 0.15% 99.56% | 6 0.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 54811312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_mach_latency_hist_seqr::total 1377 54911312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 55011312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 55111312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 55211312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan 55311312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 55411312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 55511312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 55611312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 55711312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 55811312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan 55911312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 56011312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 56111312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 56211312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 56311312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 56411312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan 56511312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 56611312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 56711312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8 56811312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 56911312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 57011312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 57111312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 57211312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan 57311312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% 57411312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 57511312Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 57611312Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 57711312Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 499 57811312Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 46.250501 57911312Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 41.916728 58011312Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 24.776985 58111312Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 420 84.17% 84.17% | 70 14.03% 98.20% | 2 0.40% 98.60% | 2 0.40% 99.00% | 4 0.80% 99.80% | 0 0.00% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 58211312Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 499 58311312Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 58411312Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 58511312Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 254 58611312Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 52.992126 58711312Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 45.979346 58811312Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 39.646660 58911312Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 216 85.04% 85.04% | 28 11.02% 96.06% | 5 1.97% 98.03% | 3 1.18% 99.21% | 0 0.00% 99.21% | 2 0.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 59011312Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 254 59111312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 59211312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 59311312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 623 59411312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 56.260032 59511312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 50.022291 59611312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 35.712767 59711312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 512 82.18% 82.18% | 91 14.61% 96.79% | 13 2.09% 98.88% | 1 0.16% 99.04% | 2 0.32% 99.36% | 4 0.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 59811312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 623 59911312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist_seqr::bucket_size 4 60011312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist_seqr::max_bucket 39 60111312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist_seqr::samples 1 60211312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist_seqr::mean 32 60311312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist_seqr::gmean 32 60411312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist_seqr::stdev nan 60511312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% 60611312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist_seqr::total 1 60710628Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.GETX 1377 0.00% 0.00% 60810628Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.PUTX 1373 0.00% 0.00% 60910628Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.Memory_Data 1377 0.00% 0.00% 61010628Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.Memory_Ack 1373 0.00% 0.00% 61110628Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.I.GETX 1377 0.00% 0.00% 61210628Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.M.PUTX 1373 0.00% 0.00% 61310628Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.IM.Memory_Data 1377 0.00% 0.00% 61410628Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.MI.Memory_Ack 1373 0.00% 0.00% 61510013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Load 1045 0.00% 0.00% 61610013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Ifetch 6864 0.00% 0.00% 61710013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Store 943 0.00% 0.00% 61810013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Data 1377 0.00% 0.00% 61910013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Replacement 1373 0.00% 0.00% 62010013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Writeback_Ack 1373 0.00% 0.00% 62110013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Load 499 0.00% 0.00% 62210013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Ifetch 623 0.00% 0.00% 62310013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Store 255 0.00% 0.00% 62410013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Load 546 0.00% 0.00% 62510013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Ifetch 6241 0.00% 0.00% 62610013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Store 688 0.00% 0.00% 62710013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Replacement 1373 0.00% 0.00% 62810013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.MI.Writeback_Ack 1373 0.00% 0.00% 62910013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IS.Data 1122 0.00% 0.00% 63010013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IM.Data 255 0.00% 0.00% 6316167SN/A 6326167SN/A---------- End Simulation Statistics ---------- 633