stats.txt revision 10892
16167SN/A 26167SN/A---------- Begin Simulation Statistics ---------- 310526Snilay@cs.wisc.edusim_seconds 0.000107 # Number of seconds simulated 410892Sandreas.hansson@arm.comsim_ticks 107256 # Number of ticks simulated 510892Sandreas.hansson@arm.comfinal_tick 107256 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68673SN/Asim_freq 1000000000 # Frequency of simulated ticks 710892Sandreas.hansson@arm.comhost_inst_rate 57113 # Simulator instruction rate (inst/s) 810892Sandreas.hansson@arm.comhost_op_rate 103447 # Simulator op (including micro ops) rate (op/s) 910892Sandreas.hansson@arm.comhost_tick_rate 1138055 # Simulator tick rate (ticks/s) 1010892Sandreas.hansson@arm.comhost_mem_usage 467864 # Number of bytes of host memory used 1110628Sandreas.hansson@arm.comhost_seconds 0.09 # Real time elapsed on the host 129150SAli.Saidi@ARM.comsim_insts 5381 # Number of instructions simulated 139583Snilay@cs.wisc.edusim_ops 9748 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1 # Clock period in ticks 1610526Snilay@cs.wisc.edusystem.mem_ctrls.bytes_read::ruby.dir_cntrl0 88128 # Number of bytes read from this memory 1710526Snilay@cs.wisc.edusystem.mem_ctrls.bytes_read::total 88128 # Number of bytes read from this memory 1810526Snilay@cs.wisc.edusystem.mem_ctrls.bytes_written::ruby.dir_cntrl0 87872 # Number of bytes written to this memory 1910526Snilay@cs.wisc.edusystem.mem_ctrls.bytes_written::total 87872 # Number of bytes written to this memory 2010526Snilay@cs.wisc.edusystem.mem_ctrls.num_reads::ruby.dir_cntrl0 1377 # Number of read requests responded to by this memory 2110526Snilay@cs.wisc.edusystem.mem_ctrls.num_reads::total 1377 # Number of read requests responded to by this memory 2210526Snilay@cs.wisc.edusystem.mem_ctrls.num_writes::ruby.dir_cntrl0 1373 # Number of write requests responded to by this memory 2310526Snilay@cs.wisc.edusystem.mem_ctrls.num_writes::total 1373 # Number of write requests responded to by this memory 2410892Sandreas.hansson@arm.comsystem.mem_ctrls.bw_read::ruby.dir_cntrl0 821660327 # Total read bandwidth from this memory (bytes/s) 2510892Sandreas.hansson@arm.comsystem.mem_ctrls.bw_read::total 821660327 # Total read bandwidth from this memory (bytes/s) 2610892Sandreas.hansson@arm.comsystem.mem_ctrls.bw_write::ruby.dir_cntrl0 819273514 # Write bandwidth from this memory (bytes/s) 2710892Sandreas.hansson@arm.comsystem.mem_ctrls.bw_write::total 819273514 # Write bandwidth from this memory (bytes/s) 2810892Sandreas.hansson@arm.comsystem.mem_ctrls.bw_total::ruby.dir_cntrl0 1640933841 # Total bandwidth to/from this memory (bytes/s) 2910892Sandreas.hansson@arm.comsystem.mem_ctrls.bw_total::total 1640933841 # Total bandwidth to/from this memory (bytes/s) 3010526Snilay@cs.wisc.edusystem.mem_ctrls.readReqs 1377 # Number of read requests accepted 3110526Snilay@cs.wisc.edusystem.mem_ctrls.writeReqs 1373 # Number of write requests accepted 3210526Snilay@cs.wisc.edusystem.mem_ctrls.readBursts 1377 # Number of DRAM read bursts, including those serviced by the write queue 3310526Snilay@cs.wisc.edusystem.mem_ctrls.writeBursts 1373 # Number of DRAM write bursts, including those merged in the write queue 3410892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesReadDRAM 43264 # Total number of bytes read from DRAM 3510892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesReadWrQ 44864 # Total number of bytes read from write queue 3610892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesWritten 43264 # Total number of bytes written to DRAM 3710526Snilay@cs.wisc.edusystem.mem_ctrls.bytesReadSys 88128 # Total read bytes from the system interface side 3810526Snilay@cs.wisc.edusystem.mem_ctrls.bytesWrittenSys 87872 # Total written bytes from the system interface side 3910892Sandreas.hansson@arm.comsystem.mem_ctrls.servicedByWrQ 701 # Number of DRAM read bursts serviced by the write queue 4010892Sandreas.hansson@arm.comsystem.mem_ctrls.mergedWrBursts 674 # Number of DRAM write bursts merged with an existing one 4110526Snilay@cs.wisc.edusystem.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 4210892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::0 56 # Per bank write bursts 4310526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::1 1 # Per bank write bursts 4410526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::2 6 # Per bank write bursts 4510892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::3 12 # Per bank write bursts 4610892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::4 54 # Per bank write bursts 4710892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::5 56 # Per bank write bursts 4810892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::6 43 # Per bank write bursts 4910892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::7 70 # Per bank write bursts 5010892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::8 29 # Per bank write bursts 5110892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::9 129 # Per bank write bursts 5210892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::10 124 # Per bank write bursts 5310892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::11 21 # Per bank write bursts 5410526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::12 2 # Per bank write bursts 5510892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::13 34 # Per bank write bursts 5610892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::14 8 # Per bank write bursts 5710892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::15 31 # Per bank write bursts 5810526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::0 50 # Per bank write bursts 5910526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::1 1 # Per bank write bursts 6010526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::2 6 # Per bank write bursts 6110892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::3 11 # Per bank write bursts 6210892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::4 54 # Per bank write bursts 6310892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::5 54 # Per bank write bursts 6410892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::6 41 # Per bank write bursts 6510892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::7 72 # Per bank write bursts 6610892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::8 30 # Per bank write bursts 6710892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::9 129 # Per bank write bursts 6810526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::10 129 # Per bank write bursts 6910892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::11 21 # Per bank write bursts 7010526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::12 2 # Per bank write bursts 7110892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::13 36 # Per bank write bursts 7210892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::14 8 # Per bank write bursts 7310892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::15 32 # Per bank write bursts 7410526Snilay@cs.wisc.edusystem.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry 7510526Snilay@cs.wisc.edusystem.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry 7610892Sandreas.hansson@arm.comsystem.mem_ctrls.totGap 107152 # Total gap between requests 7710526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) 7810526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) 7910526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) 8010526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) 8110526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) 8210526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) 8310526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::6 1377 # Read request sizes (log2) 8410526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) 8510526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) 8610526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) 8710526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) 8810526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) 8910526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) 9010526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::6 1373 # Write request sizes (log2) 9110892Sandreas.hansson@arm.comsystem.mem_ctrls.rdQLenPdf::0 676 # What read queue length does an incoming req see 9210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see 9310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see 9410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see 9510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see 9610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see 9710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see 9810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see 9910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see 10010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see 10110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see 10210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see 10310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see 10410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see 10510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see 10610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see 10710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see 10810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see 10910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see 11010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see 11110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see 11210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see 11310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see 11410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see 11510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see 11610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see 11710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see 11810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see 11910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see 12010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see 12110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see 12210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see 12310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see 12410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see 12510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see 12610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see 12710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see 12810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see 12910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see 13010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see 13110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see 13210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see 13310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see 13410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see 13510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see 13610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see 13710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see 13810892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::15 7 # What write queue length does an incoming req see 13910892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::16 10 # What write queue length does an incoming req see 14010892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::17 40 # What write queue length does an incoming req see 14110892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::18 45 # What write queue length does an incoming req see 14210892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::19 43 # What write queue length does an incoming req see 14310892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::20 44 # What write queue length does an incoming req see 14410892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::21 42 # What write queue length does an incoming req see 14510892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::22 43 # What write queue length does an incoming req see 14610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::23 41 # What write queue length does an incoming req see 14710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::24 41 # What write queue length does an incoming req see 14810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::25 41 # What write queue length does an incoming req see 14910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::26 41 # What write queue length does an incoming req see 15010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::27 41 # What write queue length does an incoming req see 15110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::28 41 # What write queue length does an incoming req see 15210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::29 41 # What write queue length does an incoming req see 15310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::30 41 # What write queue length does an incoming req see 15410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::31 41 # What write queue length does an incoming req see 15510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::32 41 # What write queue length does an incoming req see 15610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see 15710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see 15810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see 15910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see 16010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see 16110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see 16210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see 16310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see 16410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see 16510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see 16610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see 16710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see 16810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see 16910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see 17010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see 17110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see 17210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see 17310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see 17410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see 17510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see 17610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see 17710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see 17810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see 17910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see 18010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see 18110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see 18210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see 18310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see 18410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see 18510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see 18610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see 18710892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::samples 276 # Bytes accessed per row activation 18810892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::mean 306.782609 # Bytes accessed per row activation 18910892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::gmean 194.488181 # Bytes accessed per row activation 19010892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::stdev 303.473845 # Bytes accessed per row activation 19110892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::0-127 80 28.99% 28.99% # Bytes accessed per row activation 19210892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::128-255 80 28.99% 57.97% # Bytes accessed per row activation 19310892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::256-383 33 11.96% 69.93% # Bytes accessed per row activation 19410892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::384-511 22 7.97% 77.90% # Bytes accessed per row activation 19510892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::512-639 18 6.52% 84.42% # Bytes accessed per row activation 19610892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::640-767 7 2.54% 86.96% # Bytes accessed per row activation 19710892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::768-895 7 2.54% 89.49% # Bytes accessed per row activation 19810892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::896-1023 4 1.45% 90.94% # Bytes accessed per row activation 19910892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::1024-1151 25 9.06% 100.00% # Bytes accessed per row activation 20010892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::total 276 # Bytes accessed per row activation 20110526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::samples 41 # Reads before turning the bus around for writes 20210892Sandreas.hansson@arm.comsystem.mem_ctrls.rdPerTurnAround::mean 16.243902 # Reads before turning the bus around for writes 20310892Sandreas.hansson@arm.comsystem.mem_ctrls.rdPerTurnAround::gmean 16.023325 # Reads before turning the bus around for writes 20410892Sandreas.hansson@arm.comsystem.mem_ctrls.rdPerTurnAround::stdev 3.314970 # Reads before turning the bus around for writes 20510892Sandreas.hansson@arm.comsystem.mem_ctrls.rdPerTurnAround::12-13 1 2.44% 2.44% # Reads before turning the bus around for writes 20610892Sandreas.hansson@arm.comsystem.mem_ctrls.rdPerTurnAround::14-15 16 39.02% 41.46% # Reads before turning the bus around for writes 20710892Sandreas.hansson@arm.comsystem.mem_ctrls.rdPerTurnAround::16-17 18 43.90% 85.37% # Reads before turning the bus around for writes 20810892Sandreas.hansson@arm.comsystem.mem_ctrls.rdPerTurnAround::18-19 5 12.20% 97.56% # Reads before turning the bus around for writes 20910526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::34-35 1 2.44% 100.00% # Reads before turning the bus around for writes 21010526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::total 41 # Reads before turning the bus around for writes 21110526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::samples 41 # Writes before turning the bus around for reads 21210892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::mean 16.487805 # Writes before turning the bus around for reads 21310892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::gmean 16.459950 # Writes before turning the bus around for reads 21410892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::stdev 1.003044 # Writes before turning the bus around for reads 21510892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::16 32 78.05% 78.05% # Writes before turning the bus around for reads 21610892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::17 2 4.88% 82.93% # Writes before turning the bus around for reads 21710892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::18 3 7.32% 90.24% # Writes before turning the bus around for reads 21810892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::19 4 9.76% 100.00% # Writes before turning the bus around for reads 21910526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::total 41 # Writes before turning the bus around for reads 22010892Sandreas.hansson@arm.comsystem.mem_ctrls.totQLat 9573 # Total ticks spent queuing 22110892Sandreas.hansson@arm.comsystem.mem_ctrls.totMemAccLat 22417 # Total ticks spent from burst creation until serviced by the DRAM 22210892Sandreas.hansson@arm.comsystem.mem_ctrls.totBusLat 3380 # Total ticks spent in databus transfers 22310892Sandreas.hansson@arm.comsystem.mem_ctrls.avgQLat 14.16 # Average queueing delay per DRAM burst 22410526Snilay@cs.wisc.edusystem.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst 22510892Sandreas.hansson@arm.comsystem.mem_ctrls.avgMemAccLat 33.16 # Average memory access latency per DRAM burst 22610892Sandreas.hansson@arm.comsystem.mem_ctrls.avgRdBW 403.37 # Average DRAM read bandwidth in MiByte/s 22710892Sandreas.hansson@arm.comsystem.mem_ctrls.avgWrBW 403.37 # Average achieved write bandwidth in MiByte/s 22810892Sandreas.hansson@arm.comsystem.mem_ctrls.avgRdBWSys 821.66 # Average system read bandwidth in MiByte/s 22910892Sandreas.hansson@arm.comsystem.mem_ctrls.avgWrBWSys 819.27 # Average system write bandwidth in MiByte/s 23010526Snilay@cs.wisc.edusystem.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 23110892Sandreas.hansson@arm.comsystem.mem_ctrls.busUtil 6.30 # Data bus utilization in percentage 23210892Sandreas.hansson@arm.comsystem.mem_ctrls.busUtilRead 3.15 # Data bus utilization in percentage for reads 23310892Sandreas.hansson@arm.comsystem.mem_ctrls.busUtilWrite 3.15 # Data bus utilization in percentage for writes 23410526Snilay@cs.wisc.edusystem.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing 23510892Sandreas.hansson@arm.comsystem.mem_ctrls.avgWrQLen 25.88 # Average write queue length when enqueuing 23610892Sandreas.hansson@arm.comsystem.mem_ctrls.readRowHits 443 # Number of row buffer hits during reads 23710892Sandreas.hansson@arm.comsystem.mem_ctrls.writeRowHits 622 # Number of row buffer hits during writes 23810892Sandreas.hansson@arm.comsystem.mem_ctrls.readRowHitRate 65.53 # Row buffer hit rate for reads 23910892Sandreas.hansson@arm.comsystem.mem_ctrls.writeRowHitRate 88.98 # Row buffer hit rate for writes 24010526Snilay@cs.wisc.edusystem.mem_ctrls.avgGap 38.96 # Average gap between requests 24110892Sandreas.hansson@arm.comsystem.mem_ctrls.pageHitRate 77.45 # Row buffer hit rate, read and write combined 24210892Sandreas.hansson@arm.comsystem.mem_ctrls_0.actEnergy 703080 # Energy for activate commands per rank (pJ) 24310892Sandreas.hansson@arm.comsystem.mem_ctrls_0.preEnergy 390600 # Energy for precharge commands per rank (pJ) 24410892Sandreas.hansson@arm.comsystem.mem_ctrls_0.readEnergy 3319680 # Energy for read commands per rank (pJ) 24510892Sandreas.hansson@arm.comsystem.mem_ctrls_0.writeEnergy 2685312 # Energy for write commands per rank (pJ) 24610628Sandreas.hansson@arm.comsystem.mem_ctrls_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) 24710892Sandreas.hansson@arm.comsystem.mem_ctrls_0.actBackEnergy 57105108 # Energy for active background per rank (pJ) 24810892Sandreas.hansson@arm.comsystem.mem_ctrls_0.preBackEnergy 10794600 # Energy for precharge background per rank (pJ) 24910892Sandreas.hansson@arm.comsystem.mem_ctrls_0.totalEnergy 81609660 # Total energy per rank (pJ) 25010892Sandreas.hansson@arm.comsystem.mem_ctrls_0.averagePower 804.210371 # Core power per rank (mW) 25110892Sandreas.hansson@arm.comsystem.mem_ctrls_0.memoryStateTime::IDLE 17627 # Time in different power states 25210628Sandreas.hansson@arm.comsystem.mem_ctrls_0.memoryStateTime::REF 3380 # Time in different power states 25310628Sandreas.hansson@arm.comsystem.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states 25410892Sandreas.hansson@arm.comsystem.mem_ctrls_0.memoryStateTime::ACT 80485 # Time in different power states 25510628Sandreas.hansson@arm.comsystem.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states 25610892Sandreas.hansson@arm.comsystem.mem_ctrls_1.actEnergy 1292760 # Energy for activate commands per rank (pJ) 25710892Sandreas.hansson@arm.comsystem.mem_ctrls_1.preEnergy 718200 # Energy for precharge commands per rank (pJ) 25810892Sandreas.hansson@arm.comsystem.mem_ctrls_1.readEnergy 4630080 # Energy for read commands per rank (pJ) 25910892Sandreas.hansson@arm.comsystem.mem_ctrls_1.writeEnergy 3805056 # Energy for write commands per rank (pJ) 26010628Sandreas.hansson@arm.comsystem.mem_ctrls_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) 26110892Sandreas.hansson@arm.comsystem.mem_ctrls_1.actBackEnergy 62793936 # Energy for active background per rank (pJ) 26210892Sandreas.hansson@arm.comsystem.mem_ctrls_1.preBackEnergy 5804400 # Energy for precharge background per rank (pJ) 26310892Sandreas.hansson@arm.comsystem.mem_ctrls_1.totalEnergy 85655712 # Total energy per rank (pJ) 26410892Sandreas.hansson@arm.comsystem.mem_ctrls_1.averagePower 844.081594 # Core power per rank (mW) 26510892Sandreas.hansson@arm.comsystem.mem_ctrls_1.memoryStateTime::IDLE 9408 # Time in different power states 26610628Sandreas.hansson@arm.comsystem.mem_ctrls_1.memoryStateTime::REF 3380 # Time in different power states 26710628Sandreas.hansson@arm.comsystem.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states 26810892Sandreas.hansson@arm.comsystem.mem_ctrls_1.memoryStateTime::ACT 88844 # Time in different power states 26910628Sandreas.hansson@arm.comsystem.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states 27010526Snilay@cs.wisc.edusystem.cpu.clk_domain.clock 1 # Clock period in ticks 27110036SAli.Saidi@ARM.comsystem.cpu.apic_clk_domain.clock 16 # Clock period in ticks 2728673SN/Asystem.cpu.workload.num_syscalls 11 # Number of system calls 27310892Sandreas.hansson@arm.comsystem.cpu.numCycles 107256 # number of cpu cycles simulated 2748673SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2757935SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 2769150SAli.Saidi@ARM.comsystem.cpu.committedInsts 5381 # Number of instructions committed 2779583Snilay@cs.wisc.edusystem.cpu.committedOps 9748 # Number of ops (including micro ops) committed 2789924Ssteve.reinhardt@amd.comsystem.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses 2798673SN/Asystem.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 2809702Snilay@cs.wisc.edusystem.cpu.num_func_calls 209 # number of times a function call or return occured 2819150SAli.Saidi@ARM.comsystem.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls 2829924Ssteve.reinhardt@amd.comsystem.cpu.num_int_insts 9654 # number of integer instructions 2837935SN/Asystem.cpu.num_fp_insts 0 # number of float instructions 2849924Ssteve.reinhardt@amd.comsystem.cpu.num_int_register_reads 18335 # number of times the integer registers were read 2859924Ssteve.reinhardt@amd.comsystem.cpu.num_int_register_writes 7527 # number of times the integer registers were written 2867935SN/Asystem.cpu.num_fp_register_reads 0 # number of times the floating registers were read 2877935SN/Asystem.cpu.num_fp_register_writes 0 # number of times the floating registers were written 2889924Ssteve.reinhardt@amd.comsystem.cpu.num_cc_register_reads 6487 # number of times the CC registers were read 2899924Ssteve.reinhardt@amd.comsystem.cpu.num_cc_register_writes 3536 # number of times the CC registers were written 2909583Snilay@cs.wisc.edusystem.cpu.num_mem_refs 1988 # number of memory refs 2919583Snilay@cs.wisc.edusystem.cpu.num_load_insts 1053 # Number of load instructions 2929373Snilay@cs.wisc.edusystem.cpu.num_store_insts 935 # Number of store instructions 29310526Snilay@cs.wisc.edusystem.cpu.num_idle_cycles 0.999991 # Number of idle cycles 29410892Sandreas.hansson@arm.comsystem.cpu.num_busy_cycles 107255.000009 # Number of busy cycles 29510526Snilay@cs.wisc.edusystem.cpu.not_idle_fraction 0.999991 # Percentage of non-idle cycles 29610526Snilay@cs.wisc.edusystem.cpu.idle_fraction 0.000009 # Percentage of idle cycles 29710063Snilay@cs.wisc.edusystem.cpu.Branches 1208 # Number of branches fetched 29810220Sandreas.hansson@arm.comsystem.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction 29910220Sandreas.hansson@arm.comsystem.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction 30010220Sandreas.hansson@arm.comsystem.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction 30110220Sandreas.hansson@arm.comsystem.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction 30210220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction 30310220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction 30410220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction 30510220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction 30610220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction 30710220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction 30810220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction 30910220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction 31010220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction 31110220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction 31210220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction 31310220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction 31410220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction 31510220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction 31610220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction 31710220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction 31810220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction 31910220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction 32010220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction 32110220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction 32210220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction 32310220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction 32410220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction 32510220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction 32610220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction 32710220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction 32810220Sandreas.hansson@arm.comsystem.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction 32910220Sandreas.hansson@arm.comsystem.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction 33010220Sandreas.hansson@arm.comsystem.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 33110220Sandreas.hansson@arm.comsystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 33210220Sandreas.hansson@arm.comsystem.cpu.op_class::total 9748 # Class of executed instruction 33310628Sandreas.hansson@arm.comsystem.ruby.clk_domain.clock 1 # Clock period in ticks 33410628Sandreas.hansson@arm.comsystem.ruby.delayHist::bucket_size 1 # delay histogram for all message 33510628Sandreas.hansson@arm.comsystem.ruby.delayHist::max_bucket 9 # delay histogram for all message 33610628Sandreas.hansson@arm.comsystem.ruby.delayHist::samples 2750 # delay histogram for all message 33710628Sandreas.hansson@arm.comsystem.ruby.delayHist | 2750 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message 33810628Sandreas.hansson@arm.comsystem.ruby.delayHist::total 2750 # delay histogram for all message 33910628Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist::bucket_size 1 34010628Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist::max_bucket 9 34110628Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist::samples 8852 34210628Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist::mean 1 34310628Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist::gmean 1 34410628Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8852 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 34510628Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist::total 8852 34610628Sandreas.hansson@arm.comsystem.ruby.latency_hist::bucket_size 64 34710628Sandreas.hansson@arm.comsystem.ruby.latency_hist::max_bucket 639 34810628Sandreas.hansson@arm.comsystem.ruby.latency_hist::samples 8852 34910892Sandreas.hansson@arm.comsystem.ruby.latency_hist::mean 11.116584 35010892Sandreas.hansson@arm.comsystem.ruby.latency_hist::gmean 4.640695 35110892Sandreas.hansson@arm.comsystem.ruby.latency_hist::stdev 22.790037 35210892Sandreas.hansson@arm.comsystem.ruby.latency_hist | 8597 97.12% 97.12% | 214 2.42% 99.54% | 29 0.33% 99.86% | 4 0.05% 99.91% | 5 0.06% 99.97% | 3 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 35310628Sandreas.hansson@arm.comsystem.ruby.latency_hist::total 8852 35410628Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist::bucket_size 1 35510628Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist::max_bucket 9 35610628Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist::samples 7475 35710628Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist::mean 3 35810628Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist::gmean 3.000000 35910628Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7475 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 36010628Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist::total 7475 36110628Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist::bucket_size 64 36210628Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist::max_bucket 639 36310628Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist::samples 1377 36410892Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist::mean 55.177197 36510892Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist::gmean 49.553011 36610892Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist::stdev 32.253276 36710892Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist | 1122 81.48% 81.48% | 214 15.54% 97.02% | 29 2.11% 99.13% | 4 0.29% 99.42% | 5 0.36% 99.78% | 3 0.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 36810628Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist::total 1377 36910628Sandreas.hansson@arm.comsystem.ruby.Directory.incomplete_times 1376 37010628Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 # Number of cache demand hits 37110628Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.cacheMemory.demand_misses 1377 # Number of cache demand misses 37210628Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.cacheMemory.demand_accesses 8852 # Number of cache demand accesses 37310628Sandreas.hansson@arm.comsystem.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks 37410892Sandreas.hansson@arm.comsystem.ruby.network.routers0.percent_links_utilized 6.409898 37510628Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Control::2 1377 37610628Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Data::2 1373 37710628Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Response_Data::4 1377 37810628Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Writeback_Control::3 1373 37910628Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Control::2 11016 38010628Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Data::2 98856 38110628Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Response_Data::4 99144 38210628Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Writeback_Control::3 10984 38310892Sandreas.hansson@arm.comsystem.ruby.network.routers1.percent_links_utilized 6.409898 38410628Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Control::2 1377 38510628Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Data::2 1373 38610628Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Response_Data::4 1377 38710628Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Writeback_Control::3 1373 38810628Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Control::2 11016 38910628Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Data::2 98856 39010628Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Response_Data::4 99144 39110628Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Writeback_Control::3 10984 39210892Sandreas.hansson@arm.comsystem.ruby.network.routers2.percent_links_utilized 6.409898 39310628Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Control::2 1377 39410628Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Data::2 1373 39510628Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Response_Data::4 1377 39610628Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Writeback_Control::3 1373 39710628Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Control::2 11016 39810628Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Data::2 98856 39910628Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Response_Data::4 99144 40010628Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Writeback_Control::3 10984 40110628Sandreas.hansson@arm.comsystem.ruby.network.msg_count.Control 4131 40210628Sandreas.hansson@arm.comsystem.ruby.network.msg_count.Data 4119 40310628Sandreas.hansson@arm.comsystem.ruby.network.msg_count.Response_Data 4131 40410628Sandreas.hansson@arm.comsystem.ruby.network.msg_count.Writeback_Control 4119 40510628Sandreas.hansson@arm.comsystem.ruby.network.msg_byte.Control 33048 40610628Sandreas.hansson@arm.comsystem.ruby.network.msg_byte.Data 296568 40710628Sandreas.hansson@arm.comsystem.ruby.network.msg_byte.Response_Data 297432 40810628Sandreas.hansson@arm.comsystem.ruby.network.msg_byte.Writeback_Control 32952 40910892Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle0.link_utilization 6.417357 4109864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1377 4119864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1373 4129864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 99144 4139864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 10984 41410892Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.link_utilization 6.402439 4159864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Control::2 1377 4169864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Data::2 1373 4179864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Control::2 11016 4189864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Data::2 98856 41910892Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle0.link_utilization 6.402439 4209864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_count.Control::2 1377 4219864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_count.Data::2 1373 4229864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_bytes.Control::2 11016 4239864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_bytes.Data::2 98856 42410892Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.link_utilization 6.417357 4259864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1377 4269864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1373 4279864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 99144 4289864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 10984 42910892Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.link_utilization 6.417357 4309864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1377 4319864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1373 4329864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 99144 4339864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 10984 43410892Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle1.link_utilization 6.402439 4359864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_count.Control::2 1377 4369864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_count.Data::2 1373 4379864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_bytes.Control::2 11016 4389864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_bytes.Data::2 98856 43910013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 44010013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 44110013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::samples 1377 # delay histogram for vnet_1 44210013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1 | 1377 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 44310013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::total 1377 # delay histogram for vnet_1 44410013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 44510013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 44610013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::samples 1373 # delay histogram for vnet_2 44710013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2 | 1373 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 44810013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::total 1373 # delay histogram for vnet_2 44910892Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist::bucket_size 64 45010892Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist::max_bucket 639 45110013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::samples 1045 45210892Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist::mean 24.565550 45310892Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist::gmean 10.818925 45410892Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist::stdev 28.664875 45510892Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist | 965 92.34% 92.34% | 74 7.08% 99.43% | 4 0.38% 99.81% | 1 0.10% 99.90% | 0 0.00% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 45610013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::total 1045 45710013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::bucket_size 1 45810013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::max_bucket 9 45910013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::samples 546 46010013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::mean 3 46110013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::gmean 3.000000 46210013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 546 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 46310013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::total 546 46410892Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist::bucket_size 64 46510892Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist::max_bucket 639 46610013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::samples 499 46710892Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist::mean 48.162325 46810892Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist::gmean 44.026667 46910892Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist::stdev 25.587548 47010892Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist | 419 83.97% 83.97% | 74 14.83% 98.80% | 4 0.80% 99.60% | 1 0.20% 99.80% | 0 0.00% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 47110013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::total 499 47210526Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::bucket_size 64 47310526Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::max_bucket 639 47410013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::samples 935 47510892Sandreas.hansson@arm.comsystem.ruby.ST.latency_hist::mean 16.914439 47610892Sandreas.hansson@arm.comsystem.ruby.ST.latency_hist::gmean 6.394076 47710892Sandreas.hansson@arm.comsystem.ruby.ST.latency_hist::stdev 28.735394 47810892Sandreas.hansson@arm.comsystem.ruby.ST.latency_hist | 895 95.72% 95.72% | 33 3.53% 99.25% | 3 0.32% 99.57% | 2 0.21% 99.79% | 1 0.11% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 47910013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::total 935 48010013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::bucket_size 1 48110013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::max_bucket 9 48210013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::samples 681 48310013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::mean 3 48410013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::gmean 3.000000 48510013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 681 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 48610013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::total 681 48710526Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::bucket_size 64 48810526Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::max_bucket 639 48910013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::samples 254 49010892Sandreas.hansson@arm.comsystem.ruby.ST.miss_latency_hist::mean 54.220472 49110892Sandreas.hansson@arm.comsystem.ruby.ST.miss_latency_hist::gmean 48.633946 49210892Sandreas.hansson@arm.comsystem.ruby.ST.miss_latency_hist::stdev 33.614512 49310892Sandreas.hansson@arm.comsystem.ruby.ST.miss_latency_hist | 214 84.25% 84.25% | 33 12.99% 97.24% | 3 1.18% 98.43% | 2 0.79% 99.21% | 1 0.39% 99.61% | 1 0.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 49410013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::total 254 49510526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::bucket_size 64 49610526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::max_bucket 639 49710013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::samples 6864 49810892Sandreas.hansson@arm.comsystem.ruby.IFETCH.latency_hist::mean 8.284237 49910892Sandreas.hansson@arm.comsystem.ruby.IFETCH.latency_hist::gmean 3.905930 50010892Sandreas.hansson@arm.comsystem.ruby.IFETCH.latency_hist::stdev 19.803554 50110892Sandreas.hansson@arm.comsystem.ruby.IFETCH.latency_hist | 6729 98.03% 98.03% | 107 1.56% 99.59% | 22 0.32% 99.91% | 1 0.01% 99.93% | 4 0.06% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 50210013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::total 6864 50310013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::bucket_size 1 50410013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::max_bucket 9 50510013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::samples 6241 50610013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::mean 3 50710013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::gmean 3.000000 50810013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6241 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 50910013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::total 6241 51010526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::bucket_size 64 51110526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::max_bucket 639 51210013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::samples 623 51310892Sandreas.hansson@arm.comsystem.ruby.IFETCH.miss_latency_hist::mean 61.219904 51410892Sandreas.hansson@arm.comsystem.ruby.IFETCH.miss_latency_hist::gmean 54.926300 51510892Sandreas.hansson@arm.comsystem.ruby.IFETCH.miss_latency_hist::stdev 35.218812 51610892Sandreas.hansson@arm.comsystem.ruby.IFETCH.miss_latency_hist | 488 78.33% 78.33% | 107 17.17% 95.51% | 22 3.53% 99.04% | 1 0.16% 99.20% | 4 0.64% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 51710013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::total 623 51810526Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::bucket_size 4 51910526Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::max_bucket 39 52010013Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::samples 8 52110526Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::mean 6.875000 52210526Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::gmean 4.063647 52310526Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::stdev 10.960155 52410013Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist | 7 87.50% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 1 12.50% 100.00% | 0 0.00% 100.00% 52510013Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::total 8 52610013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::bucket_size 1 52710013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::max_bucket 9 52810013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::samples 7 52910013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::mean 3 53010013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::gmean 3.000000 53110013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 53210013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::total 7 53310526Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::bucket_size 4 53410526Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::max_bucket 39 53510013Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::samples 1 53610526Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::mean 34 53710526Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::gmean 34.000000 53810013Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::stdev nan 53910013Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% 54010013Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::total 1 54110526Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::bucket_size 64 54210526Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::max_bucket 639 54310013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::samples 1377 54410892Sandreas.hansson@arm.comsystem.ruby.Directory.miss_mach_latency_hist::mean 55.177197 54510892Sandreas.hansson@arm.comsystem.ruby.Directory.miss_mach_latency_hist::gmean 49.553011 54610892Sandreas.hansson@arm.comsystem.ruby.Directory.miss_mach_latency_hist::stdev 32.253276 54710892Sandreas.hansson@arm.comsystem.ruby.Directory.miss_mach_latency_hist | 1122 81.48% 81.48% | 214 15.54% 97.02% | 29 2.11% 99.13% | 4 0.29% 99.42% | 5 0.36% 99.78% | 3 0.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 54810013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::total 1377 54910013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 55010013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 55110013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 1 55210013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev nan 55310013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 55410013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 1 55510013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 1 55610013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 9 55710013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::samples 1 55810013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::stdev nan 55910013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 56010013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::total 1 56110013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 1 56210013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 9 56310013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 1 56410013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev nan 56510013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 56610013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::total 1 56710013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 8 56810013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 79 56910013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1 57010526Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 75 57110526Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 75.000000 57210013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan 57310526Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% 57410013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1 57510892Sandreas.hansson@arm.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64 57610892Sandreas.hansson@arm.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639 57710013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::samples 499 57810892Sandreas.hansson@arm.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist::mean 48.162325 57910892Sandreas.hansson@arm.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 44.026667 58010892Sandreas.hansson@arm.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 25.587548 58110892Sandreas.hansson@arm.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist | 419 83.97% 83.97% | 74 14.83% 98.80% | 4 0.80% 99.60% | 1 0.20% 99.80% | 0 0.00% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 58210013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::total 499 58310526Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 64 58410526Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 639 58510013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::samples 254 58610892Sandreas.hansson@arm.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist::mean 54.220472 58710892Sandreas.hansson@arm.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 48.633946 58810892Sandreas.hansson@arm.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 33.614512 58910892Sandreas.hansson@arm.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist | 214 84.25% 84.25% | 33 12.99% 97.24% | 3 1.18% 98.43% | 2 0.79% 99.21% | 1 0.39% 99.61% | 1 0.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 59010013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::total 254 59110526Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 59210526Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 59310013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 623 59410892Sandreas.hansson@arm.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 61.219904 59510892Sandreas.hansson@arm.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 54.926300 59610892Sandreas.hansson@arm.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 35.218812 59710892Sandreas.hansson@arm.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 488 78.33% 78.33% | 107 17.17% 95.51% | 22 3.53% 99.04% | 1 0.16% 99.20% | 4 0.64% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 59810013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 623 59910526Snilay@cs.wisc.edusystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::bucket_size 4 60010526Snilay@cs.wisc.edusystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::max_bucket 39 60110013Snilay@cs.wisc.edusystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::samples 1 60210526Snilay@cs.wisc.edusystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::mean 34 60310526Snilay@cs.wisc.edusystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::gmean 34.000000 60410013Snilay@cs.wisc.edusystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::stdev nan 60510013Snilay@cs.wisc.edusystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% 60610013Snilay@cs.wisc.edusystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::total 1 60710628Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.GETX 1377 0.00% 0.00% 60810628Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.PUTX 1373 0.00% 0.00% 60910628Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.Memory_Data 1377 0.00% 0.00% 61010628Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.Memory_Ack 1373 0.00% 0.00% 61110628Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.I.GETX 1377 0.00% 0.00% 61210628Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.M.PUTX 1373 0.00% 0.00% 61310628Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.IM.Memory_Data 1377 0.00% 0.00% 61410628Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.MI.Memory_Ack 1373 0.00% 0.00% 61510013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Load 1045 0.00% 0.00% 61610013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Ifetch 6864 0.00% 0.00% 61710013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Store 943 0.00% 0.00% 61810013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Data 1377 0.00% 0.00% 61910013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Replacement 1373 0.00% 0.00% 62010013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Writeback_Ack 1373 0.00% 0.00% 62110013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Load 499 0.00% 0.00% 62210013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Ifetch 623 0.00% 0.00% 62310013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Store 255 0.00% 0.00% 62410013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Load 546 0.00% 0.00% 62510013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Ifetch 6241 0.00% 0.00% 62610013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Store 688 0.00% 0.00% 62710013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Replacement 1373 0.00% 0.00% 62810013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.MI.Writeback_Ack 1373 0.00% 0.00% 62910013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IS.Data 1122 0.00% 0.00% 63010013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IM.Data 255 0.00% 0.00% 6316167SN/A 6326167SN/A---------- End Simulation Statistics ---------- 633