stats.txt revision 11106
15148SN/A 25148SN/A---------- Begin Simulation Statistics ---------- 36483SN/Asim_seconds 0.000006 # Number of seconds simulated 49583Snilay@cs.wisc.edusim_ticks 5615000 # Number of ticks simulated 59583Snilay@cs.wisc.edufinal_tick 5615000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68673SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710827Sandreas.hansson@arm.comhost_inst_rate 96804 # Simulator instruction rate (inst/s) 810827Sandreas.hansson@arm.comhost_op_rate 175298 # Simulator op (including micro ops) rate (op/s) 910827Sandreas.hansson@arm.comhost_tick_rate 100934348 # Simulator tick rate (ticks/s) 1010827Sandreas.hansson@arm.comhost_mem_usage 242164 # Number of bytes of host memory used 1110827Sandreas.hansson@arm.comhost_seconds 0.06 # Real time elapsed on the host 129150SAli.Saidi@ARM.comsim_insts 5381 # Number of instructions simulated 139583Snilay@cs.wisc.edusim_ops 9748 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 169150SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.inst 54912 # Number of bytes read from this memory 179583Snilay@cs.wisc.edusystem.physmem.bytes_read::cpu.data 7066 # Number of bytes read from this memory 189583Snilay@cs.wisc.edusystem.physmem.bytes_read::total 61978 # Number of bytes read from this memory 199150SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::cpu.inst 54912 # Number of instructions bytes read from this memory 209150SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::total 54912 # Number of instructions bytes read from this memory 219373Snilay@cs.wisc.edusystem.physmem.bytes_written::cpu.data 7112 # Number of bytes written to this memory 229373Snilay@cs.wisc.edusystem.physmem.bytes_written::total 7112 # Number of bytes written to this memory 239150SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.inst 6864 # Number of read requests responded to by this memory 249583Snilay@cs.wisc.edusystem.physmem.num_reads::cpu.data 1053 # Number of read requests responded to by this memory 259583Snilay@cs.wisc.edusystem.physmem.num_reads::total 7917 # Number of read requests responded to by this memory 269373Snilay@cs.wisc.edusystem.physmem.num_writes::cpu.data 935 # Number of write requests responded to by this memory 279373Snilay@cs.wisc.edusystem.physmem.num_writes::total 935 # Number of write requests responded to by this memory 289583Snilay@cs.wisc.edusystem.physmem.bw_read::cpu.inst 9779519145 # Total read bandwidth from this memory (bytes/s) 299583Snilay@cs.wisc.edusystem.physmem.bw_read::cpu.data 1258414960 # Total read bandwidth from this memory (bytes/s) 309583Snilay@cs.wisc.edusystem.physmem.bw_read::total 11037934105 # Total read bandwidth from this memory (bytes/s) 319583Snilay@cs.wisc.edusystem.physmem.bw_inst_read::cpu.inst 9779519145 # Instruction read bandwidth from this memory (bytes/s) 329583Snilay@cs.wisc.edusystem.physmem.bw_inst_read::total 9779519145 # Instruction read bandwidth from this memory (bytes/s) 339583Snilay@cs.wisc.edusystem.physmem.bw_write::cpu.data 1266607302 # Write bandwidth from this memory (bytes/s) 349583Snilay@cs.wisc.edusystem.physmem.bw_write::total 1266607302 # Write bandwidth from this memory (bytes/s) 359583Snilay@cs.wisc.edusystem.physmem.bw_total::cpu.inst 9779519145 # Total bandwidth to/from this memory (bytes/s) 369583Snilay@cs.wisc.edusystem.physmem.bw_total::cpu.data 2525022262 # Total bandwidth to/from this memory (bytes/s) 379583Snilay@cs.wisc.edusystem.physmem.bw_total::total 12304541407 # Total bandwidth to/from this memory (bytes/s) 3810036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 3910036SAli.Saidi@ARM.comsystem.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 408673SN/Asystem.cpu.workload.num_syscalls 11 # Number of system calls 419583Snilay@cs.wisc.edusystem.cpu.numCycles 11231 # number of cpu cycles simulated 428673SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 437935SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 449150SAli.Saidi@ARM.comsystem.cpu.committedInsts 5381 # Number of instructions committed 459583Snilay@cs.wisc.edusystem.cpu.committedOps 9748 # Number of ops (including micro ops) committed 469924Ssteve.reinhardt@amd.comsystem.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses 478673SN/Asystem.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 489702Snilay@cs.wisc.edusystem.cpu.num_func_calls 209 # number of times a function call or return occured 499150SAli.Saidi@ARM.comsystem.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls 509924Ssteve.reinhardt@amd.comsystem.cpu.num_int_insts 9654 # number of integer instructions 517935SN/Asystem.cpu.num_fp_insts 0 # number of float instructions 529924Ssteve.reinhardt@amd.comsystem.cpu.num_int_register_reads 18335 # number of times the integer registers were read 539924Ssteve.reinhardt@amd.comsystem.cpu.num_int_register_writes 7527 # number of times the integer registers were written 547935SN/Asystem.cpu.num_fp_register_reads 0 # number of times the floating registers were read 557935SN/Asystem.cpu.num_fp_register_writes 0 # number of times the floating registers were written 569924Ssteve.reinhardt@amd.comsystem.cpu.num_cc_register_reads 6487 # number of times the CC registers were read 579924Ssteve.reinhardt@amd.comsystem.cpu.num_cc_register_writes 3536 # number of times the CC registers were written 589583Snilay@cs.wisc.edusystem.cpu.num_mem_refs 1988 # number of memory refs 599583Snilay@cs.wisc.edusystem.cpu.num_load_insts 1053 # Number of load instructions 609373Snilay@cs.wisc.edusystem.cpu.num_store_insts 935 # Number of store instructions 6110488Snilay@cs.wisc.edusystem.cpu.num_idle_cycles 0.002000 # Number of idle cycles 6210488Snilay@cs.wisc.edusystem.cpu.num_busy_cycles 11230.998000 # Number of busy cycles 6310488Snilay@cs.wisc.edusystem.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 6410488Snilay@cs.wisc.edusystem.cpu.idle_fraction 0.000000 # Percentage of idle cycles 6510063Snilay@cs.wisc.edusystem.cpu.Branches 1208 # Number of branches fetched 6610220Sandreas.hansson@arm.comsystem.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction 6710220Sandreas.hansson@arm.comsystem.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction 6810220Sandreas.hansson@arm.comsystem.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction 6910220Sandreas.hansson@arm.comsystem.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction 7010220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction 7110220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction 7210220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction 7310220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction 7410220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction 7510220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction 7610220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction 7710220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction 7810220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction 7910220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction 8010220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction 8110220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction 8210220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction 8310220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction 8410220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction 8510220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction 8610220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction 8710220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction 8810220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction 8910220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction 9010220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction 9110220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction 9210220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction 9310220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction 9410220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction 9510220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction 9610220Sandreas.hansson@arm.comsystem.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction 9710220Sandreas.hansson@arm.comsystem.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction 9810220Sandreas.hansson@arm.comsystem.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 9910220Sandreas.hansson@arm.comsystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 10010220Sandreas.hansson@arm.comsystem.cpu.op_class::total 9748 # Class of executed instruction 10110827Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 7917 # Transaction distribution 10210827Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 7917 # Transaction distribution 10310827Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 935 # Transaction distribution 10410827Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 935 # Transaction distribution 10510827Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.icache_port::system.physmem.port 13728 # Packet count per connected master and slave (bytes) 10610827Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.icache_port::total 13728 # Packet count per connected master and slave (bytes) 10710827Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3976 # Packet count per connected master and slave (bytes) 10810827Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.dcache_port::total 3976 # Packet count per connected master and slave (bytes) 10910827Sandreas.hansson@arm.comsystem.membus.pkt_count::total 17704 # Packet count per connected master and slave (bytes) 11010827Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.icache_port::system.physmem.port 54912 # Cumulative packet size per connected master and slave (bytes) 11110827Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.icache_port::total 54912 # Cumulative packet size per connected master and slave (bytes) 11210827Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 14178 # Cumulative packet size per connected master and slave (bytes) 11310827Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.dcache_port::total 14178 # Cumulative packet size per connected master and slave (bytes) 11410827Sandreas.hansson@arm.comsystem.membus.pkt_size::total 69090 # Cumulative packet size per connected master and slave (bytes) 11510827Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 11610827Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 8852 # Request fanout histogram 11710827Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0.775418 # Request fanout histogram 11810827Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0.417330 # Request fanout histogram 11910827Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 12010827Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 1988 22.46% 22.46% # Request fanout histogram 12110827Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 6864 77.54% 100.00% # Request fanout histogram 12210827Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 12310827Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 12410827Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 12510827Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 8852 # Request fanout histogram 1265148SN/A 1275148SN/A---------- End Simulation Statistics ---------- 128