stats.txt revision 9449:56610ab73040
19241Sandreas.hansson@arm.com 29717Sandreas.hansson@arm.com---------- Begin Simulation Statistics ---------- 39241Sandreas.hansson@arm.comsim_seconds 0.000015 # Number of seconds simulated 49241Sandreas.hansson@arm.comsim_ticks 15014000 # Number of ticks simulated 59241Sandreas.hansson@arm.comfinal_tick 15014000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 69241Sandreas.hansson@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 79241Sandreas.hansson@arm.comhost_inst_rate 15963 # Simulator instruction rate (inst/s) 89241Sandreas.hansson@arm.comhost_op_rate 28915 # Simulator op (including micro ops) rate (op/s) 99241Sandreas.hansson@arm.comhost_tick_rate 44538984 # Simulator tick rate (ticks/s) 109241Sandreas.hansson@arm.comhost_mem_usage 232848 # Number of bytes of host memory used 119241Sandreas.hansson@arm.comhost_seconds 0.34 # Real time elapsed on the host 129241Sandreas.hansson@arm.comsim_insts 5380 # Number of instructions simulated 139241Sandreas.hansson@arm.comsim_ops 9746 # Number of ops (including micro ops) simulated 149241Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 19392 # Number of bytes read from this memory 159241Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory 169241Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 28736 # Number of bytes read from this memory 179241Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 19392 # Number of instructions bytes read from this memory 189241Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 19392 # Number of instructions bytes read from this memory 199241Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 303 # Number of read requests responded to by this memory 209241Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory 219241Sandreas.hansson@arm.comsystem.physmem.num_reads::total 449 # Number of read requests responded to by this memory 229241Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 1291594512 # Total read bandwidth from this memory (bytes/s) 239241Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 622352471 # Total read bandwidth from this memory (bytes/s) 249241Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1913946983 # Total read bandwidth from this memory (bytes/s) 259241Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 1291594512 # Instruction read bandwidth from this memory (bytes/s) 269241Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 1291594512 # Instruction read bandwidth from this memory (bytes/s) 279241Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 1291594512 # Total bandwidth to/from this memory (bytes/s) 289241Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 622352471 # Total bandwidth to/from this memory (bytes/s) 299241Sandreas.hansson@arm.comsystem.physmem.bw_total::total 1913946983 # Total bandwidth to/from this memory (bytes/s) 309241Sandreas.hansson@arm.comsystem.physmem.readReqs 450 # Total number of read requests seen 319241Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Total number of write requests seen 329241Sandreas.hansson@arm.comsystem.physmem.cpureqs 450 # Reqs generatd by CPU via cache - shady 339241Sandreas.hansson@arm.comsystem.physmem.bytesRead 28736 # Total number of bytes read from memory 349241Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to memory 359241Sandreas.hansson@arm.comsystem.physmem.bytesConsumedRd 28736 # bytesRead derated as per pkt->getSize() 369241Sandreas.hansson@arm.comsystem.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 379241Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 389241Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 399241Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::0 41 # Track reads on a per bank basis 409241Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::1 20 # Track reads on a per bank basis 419241Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::2 55 # Track reads on a per bank basis 429241Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::3 23 # Track reads on a per bank basis 439241Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::4 52 # Track reads on a per bank basis 449241Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::5 23 # Track reads on a per bank basis 459241Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::6 17 # Track reads on a per bank basis 469241Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::7 14 # Track reads on a per bank basis 479241Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::8 22 # Track reads on a per bank basis 489241Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::9 35 # Track reads on a per bank basis 499241Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::10 29 # Track reads on a per bank basis 509241Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::11 39 # Track reads on a per bank basis 519241Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::12 12 # Track reads on a per bank basis 529241Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::13 17 # Track reads on a per bank basis 539241Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::14 34 # Track reads on a per bank basis 549241Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::15 17 # Track reads on a per bank basis 559241Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 569241Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 579718Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 589720Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 599717Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 609719Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 619241Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 629719Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 639719Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 649719Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 659719Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 669241Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 679241Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 689241Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 699241Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 709241Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 719241Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 729241Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 739241Sandreas.hansson@arm.comsystem.physmem.totGap 14993500 # Total gap between requests 749241Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Categorize read packet sizes 759294Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Categorize read packet sizes 769294Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Categorize read packet sizes 779241Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Categorize read packet sizes 789241Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Categorize read packet sizes 799241Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Categorize read packet sizes 809241Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 450 # Categorize read packet sizes 819241Sandreas.hansson@arm.comsystem.physmem.readPktSize::7 0 # Categorize read packet sizes 829241Sandreas.hansson@arm.comsystem.physmem.readPktSize::8 0 # Categorize read packet sizes 839241Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # categorize write packet sizes 849241Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # categorize write packet sizes 859241Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # categorize write packet sizes 869241Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # categorize write packet sizes 879241Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # categorize write packet sizes 889241Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # categorize write packet sizes 899241Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # categorize write packet sizes 909241Sandreas.hansson@arm.comsystem.physmem.writePktSize::7 0 # categorize write packet sizes 919241Sandreas.hansson@arm.comsystem.physmem.writePktSize::8 0 # categorize write packet sizes 929524SAndreas.Sandberg@ARM.comsystem.physmem.neitherpktsize::0 0 # categorize neither packet sizes 939241Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::1 0 # categorize neither packet sizes 949241Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::2 0 # categorize neither packet sizes 959718Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::3 0 # categorize neither packet sizes 969718Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::4 0 # categorize neither packet sizes 979241Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::5 0 # categorize neither packet sizes 989717Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::6 0 # categorize neither packet sizes 999241Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::7 0 # categorize neither packet sizes 1009241Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::8 0 # categorize neither packet sizes 1019241Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 230 # What read queue length does an incoming req see 1029241Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 151 # What read queue length does an incoming req see 1039241Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see 1049241Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see 1059241Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 1069241Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 1079241Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1089241Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1099524SAndreas.Sandberg@ARM.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1109719Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1119720Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1129719Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1139241Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1149241Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1159241Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1169241Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1179241Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1189241Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1199241Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1209342SAndreas.Sandberg@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1219241Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1229719Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1239719Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1249719Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1259719Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1269719Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1279719Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1289719Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1299719Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1309719Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1319719Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1329241Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1339241Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 1349241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1359241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1369241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1379241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1389241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1399241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1409719Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1419241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1429719Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1439241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1449717Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1459241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1469241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1479241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1489719Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1499719Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1509719Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1519241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1529241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1539241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1549241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1559241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1569241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1579717Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1589717Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1599717Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1609717Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1619241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1629241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1639241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1649719Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1659719Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 1669719Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 1679719Sandreas.hansson@arm.comsystem.physmem.totQLat 1656450 # Total cycles spent in queuing delays 1689719Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 12024450 # Sum of mem lat for all requests 1699720Sandreas.hansson@arm.comsystem.physmem.totBusLat 1800000 # Total cycles spent in databus access 1709719Sandreas.hansson@arm.comsystem.physmem.totBankLat 8568000 # Total cycles spent in bank access 1719241Sandreas.hansson@arm.comsystem.physmem.avgQLat 3681.00 # Average queueing delay per request 1729241Sandreas.hansson@arm.comsystem.physmem.avgBankLat 19040.00 # Average bank access latency per request 1739241Sandreas.hansson@arm.comsystem.physmem.avgBusLat 4000.00 # Average bus latency per request 1749717Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 26721.00 # Average memory access latency 1759241Sandreas.hansson@arm.comsystem.physmem.avgRdBW 1913.95 # Average achieved read bandwidth in MB/s 1769717Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 1779717Sandreas.hansson@arm.comsystem.physmem.avgConsumedRdBW 1913.95 # Average consumed read bandwidth in MB/s 1789717Sandreas.hansson@arm.comsystem.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 1799717Sandreas.hansson@arm.comsystem.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 1809717Sandreas.hansson@arm.comsystem.physmem.busUtil 11.96 # Data bus utilization in percentage 1819719Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 0.80 # Average read queue length over time 1829719Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length over time 1839718Sandreas.hansson@arm.comsystem.physmem.readRowHits 352 # Number of row buffer hits during reads 1849719Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 1859719Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 78.22 # Row buffer hit rate for reads 1869719Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 1879719Sandreas.hansson@arm.comsystem.physmem.avgGap 33318.89 # Average gap between requests 1889719Sandreas.hansson@arm.comsystem.cpu.workload.num_syscalls 11 # Number of system calls 1899719Sandreas.hansson@arm.comsystem.cpu.numCycles 30029 # number of cpu cycles simulated 1909719Sandreas.hansson@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 1919719Sandreas.hansson@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 1929719Sandreas.hansson@arm.comsystem.cpu.BPredUnit.lookups 3018 # Number of BP lookups 1939719Sandreas.hansson@arm.comsystem.cpu.BPredUnit.condPredicted 3018 # Number of conditional branches predicted 1949719Sandreas.hansson@arm.comsystem.cpu.BPredUnit.condIncorrect 546 # Number of conditional branches incorrect 1959719Sandreas.hansson@arm.comsystem.cpu.BPredUnit.BTBLookups 2500 # Number of BTB lookups 1969719Sandreas.hansson@arm.comsystem.cpu.BPredUnit.BTBHits 796 # Number of BTB hits 1979720Sandreas.hansson@arm.comsystem.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1989719Sandreas.hansson@arm.comsystem.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 1999719Sandreas.hansson@arm.comsystem.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. 2009719Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 8963 # Number of cycles fetch is stalled on an Icache miss 2019717Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 14512 # Number of instructions fetch has processed 2029241Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 3018 # Number of branches that fetch encountered 2039241Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 796 # Number of branches that fetch has predicted taken 2049241Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 3937 # Number of cycles fetch has run and was not squashing or blocked 2059718Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 2417 # Number of cycles fetch has spent squashing 2069241Sandreas.hansson@arm.comsystem.cpu.fetch.BlockedCycles 3663 # Number of cycles fetch has spent blocked 2079241Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 2089241Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 144 # Number of stall cycles due to pending traps 2099241Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR 2109241Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 1881 # Number of cache lines fetched 2119241Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 288 # Number of outstanding Icache misses that were squashed 2129241Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 18583 # Number of instructions fetched each cycle (Total) 2139718Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 1.378787 # Number of instructions fetched each cycle (Total) 2149241Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 2.879591 # Number of instructions fetched each cycle (Total) 2159241Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 2169718Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 14745 79.35% 79.35% # Number of instructions fetched each cycle (Total) 2179241Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 189 1.02% 80.36% # Number of instructions fetched each cycle (Total) 2189241Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 157 0.84% 81.21% # Number of instructions fetched each cycle (Total) 2199241Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 193 1.04% 82.25% # Number of instructions fetched each cycle (Total) 2209241Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 162 0.87% 83.12% # Number of instructions fetched each cycle (Total) 2219241Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 171 0.92% 84.04% # Number of instructions fetched each cycle (Total) 2229241Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 265 1.43% 85.47% # Number of instructions fetched each cycle (Total) 2239241Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 161 0.87% 86.33% # Number of instructions fetched each cycle (Total) 2249241Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 2540 13.67% 100.00% # Number of instructions fetched each cycle (Total) 2259241Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 2269241Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 2279241Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 2289241Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 18583 # Number of instructions fetched each cycle (Total) 2299241Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.100503 # Number of branch fetches per cycle 2309241Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.483266 # Number of inst fetches per cycle 2319241Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 9455 # Number of cycles decode is idle 2329241Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 3616 # Number of cycles decode is blocked 2339241Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 3547 # Number of cycles decode is running 2349241Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking 2359241Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 1830 # Number of cycles decode is squashing 2369241Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 24452 # Number of instructions handled by decode 2379241Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 1830 # Number of cycles rename is squashing 2389241Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 9798 # Number of cycles rename is idle 2399241Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 2386 # Number of cycles rename is blocking 2409241Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 485 # count of cycles rename stalled for serializing inst 2419241Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 3325 # Number of cycles rename is running 2429241Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 759 # Number of cycles rename is unblocking 2439241Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 22970 # Number of instructions processed by rename 2449241Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full 2459241Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 39 # Number of times rename has blocked due to IQ full 2469241Sandreas.hansson@arm.comsystem.cpu.rename.LSQFullEvents 640 # Number of times rename has blocked due to LSQ full 2479718Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 25107 # Number of destination operands rename has renamed 2489241Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 55203 # Number of register rename lookups that rename has made 2499241Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 55187 # Number of integer rename lookups 2509241Sandreas.hansson@arm.comsystem.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups 2519718Sandreas.hansson@arm.comsystem.cpu.rename.CommittedMaps 11061 # Number of HB maps that are committed 2529241Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 14046 # Number of HB maps that are undone due to squashing 2539241Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 31 # count of serializing insts renamed 2549241Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 31 # count of temporary serializing insts renamed 2559241Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 2021 # count of insts added to the skid buffer 2569241Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 2205 # Number of loads inserted to the mem dependence unit. 2579241Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 1757 # Number of stores inserted to the mem dependence unit. 2589241Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. 2599241Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingStores 7 # Number of conflicting stores. 2609241Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 20458 # Number of instructions added to the IQ (excludes non-spec) 2619241Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 35 # Number of non-speculative instructions added to the IQ 2629241Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 17350 # Number of instructions issued 2639241Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 213 # Number of squashed instructions issued 2649241Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 9975 # Number of squashed instructions iterated over during squash; mainly for profiling 2659241Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 13877 # Number of squashed operands that are examined and possibly removed from graph 2669241Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 23 # Number of squashed non-spec instructions that were removed 2679241Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 18583 # Number of insts issued each cycle 2689241Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.933649 # Number of insts issued each cycle 2699241Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.794423 # Number of insts issued each cycle 2709718Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 2719718Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 13202 71.04% 71.04% # Number of insts issued each cycle 2729718Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 1385 7.45% 78.50% # Number of insts issued each cycle 2739718Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 1043 5.61% 84.11% # Number of insts issued each cycle 2749718Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 691 3.72% 87.83% # Number of insts issued each cycle 2759718Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 742 3.99% 91.82% # Number of insts issued each cycle 2769718Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 623 3.35% 95.17% # Number of insts issued each cycle 2779241Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 598 3.22% 98.39% # Number of insts issued each cycle 2789718Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 257 1.38% 99.77% # Number of insts issued each cycle 2799241Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 42 0.23% 100.00% # Number of insts issued each cycle 2809241Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 2819718Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 2829241Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 2839241Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 18583 # Number of insts issued each cycle 2849241Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 2859241Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 138 77.53% 77.53% # attempts to use FU when none available 2869241Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 77.53% # attempts to use FU when none available 2879241Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 77.53% # attempts to use FU when none available 2889718Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 77.53% # attempts to use FU when none available 2899241Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 77.53% # attempts to use FU when none available 2909241Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 77.53% # attempts to use FU when none available 2919241Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 77.53% # attempts to use FU when none available 2929241Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 77.53% # attempts to use FU when none available 2939241Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.53% # attempts to use FU when none available 2949241Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 77.53% # attempts to use FU when none available 2959241Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.53% # attempts to use FU when none available 2969241Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 77.53% # attempts to use FU when none available 2979241Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 77.53% # attempts to use FU when none available 2989241Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 77.53% # attempts to use FU when none available 2999241Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 77.53% # attempts to use FU when none available 3009241Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 77.53% # attempts to use FU when none available 3019241Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.53% # attempts to use FU when none available 3029241Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 77.53% # attempts to use FU when none available 3039241Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.53% # attempts to use FU when none available 3049241Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.53% # attempts to use FU when none available 3059241Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.53% # attempts to use FU when none available 3069241Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.53% # attempts to use FU when none available 3079241Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.53% # attempts to use FU when none available 3089241Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.53% # attempts to use FU when none available 3099241Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.53% # attempts to use FU when none available 3109241Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.53% # attempts to use FU when none available 3119241Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.53% # attempts to use FU when none available 3129241Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.53% # attempts to use FU when none available 3139241Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.53% # attempts to use FU when none available 3149241Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 19 10.67% 88.20% # attempts to use FU when none available 3159241Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 21 11.80% 100.00% # attempts to use FU when none available 3169241Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 3179241Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 3189721Ssascha.bischoff@arm.comsystem.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued 3199721Ssascha.bischoff@arm.comsystem.cpu.iq.FU_type_0::IntAlu 13964 80.48% 80.51% # Type of FU issued 3209721Ssascha.bischoff@arm.comsystem.cpu.iq.FU_type_0::IntMult 0 0.00% 80.51% # Type of FU issued 3219241Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.51% # Type of FU issued 3229241Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.51% # Type of FU issued 3239241Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.51% # Type of FU issued 3249241Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.51% # Type of FU issued 3259241Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.51% # Type of FU issued 3269241Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.51% # Type of FU issued 3279241Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.51% # Type of FU issued 3289241Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.51% # Type of FU issued 3299241Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.51% # Type of FU issued 3309721Ssascha.bischoff@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.51% # Type of FU issued 3319241Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.51% # Type of FU issued 3329721Ssascha.bischoff@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.51% # Type of FU issued 3339241Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.51% # Type of FU issued 3349241Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.51% # Type of FU issued 3359241Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.51% # Type of FU issued 3369241Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.51% # Type of FU issued 3379241Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.51% # Type of FU issued 3389241Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.51% # Type of FU issued 3399241Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.51% # Type of FU issued 3409241Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.51% # Type of FU issued 3419241Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.51% # Type of FU issued 3429241Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.51% # Type of FU issued 3439241Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.51% # Type of FU issued 3449241Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.51% # Type of FU issued 3459241Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.51% # Type of FU issued 3469241Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.51% # Type of FU issued 3479717Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.51% # Type of FU issued 3489241Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 1899 10.95% 91.45% # Type of FU issued 3499241Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 1483 8.55% 100.00% # Type of FU issued 3509241Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 3519241Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 3529241Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 17350 # Type of FU issued 3539241Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.577775 # Inst issue rate 3549241Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 178 # FU busy when requested 3559584Sandreas@sandberg.pp.sesystem.cpu.iq.fu_busy_rate 0.010259 # FU busy rate (busy events/executed inst) 3569584Sandreas@sandberg.pp.sesystem.cpu.iq.int_inst_queue_reads 53666 # Number of integer instruction queue reads 3579584Sandreas@sandberg.pp.sesystem.cpu.iq.int_inst_queue_writes 30475 # Number of integer instruction queue writes 3589241Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 16004 # Number of integer instruction queue wakeup accesses 3599241Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads 3609584Sandreas@sandberg.pp.sesystem.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes 3619584Sandreas@sandberg.pp.sesystem.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses 3629584Sandreas@sandberg.pp.sesystem.cpu.iq.int_alu_accesses 17520 # Number of integer alu accesses 3639241Sandreas.hansson@arm.comsystem.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses 3649241Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 158 # Number of loads that had data forwarded from stores 3659241Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 3669717Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1153 # Number of loads squashed 3679241Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 13 # Number of memory responses ignored because the instruction is squashed 3689241Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations 3699241Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 822 # Number of stores squashed 3709241Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 3719719Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 3729719Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 3739719Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 14 # Number of times an access to memory failed due to the cache being blocked 3749719Sandreas.hansson@arm.comsystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 3759241Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 1830 # Number of cycles IEW is squashing 3769241Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 1703 # Number of cycles IEW is blocking 3779241Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking 3789719Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 20493 # Number of instructions dispatched to IQ 3799719Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 33 # Number of squashed instructions skipped by dispatch 3809719Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 2205 # Number of dispatched load instructions 3819719Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 1757 # Number of dispatched store instructions 3829719Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions 3839719Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall 3849719Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 3859719Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations 3869719Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 56 # Number of branches that were predicted taken incorrectly 3879719Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 601 # Number of branches that were predicted not taken incorrectly 3889719Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 657 # Number of branch mispredicts detected at execute 3899719Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 16426 # Number of executed instructions 3909720Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 1777 # Number of load instructions executed 3919720Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 924 # Number of squashed instructions skipped in execute 3929719Sandreas.hansson@arm.comsystem.cpu.iew.exec_swp 0 # number of swp insts executed 3939719Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 0 # number of nop insts executed 3949719Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 3141 # number of memory reference insts executed 3959719Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 1630 # Number of branches executed 3969719Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 1364 # Number of stores executed 3979719Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.547005 # Inst execution rate 3989720Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 16198 # cumulative count of insts sent to commit 3999720Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 16008 # cumulative count of insts written-back 4009719Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 10179 # num instructions producing a value 4019719Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 15729 # num instructions consuming a value 4029719Sandreas.hansson@arm.comsystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 4039719Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.533085 # insts written-back per cycle 4049719Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.647149 # average fanout of values written-back 4059719Sandreas.hansson@arm.comsystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 4069719Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 10746 # The number of squashed insts skipped by commit 4079719Sandreas.hansson@arm.comsystem.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards 4089719Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 566 # The number of times a branch was mispredicted 4099719Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 16753 # Number of insts commited each cycle 4109719Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.581747 # Number of insts commited each cycle 4119719Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.458276 # Number of insts commited each cycle 4129719Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 4139719Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 13224 78.94% 78.94% # Number of insts commited each cycle 4149719Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 1319 7.87% 86.81% # Number of insts commited each cycle 4159719Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 595 3.55% 90.36% # Number of insts commited each cycle 4169719Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 710 4.24% 94.60% # Number of insts commited each cycle 4179719Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 351 2.10% 96.69% # Number of insts commited each cycle 4189719Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 138 0.82% 97.52% # Number of insts commited each cycle 4199719Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 120 0.72% 98.23% # Number of insts commited each cycle 4209719Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 75 0.45% 98.68% # Number of insts commited each cycle 4219719Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 221 1.32% 100.00% # Number of insts commited each cycle 4229719Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 4239719Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 4249719Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 4259719Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 16753 # Number of insts commited each cycle 4269719Sandreas.hansson@arm.comsystem.cpu.commit.committedInsts 5380 # Number of instructions committed 4279719Sandreas.hansson@arm.comsystem.cpu.commit.committedOps 9746 # Number of ops (including micro ops) committed 4289719Sandreas.hansson@arm.comsystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 4299719Sandreas.hansson@arm.comsystem.cpu.commit.refs 1987 # Number of memory references committed 4309719Sandreas.hansson@arm.comsystem.cpu.commit.loads 1052 # Number of loads committed 4319719Sandreas.hansson@arm.comsystem.cpu.commit.membars 0 # Number of memory barriers committed 4329241Sandreas.hansson@arm.comsystem.cpu.commit.branches 1208 # Number of branches committed 4339241Sandreas.hansson@arm.comsystem.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 4349241Sandreas.hansson@arm.comsystem.cpu.commit.int_insts 9652 # Number of committed integer instructions. 4359241Sandreas.hansson@arm.comsystem.cpu.commit.function_calls 0 # Number of function calls committed. 4369241Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 221 # number cycles where commit BW limit reached 4379241Sandreas.hansson@arm.comsystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 4389241Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 37024 # The number of ROB reads 4399241Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 42843 # The number of ROB writes 440system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself 441system.cpu.idleCycles 11446 # Total number of cycles that the CPU has spent unscheduled due to idling 442system.cpu.committedInsts 5380 # Number of Instructions Simulated 443system.cpu.committedOps 9746 # Number of Ops (including micro ops) Simulated 444system.cpu.committedInsts_total 5380 # Number of Instructions Simulated 445system.cpu.cpi 5.581599 # CPI: Cycles Per Instruction 446system.cpu.cpi_total 5.581599 # CPI: Total CPI of All Threads 447system.cpu.ipc 0.179160 # IPC: Instructions Per Cycle 448system.cpu.ipc_total 0.179160 # IPC: Total IPC of All Threads 449system.cpu.int_regfile_reads 28877 # number of integer regfile reads 450system.cpu.int_regfile_writes 17233 # number of integer regfile writes 451system.cpu.fp_regfile_reads 4 # number of floating regfile reads 452system.cpu.misc_regfile_reads 7157 # number of misc regfile reads 453system.cpu.icache.replacements 0 # number of replacements 454system.cpu.icache.tagsinuse 144.838495 # Cycle average of tags in use 455system.cpu.icache.total_refs 1482 # Total number of references to valid blocks. 456system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks. 457system.cpu.icache.avg_refs 4.875000 # Average number of references to valid blocks. 458system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 459system.cpu.icache.occ_blocks::cpu.inst 144.838495 # Average occupied blocks per requestor 460system.cpu.icache.occ_percent::cpu.inst 0.070722 # Average percentage of cache occupancy 461system.cpu.icache.occ_percent::total 0.070722 # Average percentage of cache occupancy 462system.cpu.icache.ReadReq_hits::cpu.inst 1482 # number of ReadReq hits 463system.cpu.icache.ReadReq_hits::total 1482 # number of ReadReq hits 464system.cpu.icache.demand_hits::cpu.inst 1482 # number of demand (read+write) hits 465system.cpu.icache.demand_hits::total 1482 # number of demand (read+write) hits 466system.cpu.icache.overall_hits::cpu.inst 1482 # number of overall hits 467system.cpu.icache.overall_hits::total 1482 # number of overall hits 468system.cpu.icache.ReadReq_misses::cpu.inst 399 # number of ReadReq misses 469system.cpu.icache.ReadReq_misses::total 399 # number of ReadReq misses 470system.cpu.icache.demand_misses::cpu.inst 399 # number of demand (read+write) misses 471system.cpu.icache.demand_misses::total 399 # number of demand (read+write) misses 472system.cpu.icache.overall_misses::cpu.inst 399 # number of overall misses 473system.cpu.icache.overall_misses::total 399 # number of overall misses 474system.cpu.icache.ReadReq_miss_latency::cpu.inst 19371000 # number of ReadReq miss cycles 475system.cpu.icache.ReadReq_miss_latency::total 19371000 # number of ReadReq miss cycles 476system.cpu.icache.demand_miss_latency::cpu.inst 19371000 # number of demand (read+write) miss cycles 477system.cpu.icache.demand_miss_latency::total 19371000 # number of demand (read+write) miss cycles 478system.cpu.icache.overall_miss_latency::cpu.inst 19371000 # number of overall miss cycles 479system.cpu.icache.overall_miss_latency::total 19371000 # number of overall miss cycles 480system.cpu.icache.ReadReq_accesses::cpu.inst 1881 # number of ReadReq accesses(hits+misses) 481system.cpu.icache.ReadReq_accesses::total 1881 # number of ReadReq accesses(hits+misses) 482system.cpu.icache.demand_accesses::cpu.inst 1881 # number of demand (read+write) accesses 483system.cpu.icache.demand_accesses::total 1881 # number of demand (read+write) accesses 484system.cpu.icache.overall_accesses::cpu.inst 1881 # number of overall (read+write) accesses 485system.cpu.icache.overall_accesses::total 1881 # number of overall (read+write) accesses 486system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.212121 # miss rate for ReadReq accesses 487system.cpu.icache.ReadReq_miss_rate::total 0.212121 # miss rate for ReadReq accesses 488system.cpu.icache.demand_miss_rate::cpu.inst 0.212121 # miss rate for demand accesses 489system.cpu.icache.demand_miss_rate::total 0.212121 # miss rate for demand accesses 490system.cpu.icache.overall_miss_rate::cpu.inst 0.212121 # miss rate for overall accesses 491system.cpu.icache.overall_miss_rate::total 0.212121 # miss rate for overall accesses 492system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48548.872180 # average ReadReq miss latency 493system.cpu.icache.ReadReq_avg_miss_latency::total 48548.872180 # average ReadReq miss latency 494system.cpu.icache.demand_avg_miss_latency::cpu.inst 48548.872180 # average overall miss latency 495system.cpu.icache.demand_avg_miss_latency::total 48548.872180 # average overall miss latency 496system.cpu.icache.overall_avg_miss_latency::cpu.inst 48548.872180 # average overall miss latency 497system.cpu.icache.overall_avg_miss_latency::total 48548.872180 # average overall miss latency 498system.cpu.icache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked 499system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 500system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked 501system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 502system.cpu.icache.avg_blocked_cycles::no_mshrs 44 # average number of cycles each access was blocked 503system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 504system.cpu.icache.fast_writes 0 # number of fast writes performed 505system.cpu.icache.cache_copies 0 # number of cache copies performed 506system.cpu.icache.ReadReq_mshr_hits::cpu.inst 95 # number of ReadReq MSHR hits 507system.cpu.icache.ReadReq_mshr_hits::total 95 # number of ReadReq MSHR hits 508system.cpu.icache.demand_mshr_hits::cpu.inst 95 # number of demand (read+write) MSHR hits 509system.cpu.icache.demand_mshr_hits::total 95 # number of demand (read+write) MSHR hits 510system.cpu.icache.overall_mshr_hits::cpu.inst 95 # number of overall MSHR hits 511system.cpu.icache.overall_mshr_hits::total 95 # number of overall MSHR hits 512system.cpu.icache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses 513system.cpu.icache.ReadReq_mshr_misses::total 304 # number of ReadReq MSHR misses 514system.cpu.icache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses 515system.cpu.icache.demand_mshr_misses::total 304 # number of demand (read+write) MSHR misses 516system.cpu.icache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses 517system.cpu.icache.overall_mshr_misses::total 304 # number of overall MSHR misses 518system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15461500 # number of ReadReq MSHR miss cycles 519system.cpu.icache.ReadReq_mshr_miss_latency::total 15461500 # number of ReadReq MSHR miss cycles 520system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15461500 # number of demand (read+write) MSHR miss cycles 521system.cpu.icache.demand_mshr_miss_latency::total 15461500 # number of demand (read+write) MSHR miss cycles 522system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15461500 # number of overall MSHR miss cycles 523system.cpu.icache.overall_mshr_miss_latency::total 15461500 # number of overall MSHR miss cycles 524system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.161616 # mshr miss rate for ReadReq accesses 525system.cpu.icache.ReadReq_mshr_miss_rate::total 0.161616 # mshr miss rate for ReadReq accesses 526system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.161616 # mshr miss rate for demand accesses 527system.cpu.icache.demand_mshr_miss_rate::total 0.161616 # mshr miss rate for demand accesses 528system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.161616 # mshr miss rate for overall accesses 529system.cpu.icache.overall_mshr_miss_rate::total 0.161616 # mshr miss rate for overall accesses 530system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50860.197368 # average ReadReq mshr miss latency 531system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50860.197368 # average ReadReq mshr miss latency 532system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50860.197368 # average overall mshr miss latency 533system.cpu.icache.demand_avg_mshr_miss_latency::total 50860.197368 # average overall mshr miss latency 534system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50860.197368 # average overall mshr miss latency 535system.cpu.icache.overall_avg_mshr_miss_latency::total 50860.197368 # average overall mshr miss latency 536system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 537system.cpu.l2cache.replacements 0 # number of replacements 538system.cpu.l2cache.tagsinuse 178.021458 # Cycle average of tags in use 539system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. 540system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. 541system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. 542system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 543system.cpu.l2cache.occ_blocks::cpu.inst 144.985394 # Average occupied blocks per requestor 544system.cpu.l2cache.occ_blocks::cpu.data 33.036064 # Average occupied blocks per requestor 545system.cpu.l2cache.occ_percent::cpu.inst 0.004425 # Average percentage of cache occupancy 546system.cpu.l2cache.occ_percent::cpu.data 0.001008 # Average percentage of cache occupancy 547system.cpu.l2cache.occ_percent::total 0.005433 # Average percentage of cache occupancy 548system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 549system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 550system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 551system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 552system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 553system.cpu.l2cache.overall_hits::total 1 # number of overall hits 554system.cpu.l2cache.ReadReq_misses::cpu.inst 303 # number of ReadReq misses 555system.cpu.l2cache.ReadReq_misses::cpu.data 71 # number of ReadReq misses 556system.cpu.l2cache.ReadReq_misses::total 374 # number of ReadReq misses 557system.cpu.l2cache.ReadExReq_misses::cpu.data 76 # number of ReadExReq misses 558system.cpu.l2cache.ReadExReq_misses::total 76 # number of ReadExReq misses 559system.cpu.l2cache.demand_misses::cpu.inst 303 # number of demand (read+write) misses 560system.cpu.l2cache.demand_misses::cpu.data 147 # number of demand (read+write) misses 561system.cpu.l2cache.demand_misses::total 450 # number of demand (read+write) misses 562system.cpu.l2cache.overall_misses::cpu.inst 303 # number of overall misses 563system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses 564system.cpu.l2cache.overall_misses::total 450 # number of overall misses 565system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15146500 # number of ReadReq miss cycles 566system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3811500 # number of ReadReq miss cycles 567system.cpu.l2cache.ReadReq_miss_latency::total 18958000 # number of ReadReq miss cycles 568system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3992500 # number of ReadExReq miss cycles 569system.cpu.l2cache.ReadExReq_miss_latency::total 3992500 # number of ReadExReq miss cycles 570system.cpu.l2cache.demand_miss_latency::cpu.inst 15146500 # number of demand (read+write) miss cycles 571system.cpu.l2cache.demand_miss_latency::cpu.data 7804000 # number of demand (read+write) miss cycles 572system.cpu.l2cache.demand_miss_latency::total 22950500 # number of demand (read+write) miss cycles 573system.cpu.l2cache.overall_miss_latency::cpu.inst 15146500 # number of overall miss cycles 574system.cpu.l2cache.overall_miss_latency::cpu.data 7804000 # number of overall miss cycles 575system.cpu.l2cache.overall_miss_latency::total 22950500 # number of overall miss cycles 576system.cpu.l2cache.ReadReq_accesses::cpu.inst 304 # number of ReadReq accesses(hits+misses) 577system.cpu.l2cache.ReadReq_accesses::cpu.data 71 # number of ReadReq accesses(hits+misses) 578system.cpu.l2cache.ReadReq_accesses::total 375 # number of ReadReq accesses(hits+misses) 579system.cpu.l2cache.ReadExReq_accesses::cpu.data 76 # number of ReadExReq accesses(hits+misses) 580system.cpu.l2cache.ReadExReq_accesses::total 76 # number of ReadExReq accesses(hits+misses) 581system.cpu.l2cache.demand_accesses::cpu.inst 304 # number of demand (read+write) accesses 582system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 583system.cpu.l2cache.demand_accesses::total 451 # number of demand (read+write) accesses 584system.cpu.l2cache.overall_accesses::cpu.inst 304 # number of overall (read+write) accesses 585system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 586system.cpu.l2cache.overall_accesses::total 451 # number of overall (read+write) accesses 587system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996711 # miss rate for ReadReq accesses 588system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 589system.cpu.l2cache.ReadReq_miss_rate::total 0.997333 # miss rate for ReadReq accesses 590system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 591system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 592system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996711 # miss rate for demand accesses 593system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 594system.cpu.l2cache.demand_miss_rate::total 0.997783 # miss rate for demand accesses 595system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996711 # miss rate for overall accesses 596system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 597system.cpu.l2cache.overall_miss_rate::total 0.997783 # miss rate for overall accesses 598system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49988.448845 # average ReadReq miss latency 599system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53683.098592 # average ReadReq miss latency 600system.cpu.l2cache.ReadReq_avg_miss_latency::total 50689.839572 # average ReadReq miss latency 601system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52532.894737 # average ReadExReq miss latency 602system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52532.894737 # average ReadExReq miss latency 603system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49988.448845 # average overall miss latency 604system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53088.435374 # average overall miss latency 605system.cpu.l2cache.demand_avg_miss_latency::total 51001.111111 # average overall miss latency 606system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49988.448845 # average overall miss latency 607system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53088.435374 # average overall miss latency 608system.cpu.l2cache.overall_avg_miss_latency::total 51001.111111 # average overall miss latency 609system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 610system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 611system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 612system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 613system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 614system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 615system.cpu.l2cache.fast_writes 0 # number of fast writes performed 616system.cpu.l2cache.cache_copies 0 # number of cache copies performed 617system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 303 # number of ReadReq MSHR misses 618system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 71 # number of ReadReq MSHR misses 619system.cpu.l2cache.ReadReq_mshr_misses::total 374 # number of ReadReq MSHR misses 620system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses 621system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses 622system.cpu.l2cache.demand_mshr_misses::cpu.inst 303 # number of demand (read+write) MSHR misses 623system.cpu.l2cache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 624system.cpu.l2cache.demand_mshr_misses::total 450 # number of demand (read+write) MSHR misses 625system.cpu.l2cache.overall_mshr_misses::cpu.inst 303 # number of overall MSHR misses 626system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 627system.cpu.l2cache.overall_mshr_misses::total 450 # number of overall MSHR misses 628system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11336952 # number of ReadReq MSHR miss cycles 629system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2944072 # number of ReadReq MSHR miss cycles 630system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14281024 # number of ReadReq MSHR miss cycles 631system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3029110 # number of ReadExReq MSHR miss cycles 632system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3029110 # number of ReadExReq MSHR miss cycles 633system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11336952 # number of demand (read+write) MSHR miss cycles 634system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5973182 # number of demand (read+write) MSHR miss cycles 635system.cpu.l2cache.demand_mshr_miss_latency::total 17310134 # number of demand (read+write) MSHR miss cycles 636system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11336952 # number of overall MSHR miss cycles 637system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5973182 # number of overall MSHR miss cycles 638system.cpu.l2cache.overall_mshr_miss_latency::total 17310134 # number of overall MSHR miss cycles 639system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for ReadReq accesses 640system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 641system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997333 # mshr miss rate for ReadReq accesses 642system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 643system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 644system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for demand accesses 645system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 646system.cpu.l2cache.demand_mshr_miss_rate::total 0.997783 # mshr miss rate for demand accesses 647system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for overall accesses 648system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 649system.cpu.l2cache.overall_mshr_miss_rate::total 0.997783 # mshr miss rate for overall accesses 650system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37415.683168 # average ReadReq mshr miss latency 651system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41465.802817 # average ReadReq mshr miss latency 652system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38184.556150 # average ReadReq mshr miss latency 653system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39856.710526 # average ReadExReq mshr miss latency 654system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39856.710526 # average ReadExReq mshr miss latency 655system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37415.683168 # average overall mshr miss latency 656system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40633.891156 # average overall mshr miss latency 657system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38466.964444 # average overall mshr miss latency 658system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37415.683168 # average overall mshr miss latency 659system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40633.891156 # average overall mshr miss latency 660system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38466.964444 # average overall mshr miss latency 661system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 662system.cpu.dcache.replacements 0 # number of replacements 663system.cpu.dcache.tagsinuse 83.281408 # Cycle average of tags in use 664system.cpu.dcache.total_refs 2284 # Total number of references to valid blocks. 665system.cpu.dcache.sampled_refs 144 # Sample count of references to valid blocks. 666system.cpu.dcache.avg_refs 15.861111 # Average number of references to valid blocks. 667system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 668system.cpu.dcache.occ_blocks::cpu.data 83.281408 # Average occupied blocks per requestor 669system.cpu.dcache.occ_percent::cpu.data 0.020332 # Average percentage of cache occupancy 670system.cpu.dcache.occ_percent::total 0.020332 # Average percentage of cache occupancy 671system.cpu.dcache.ReadReq_hits::cpu.data 1425 # number of ReadReq hits 672system.cpu.dcache.ReadReq_hits::total 1425 # number of ReadReq hits 673system.cpu.dcache.WriteReq_hits::cpu.data 859 # number of WriteReq hits 674system.cpu.dcache.WriteReq_hits::total 859 # number of WriteReq hits 675system.cpu.dcache.demand_hits::cpu.data 2284 # number of demand (read+write) hits 676system.cpu.dcache.demand_hits::total 2284 # number of demand (read+write) hits 677system.cpu.dcache.overall_hits::cpu.data 2284 # number of overall hits 678system.cpu.dcache.overall_hits::total 2284 # number of overall hits 679system.cpu.dcache.ReadReq_misses::cpu.data 126 # number of ReadReq misses 680system.cpu.dcache.ReadReq_misses::total 126 # number of ReadReq misses 681system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses 682system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses 683system.cpu.dcache.demand_misses::cpu.data 202 # number of demand (read+write) misses 684system.cpu.dcache.demand_misses::total 202 # number of demand (read+write) misses 685system.cpu.dcache.overall_misses::cpu.data 202 # number of overall misses 686system.cpu.dcache.overall_misses::total 202 # number of overall misses 687system.cpu.dcache.ReadReq_miss_latency::cpu.data 6336500 # number of ReadReq miss cycles 688system.cpu.dcache.ReadReq_miss_latency::total 6336500 # number of ReadReq miss cycles 689system.cpu.dcache.WriteReq_miss_latency::cpu.data 4220500 # number of WriteReq miss cycles 690system.cpu.dcache.WriteReq_miss_latency::total 4220500 # number of WriteReq miss cycles 691system.cpu.dcache.demand_miss_latency::cpu.data 10557000 # number of demand (read+write) miss cycles 692system.cpu.dcache.demand_miss_latency::total 10557000 # number of demand (read+write) miss cycles 693system.cpu.dcache.overall_miss_latency::cpu.data 10557000 # number of overall miss cycles 694system.cpu.dcache.overall_miss_latency::total 10557000 # number of overall miss cycles 695system.cpu.dcache.ReadReq_accesses::cpu.data 1551 # number of ReadReq accesses(hits+misses) 696system.cpu.dcache.ReadReq_accesses::total 1551 # number of ReadReq accesses(hits+misses) 697system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) 698system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) 699system.cpu.dcache.demand_accesses::cpu.data 2486 # number of demand (read+write) accesses 700system.cpu.dcache.demand_accesses::total 2486 # number of demand (read+write) accesses 701system.cpu.dcache.overall_accesses::cpu.data 2486 # number of overall (read+write) accesses 702system.cpu.dcache.overall_accesses::total 2486 # number of overall (read+write) accesses 703system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081238 # miss rate for ReadReq accesses 704system.cpu.dcache.ReadReq_miss_rate::total 0.081238 # miss rate for ReadReq accesses 705system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081283 # miss rate for WriteReq accesses 706system.cpu.dcache.WriteReq_miss_rate::total 0.081283 # miss rate for WriteReq accesses 707system.cpu.dcache.demand_miss_rate::cpu.data 0.081255 # miss rate for demand accesses 708system.cpu.dcache.demand_miss_rate::total 0.081255 # miss rate for demand accesses 709system.cpu.dcache.overall_miss_rate::cpu.data 0.081255 # miss rate for overall accesses 710system.cpu.dcache.overall_miss_rate::total 0.081255 # miss rate for overall accesses 711system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50289.682540 # average ReadReq miss latency 712system.cpu.dcache.ReadReq_avg_miss_latency::total 50289.682540 # average ReadReq miss latency 713system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55532.894737 # average WriteReq miss latency 714system.cpu.dcache.WriteReq_avg_miss_latency::total 55532.894737 # average WriteReq miss latency 715system.cpu.dcache.demand_avg_miss_latency::cpu.data 52262.376238 # average overall miss latency 716system.cpu.dcache.demand_avg_miss_latency::total 52262.376238 # average overall miss latency 717system.cpu.dcache.overall_avg_miss_latency::cpu.data 52262.376238 # average overall miss latency 718system.cpu.dcache.overall_avg_miss_latency::total 52262.376238 # average overall miss latency 719system.cpu.dcache.blocked_cycles::no_mshrs 132 # number of cycles access was blocked 720system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 721system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked 722system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 723system.cpu.dcache.avg_blocked_cycles::no_mshrs 22 # average number of cycles each access was blocked 724system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 725system.cpu.dcache.fast_writes 0 # number of fast writes performed 726system.cpu.dcache.cache_copies 0 # number of cache copies performed 727system.cpu.dcache.ReadReq_mshr_hits::cpu.data 55 # number of ReadReq MSHR hits 728system.cpu.dcache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits 729system.cpu.dcache.demand_mshr_hits::cpu.data 55 # number of demand (read+write) MSHR hits 730system.cpu.dcache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits 731system.cpu.dcache.overall_mshr_hits::cpu.data 55 # number of overall MSHR hits 732system.cpu.dcache.overall_mshr_hits::total 55 # number of overall MSHR hits 733system.cpu.dcache.ReadReq_mshr_misses::cpu.data 71 # number of ReadReq MSHR misses 734system.cpu.dcache.ReadReq_mshr_misses::total 71 # number of ReadReq MSHR misses 735system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses 736system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses 737system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 738system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 739system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 740system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 741system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3735500 # number of ReadReq MSHR miss cycles 742system.cpu.dcache.ReadReq_mshr_miss_latency::total 3735500 # number of ReadReq MSHR miss cycles 743system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4068500 # number of WriteReq MSHR miss cycles 744system.cpu.dcache.WriteReq_mshr_miss_latency::total 4068500 # number of WriteReq MSHR miss cycles 745system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7804000 # number of demand (read+write) MSHR miss cycles 746system.cpu.dcache.demand_mshr_miss_latency::total 7804000 # number of demand (read+write) MSHR miss cycles 747system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7804000 # number of overall MSHR miss cycles 748system.cpu.dcache.overall_mshr_miss_latency::total 7804000 # number of overall MSHR miss cycles 749system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045777 # mshr miss rate for ReadReq accesses 750system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045777 # mshr miss rate for ReadReq accesses 751system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081283 # mshr miss rate for WriteReq accesses 752system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081283 # mshr miss rate for WriteReq accesses 753system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for demand accesses 754system.cpu.dcache.demand_mshr_miss_rate::total 0.059131 # mshr miss rate for demand accesses 755system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for overall accesses 756system.cpu.dcache.overall_mshr_miss_rate::total 0.059131 # mshr miss rate for overall accesses 757system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52612.676056 # average ReadReq mshr miss latency 758system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52612.676056 # average ReadReq mshr miss latency 759system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53532.894737 # average WriteReq mshr miss latency 760system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53532.894737 # average WriteReq mshr miss latency 761system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53088.435374 # average overall mshr miss latency 762system.cpu.dcache.demand_avg_mshr_miss_latency::total 53088.435374 # average overall mshr miss latency 763system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53088.435374 # average overall mshr miss latency 764system.cpu.dcache.overall_avg_mshr_miss_latency::total 53088.435374 # average overall mshr miss latency 765system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 766 767---------- End Simulation Statistics ---------- 768