stats.txt revision 8802:ef66a9083bc4
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000011 # Number of seconds simulated 4sim_ticks 11087000 # Number of ticks simulated 5final_tick 11087000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 31087 # Simulator instruction rate (inst/s) 8host_tick_rate 35135175 # Simulator tick rate (ticks/s) 9host_mem_usage 212404 # Number of bytes of host memory used 10host_seconds 0.32 # Real time elapsed on the host 11sim_insts 9809 # Number of instructions simulated 12system.physmem.bytes_read 28288 # Number of bytes read from this memory 13system.physmem.bytes_inst_read 18944 # Number of instructions bytes read from this memory 14system.physmem.bytes_written 0 # Number of bytes written to this memory 15system.physmem.num_reads 442 # Number of read requests responded to by this memory 16system.physmem.num_writes 0 # Number of write requests responded to by this memory 17system.physmem.num_other 0 # Number of other requests responded to by this memory 18system.physmem.bw_read 2551456661 # Total read bandwidth from this memory (bytes/s) 19system.physmem.bw_inst_read 1708667809 # Instruction read bandwidth from this memory (bytes/s) 20system.physmem.bw_total 2551456661 # Total bandwidth to/from this memory (bytes/s) 21system.cpu.workload.num_syscalls 11 # Number of system calls 22system.cpu.numCycles 22175 # number of cpu cycles simulated 23system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 24system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 25system.cpu.BPredUnit.lookups 3056 # Number of BP lookups 26system.cpu.BPredUnit.condPredicted 3056 # Number of conditional branches predicted 27system.cpu.BPredUnit.condIncorrect 497 # Number of conditional branches incorrect 28system.cpu.BPredUnit.BTBLookups 2731 # Number of BTB lookups 29system.cpu.BPredUnit.BTBHits 995 # Number of BTB hits 30system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 31system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 32system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. 33system.cpu.fetch.icacheStallCycles 5895 # Number of cycles fetch is stalled on an Icache miss 34system.cpu.fetch.Insts 13997 # Number of instructions fetch has processed 35system.cpu.fetch.Branches 3056 # Number of branches that fetch encountered 36system.cpu.fetch.predictedBranches 995 # Number of branches that fetch has predicted taken 37system.cpu.fetch.Cycles 3968 # Number of cycles fetch has run and was not squashing or blocked 38system.cpu.fetch.SquashCycles 2221 # Number of cycles fetch has spent squashing 39system.cpu.fetch.BlockedCycles 1500 # Number of cycles fetch has spent blocked 40system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 41system.cpu.fetch.PendingTrapStallCycles 9 # Number of stall cycles due to pending traps 42system.cpu.fetch.CacheLines 1891 # Number of cache lines fetched 43system.cpu.fetch.IcacheSquashes 271 # Number of outstanding Icache misses that were squashed 44system.cpu.fetch.rateDist::samples 13088 # Number of instructions fetched each cycle (Total) 45system.cpu.fetch.rateDist::mean 1.930776 # Number of instructions fetched each cycle (Total) 46system.cpu.fetch.rateDist::stdev 3.218766 # Number of instructions fetched each cycle (Total) 47system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 48system.cpu.fetch.rateDist::0 9227 70.50% 70.50% # Number of instructions fetched each cycle (Total) 49system.cpu.fetch.rateDist::1 167 1.28% 71.78% # Number of instructions fetched each cycle (Total) 50system.cpu.fetch.rateDist::2 175 1.34% 73.11% # Number of instructions fetched each cycle (Total) 51system.cpu.fetch.rateDist::3 239 1.83% 74.94% # Number of instructions fetched each cycle (Total) 52system.cpu.fetch.rateDist::4 232 1.77% 76.71% # Number of instructions fetched each cycle (Total) 53system.cpu.fetch.rateDist::5 193 1.47% 78.19% # Number of instructions fetched each cycle (Total) 54system.cpu.fetch.rateDist::6 279 2.13% 80.32% # Number of instructions fetched each cycle (Total) 55system.cpu.fetch.rateDist::7 139 1.06% 81.38% # Number of instructions fetched each cycle (Total) 56system.cpu.fetch.rateDist::8 2437 18.62% 100.00% # Number of instructions fetched each cycle (Total) 57system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 58system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 59system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 60system.cpu.fetch.rateDist::total 13088 # Number of instructions fetched each cycle (Total) 61system.cpu.fetch.branchRate 0.137813 # Number of branch fetches per cycle 62system.cpu.fetch.rate 0.631206 # Number of inst fetches per cycle 63system.cpu.decode.IdleCycles 6247 # Number of cycles decode is idle 64system.cpu.decode.BlockedCycles 1453 # Number of cycles decode is blocked 65system.cpu.decode.RunCycles 3565 # Number of cycles decode is running 66system.cpu.decode.UnblockCycles 111 # Number of cycles decode is unblocking 67system.cpu.decode.SquashCycles 1712 # Number of cycles decode is squashing 68system.cpu.decode.DecodedInsts 24090 # Number of instructions handled by decode 69system.cpu.rename.SquashCycles 1712 # Number of cycles rename is squashing 70system.cpu.rename.IdleCycles 6535 # Number of cycles rename is idle 71system.cpu.rename.BlockCycles 523 # Number of cycles rename is blocking 72system.cpu.rename.serializeStallCycles 524 # count of cycles rename stalled for serializing inst 73system.cpu.rename.RunCycles 3365 # Number of cycles rename is running 74system.cpu.rename.UnblockCycles 429 # Number of cycles rename is unblocking 75system.cpu.rename.RenamedInsts 22712 # Number of instructions processed by rename 76system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full 77system.cpu.rename.IQFullEvents 68 # Number of times rename has blocked due to IQ full 78system.cpu.rename.LSQFullEvents 272 # Number of times rename has blocked due to LSQ full 79system.cpu.rename.RenamedOperands 21246 # Number of destination operands rename has renamed 80system.cpu.rename.RenameLookups 47645 # Number of register rename lookups that rename has made 81system.cpu.rename.int_rename_lookups 47629 # Number of integer rename lookups 82system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups 83system.cpu.rename.CommittedMaps 9368 # Number of HB maps that are committed 84system.cpu.rename.UndoneMaps 11878 # Number of HB maps that are undone due to squashing 85system.cpu.rename.serializingInsts 33 # count of serializing insts renamed 86system.cpu.rename.tempSerializingInsts 33 # count of temporary serializing insts renamed 87system.cpu.rename.skidInsts 1613 # count of insts added to the skid buffer 88system.cpu.memDep0.insertedLoads 2238 # Number of loads inserted to the mem dependence unit. 89system.cpu.memDep0.insertedStores 1782 # Number of stores inserted to the mem dependence unit. 90system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads. 91system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. 92system.cpu.iq.iqInstsAdded 20539 # Number of instructions added to the IQ (excludes non-spec) 93system.cpu.iq.iqNonSpecInstsAdded 37 # Number of non-speculative instructions added to the IQ 94system.cpu.iq.iqInstsIssued 16958 # Number of instructions issued 95system.cpu.iq.iqSquashedInstsIssued 63 # Number of squashed instructions issued 96system.cpu.iq.iqSquashedInstsExamined 10220 # Number of squashed instructions iterated over during squash; mainly for profiling 97system.cpu.iq.iqSquashedOperandsExamined 12992 # Number of squashed operands that are examined and possibly removed from graph 98system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed 99system.cpu.iq.issued_per_cycle::samples 13088 # Number of insts issued each cycle 100system.cpu.iq.issued_per_cycle::mean 1.295691 # Number of insts issued each cycle 101system.cpu.iq.issued_per_cycle::stdev 2.003315 # Number of insts issued each cycle 102system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 103system.cpu.iq.issued_per_cycle::0 8001 61.13% 61.13% # Number of insts issued each cycle 104system.cpu.iq.issued_per_cycle::1 1108 8.47% 69.60% # Number of insts issued each cycle 105system.cpu.iq.issued_per_cycle::2 1006 7.69% 77.28% # Number of insts issued each cycle 106system.cpu.iq.issued_per_cycle::3 733 5.60% 82.89% # Number of insts issued each cycle 107system.cpu.iq.issued_per_cycle::4 670 5.12% 88.00% # Number of insts issued each cycle 108system.cpu.iq.issued_per_cycle::5 725 5.54% 93.54% # Number of insts issued each cycle 109system.cpu.iq.issued_per_cycle::6 615 4.70% 98.24% # Number of insts issued each cycle 110system.cpu.iq.issued_per_cycle::7 196 1.50% 99.74% # Number of insts issued each cycle 111system.cpu.iq.issued_per_cycle::8 34 0.26% 100.00% # Number of insts issued each cycle 112system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 113system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 114system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 115system.cpu.iq.issued_per_cycle::total 13088 # Number of insts issued each cycle 116system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 117system.cpu.iq.fu_full::IntAlu 94 66.67% 66.67% # attempts to use FU when none available 118system.cpu.iq.fu_full::IntMult 0 0.00% 66.67% # attempts to use FU when none available 119system.cpu.iq.fu_full::IntDiv 0 0.00% 66.67% # attempts to use FU when none available 120system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.67% # attempts to use FU when none available 121system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.67% # attempts to use FU when none available 122system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.67% # attempts to use FU when none available 123system.cpu.iq.fu_full::FloatMult 0 0.00% 66.67% # attempts to use FU when none available 124system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.67% # attempts to use FU when none available 125system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.67% # attempts to use FU when none available 126system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.67% # attempts to use FU when none available 127system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.67% # attempts to use FU when none available 128system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.67% # attempts to use FU when none available 129system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.67% # attempts to use FU when none available 130system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.67% # attempts to use FU when none available 131system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.67% # attempts to use FU when none available 132system.cpu.iq.fu_full::SimdMult 0 0.00% 66.67% # attempts to use FU when none available 133system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.67% # attempts to use FU when none available 134system.cpu.iq.fu_full::SimdShift 0 0.00% 66.67% # attempts to use FU when none available 135system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.67% # attempts to use FU when none available 136system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.67% # attempts to use FU when none available 137system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.67% # attempts to use FU when none available 138system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.67% # attempts to use FU when none available 139system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.67% # attempts to use FU when none available 140system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.67% # attempts to use FU when none available 141system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.67% # attempts to use FU when none available 142system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.67% # attempts to use FU when none available 143system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.67% # attempts to use FU when none available 144system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.67% # attempts to use FU when none available 145system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.67% # attempts to use FU when none available 146system.cpu.iq.fu_full::MemRead 24 17.02% 83.69% # attempts to use FU when none available 147system.cpu.iq.fu_full::MemWrite 23 16.31% 100.00% # attempts to use FU when none available 148system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 149system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 150system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued 151system.cpu.iq.FU_type_0::IntAlu 13641 80.44% 80.46% # Type of FU issued 152system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.46% # Type of FU issued 153system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.46% # Type of FU issued 154system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.46% # Type of FU issued 155system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.46% # Type of FU issued 156system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.46% # Type of FU issued 157system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.46% # Type of FU issued 158system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.46% # Type of FU issued 159system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.46% # Type of FU issued 160system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.46% # Type of FU issued 161system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.46% # Type of FU issued 162system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.46% # Type of FU issued 163system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.46% # Type of FU issued 164system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.46% # Type of FU issued 165system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.46% # Type of FU issued 166system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.46% # Type of FU issued 167system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.46% # Type of FU issued 168system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.46% # Type of FU issued 169system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.46% # Type of FU issued 170system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.46% # Type of FU issued 171system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.46% # Type of FU issued 172system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.46% # Type of FU issued 173system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.46% # Type of FU issued 174system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.46% # Type of FU issued 175system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.46% # Type of FU issued 176system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.46% # Type of FU issued 177system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.46% # Type of FU issued 178system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.46% # Type of FU issued 179system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.46% # Type of FU issued 180system.cpu.iq.FU_type_0::MemRead 1843 10.87% 91.33% # Type of FU issued 181system.cpu.iq.FU_type_0::MemWrite 1470 8.67% 100.00% # Type of FU issued 182system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 183system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 184system.cpu.iq.FU_type_0::total 16958 # Type of FU issued 185system.cpu.iq.rate 0.764735 # Inst issue rate 186system.cpu.iq.fu_busy_cnt 141 # FU busy when requested 187system.cpu.iq.fu_busy_rate 0.008315 # FU busy rate (busy events/executed inst) 188system.cpu.iq.int_inst_queue_reads 47200 # Number of integer instruction queue reads 189system.cpu.iq.int_inst_queue_writes 30804 # Number of integer instruction queue writes 190system.cpu.iq.int_inst_queue_wakeup_accesses 15755 # Number of integer instruction queue wakeup accesses 191system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads 192system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes 193system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses 194system.cpu.iq.int_alu_accesses 17091 # Number of integer alu accesses 195system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses 196system.cpu.iew.lsq.thread0.forwLoads 80 # Number of loads that had data forwarded from stores 197system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 198system.cpu.iew.lsq.thread0.squashedLoads 1182 # Number of loads squashed 199system.cpu.iew.lsq.thread0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed 200system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations 201system.cpu.iew.lsq.thread0.squashedStores 848 # Number of stores squashed 202system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 203system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 204system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 205system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 206system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 207system.cpu.iew.iewSquashCycles 1712 # Number of cycles IEW is squashing 208system.cpu.iew.iewBlockCycles 144 # Number of cycles IEW is blocking 209system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking 210system.cpu.iew.iewDispatchedInsts 20576 # Number of instructions dispatched to IQ 211system.cpu.iew.iewDispSquashedInsts 23 # Number of squashed instructions skipped by dispatch 212system.cpu.iew.iewDispLoadInsts 2238 # Number of dispatched load instructions 213system.cpu.iew.iewDispStoreInsts 1782 # Number of dispatched store instructions 214system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions 215system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall 216system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 217system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations 218system.cpu.iew.predictedTakenIncorrect 65 # Number of branches that were predicted taken incorrectly 219system.cpu.iew.predictedNotTakenIncorrect 523 # Number of branches that were predicted not taken incorrectly 220system.cpu.iew.branchMispredicts 588 # Number of branch mispredicts detected at execute 221system.cpu.iew.iewExecutedInsts 16100 # Number of executed instructions 222system.cpu.iew.iewExecLoadInsts 1742 # Number of load instructions executed 223system.cpu.iew.iewExecSquashedInsts 858 # Number of squashed instructions skipped in execute 224system.cpu.iew.exec_swp 0 # number of swp insts executed 225system.cpu.iew.exec_nop 0 # number of nop insts executed 226system.cpu.iew.exec_refs 3105 # number of memory reference insts executed 227system.cpu.iew.exec_branches 1601 # Number of branches executed 228system.cpu.iew.exec_stores 1363 # Number of stores executed 229system.cpu.iew.exec_rate 0.726043 # Inst execution rate 230system.cpu.iew.wb_sent 15918 # cumulative count of insts sent to commit 231system.cpu.iew.wb_count 15759 # cumulative count of insts written-back 232system.cpu.iew.wb_producers 10538 # num instructions producing a value 233system.cpu.iew.wb_consumers 15699 # num instructions consuming a value 234system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 235system.cpu.iew.wb_rate 0.710665 # insts written-back per cycle 236system.cpu.iew.wb_fanout 0.671253 # average fanout of values written-back 237system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 238system.cpu.commit.commitCommittedInsts 9809 # The number of committed instructions 239system.cpu.commit.commitSquashedInsts 10766 # The number of squashed insts skipped by commit 240system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards 241system.cpu.commit.branchMispredicts 497 # The number of times a branch was mispredicted 242system.cpu.commit.committed_per_cycle::samples 11376 # Number of insts commited each cycle 243system.cpu.commit.committed_per_cycle::mean 0.862254 # Number of insts commited each cycle 244system.cpu.commit.committed_per_cycle::stdev 1.686850 # Number of insts commited each cycle 245system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 246system.cpu.commit.committed_per_cycle::0 7944 69.83% 69.83% # Number of insts commited each cycle 247system.cpu.commit.committed_per_cycle::1 1088 9.56% 79.40% # Number of insts commited each cycle 248system.cpu.commit.committed_per_cycle::2 574 5.05% 84.44% # Number of insts commited each cycle 249system.cpu.commit.committed_per_cycle::3 883 7.76% 92.20% # Number of insts commited each cycle 250system.cpu.commit.committed_per_cycle::4 343 3.02% 95.22% # Number of insts commited each cycle 251system.cpu.commit.committed_per_cycle::5 152 1.34% 96.55% # Number of insts commited each cycle 252system.cpu.commit.committed_per_cycle::6 139 1.22% 97.78% # Number of insts commited each cycle 253system.cpu.commit.committed_per_cycle::7 66 0.58% 98.36% # Number of insts commited each cycle 254system.cpu.commit.committed_per_cycle::8 187 1.64% 100.00% # Number of insts commited each cycle 255system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 256system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 257system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 258system.cpu.commit.committed_per_cycle::total 11376 # Number of insts commited each cycle 259system.cpu.commit.count 9809 # Number of instructions committed 260system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 261system.cpu.commit.refs 1990 # Number of memory references committed 262system.cpu.commit.loads 1056 # Number of loads committed 263system.cpu.commit.membars 0 # Number of memory barriers committed 264system.cpu.commit.branches 1214 # Number of branches committed 265system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 266system.cpu.commit.int_insts 9714 # Number of committed integer instructions. 267system.cpu.commit.function_calls 0 # Number of function calls committed. 268system.cpu.commit.bw_lim_events 187 # number cycles where commit BW limit reached 269system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 270system.cpu.rob.rob_reads 31764 # The number of ROB reads 271system.cpu.rob.rob_writes 42896 # The number of ROB writes 272system.cpu.timesIdled 182 # Number of times that the entire CPU went into an idle state and unscheduled itself 273system.cpu.idleCycles 9087 # Total number of cycles that the CPU has spent unscheduled due to idling 274system.cpu.committedInsts 9809 # Number of Instructions Simulated 275system.cpu.committedInsts_total 9809 # Number of Instructions Simulated 276system.cpu.cpi 2.260679 # CPI: Cycles Per Instruction 277system.cpu.cpi_total 2.260679 # CPI: Total CPI of All Threads 278system.cpu.ipc 0.442345 # IPC: Instructions Per Cycle 279system.cpu.ipc_total 0.442345 # IPC: Total IPC of All Threads 280system.cpu.int_regfile_reads 23665 # number of integer regfile reads 281system.cpu.int_regfile_writes 14645 # number of integer regfile writes 282system.cpu.fp_regfile_reads 4 # number of floating regfile reads 283system.cpu.misc_regfile_reads 7211 # number of misc regfile reads 284system.cpu.icache.replacements 0 # number of replacements 285system.cpu.icache.tagsinuse 145.144237 # Cycle average of tags in use 286system.cpu.icache.total_refs 1527 # Total number of references to valid blocks. 287system.cpu.icache.sampled_refs 298 # Sample count of references to valid blocks. 288system.cpu.icache.avg_refs 5.124161 # Average number of references to valid blocks. 289system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 290system.cpu.icache.occ_blocks::0 145.144237 # Average occupied blocks per context 291system.cpu.icache.occ_percent::0 0.070871 # Average percentage of cache occupancy 292system.cpu.icache.ReadReq_hits 1527 # number of ReadReq hits 293system.cpu.icache.demand_hits 1527 # number of demand (read+write) hits 294system.cpu.icache.overall_hits 1527 # number of overall hits 295system.cpu.icache.ReadReq_misses 364 # number of ReadReq misses 296system.cpu.icache.demand_misses 364 # number of demand (read+write) misses 297system.cpu.icache.overall_misses 364 # number of overall misses 298system.cpu.icache.ReadReq_miss_latency 13314500 # number of ReadReq miss cycles 299system.cpu.icache.demand_miss_latency 13314500 # number of demand (read+write) miss cycles 300system.cpu.icache.overall_miss_latency 13314500 # number of overall miss cycles 301system.cpu.icache.ReadReq_accesses 1891 # number of ReadReq accesses(hits+misses) 302system.cpu.icache.demand_accesses 1891 # number of demand (read+write) accesses 303system.cpu.icache.overall_accesses 1891 # number of overall (read+write) accesses 304system.cpu.icache.ReadReq_miss_rate 0.192491 # miss rate for ReadReq accesses 305system.cpu.icache.demand_miss_rate 0.192491 # miss rate for demand accesses 306system.cpu.icache.overall_miss_rate 0.192491 # miss rate for overall accesses 307system.cpu.icache.ReadReq_avg_miss_latency 36578.296703 # average ReadReq miss latency 308system.cpu.icache.demand_avg_miss_latency 36578.296703 # average overall miss latency 309system.cpu.icache.overall_avg_miss_latency 36578.296703 # average overall miss latency 310system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 311system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 312system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 313system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 314system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 315system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 316system.cpu.icache.fast_writes 0 # number of fast writes performed 317system.cpu.icache.cache_copies 0 # number of cache copies performed 318system.cpu.icache.writebacks 0 # number of writebacks 319system.cpu.icache.ReadReq_mshr_hits 66 # number of ReadReq MSHR hits 320system.cpu.icache.demand_mshr_hits 66 # number of demand (read+write) MSHR hits 321system.cpu.icache.overall_mshr_hits 66 # number of overall MSHR hits 322system.cpu.icache.ReadReq_mshr_misses 298 # number of ReadReq MSHR misses 323system.cpu.icache.demand_mshr_misses 298 # number of demand (read+write) MSHR misses 324system.cpu.icache.overall_mshr_misses 298 # number of overall MSHR misses 325system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 326system.cpu.icache.ReadReq_mshr_miss_latency 10466500 # number of ReadReq MSHR miss cycles 327system.cpu.icache.demand_mshr_miss_latency 10466500 # number of demand (read+write) MSHR miss cycles 328system.cpu.icache.overall_mshr_miss_latency 10466500 # number of overall MSHR miss cycles 329system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 330system.cpu.icache.ReadReq_mshr_miss_rate 0.157589 # mshr miss rate for ReadReq accesses 331system.cpu.icache.demand_mshr_miss_rate 0.157589 # mshr miss rate for demand accesses 332system.cpu.icache.overall_mshr_miss_rate 0.157589 # mshr miss rate for overall accesses 333system.cpu.icache.ReadReq_avg_mshr_miss_latency 35122.483221 # average ReadReq mshr miss latency 334system.cpu.icache.demand_avg_mshr_miss_latency 35122.483221 # average overall mshr miss latency 335system.cpu.icache.overall_avg_mshr_miss_latency 35122.483221 # average overall mshr miss latency 336system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 337system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 338system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 339system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 340system.cpu.dcache.replacements 0 # number of replacements 341system.cpu.dcache.tagsinuse 85.499149 # Cycle average of tags in use 342system.cpu.dcache.total_refs 2112 # Total number of references to valid blocks. 343system.cpu.dcache.sampled_refs 145 # Sample count of references to valid blocks. 344system.cpu.dcache.avg_refs 14.565517 # Average number of references to valid blocks. 345system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 346system.cpu.dcache.occ_blocks::0 85.499149 # Average occupied blocks per context 347system.cpu.dcache.occ_percent::0 0.020874 # Average percentage of cache occupancy 348system.cpu.dcache.ReadReq_hits 1494 # number of ReadReq hits 349system.cpu.dcache.WriteReq_hits 618 # number of WriteReq hits 350system.cpu.dcache.demand_hits 2112 # number of demand (read+write) hits 351system.cpu.dcache.overall_hits 2112 # number of overall hits 352system.cpu.dcache.ReadReq_misses 113 # number of ReadReq misses 353system.cpu.dcache.WriteReq_misses 316 # number of WriteReq misses 354system.cpu.dcache.demand_misses 429 # number of demand (read+write) misses 355system.cpu.dcache.overall_misses 429 # number of overall misses 356system.cpu.dcache.ReadReq_miss_latency 3938500 # number of ReadReq miss cycles 357system.cpu.dcache.WriteReq_miss_latency 10708500 # number of WriteReq miss cycles 358system.cpu.dcache.demand_miss_latency 14647000 # number of demand (read+write) miss cycles 359system.cpu.dcache.overall_miss_latency 14647000 # number of overall miss cycles 360system.cpu.dcache.ReadReq_accesses 1607 # number of ReadReq accesses(hits+misses) 361system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses) 362system.cpu.dcache.demand_accesses 2541 # number of demand (read+write) accesses 363system.cpu.dcache.overall_accesses 2541 # number of overall (read+write) accesses 364system.cpu.dcache.ReadReq_miss_rate 0.070317 # miss rate for ReadReq accesses 365system.cpu.dcache.WriteReq_miss_rate 0.338330 # miss rate for WriteReq accesses 366system.cpu.dcache.demand_miss_rate 0.168831 # miss rate for demand accesses 367system.cpu.dcache.overall_miss_rate 0.168831 # miss rate for overall accesses 368system.cpu.dcache.ReadReq_avg_miss_latency 34853.982301 # average ReadReq miss latency 369system.cpu.dcache.WriteReq_avg_miss_latency 33887.658228 # average WriteReq miss latency 370system.cpu.dcache.demand_avg_miss_latency 34142.191142 # average overall miss latency 371system.cpu.dcache.overall_avg_miss_latency 34142.191142 # average overall miss latency 372system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 373system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 374system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 375system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 376system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 377system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 378system.cpu.dcache.fast_writes 0 # number of fast writes performed 379system.cpu.dcache.cache_copies 0 # number of cache copies performed 380system.cpu.dcache.writebacks 0 # number of writebacks 381system.cpu.dcache.ReadReq_mshr_hits 44 # number of ReadReq MSHR hits 382system.cpu.dcache.WriteReq_mshr_hits 239 # number of WriteReq MSHR hits 383system.cpu.dcache.demand_mshr_hits 283 # number of demand (read+write) MSHR hits 384system.cpu.dcache.overall_mshr_hits 283 # number of overall MSHR hits 385system.cpu.dcache.ReadReq_mshr_misses 69 # number of ReadReq MSHR misses 386system.cpu.dcache.WriteReq_mshr_misses 77 # number of WriteReq MSHR misses 387system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses 388system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses 389system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 390system.cpu.dcache.ReadReq_mshr_miss_latency 2422500 # number of ReadReq MSHR miss cycles 391system.cpu.dcache.WriteReq_mshr_miss_latency 2761000 # number of WriteReq MSHR miss cycles 392system.cpu.dcache.demand_mshr_miss_latency 5183500 # number of demand (read+write) MSHR miss cycles 393system.cpu.dcache.overall_mshr_miss_latency 5183500 # number of overall MSHR miss cycles 394system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 395system.cpu.dcache.ReadReq_mshr_miss_rate 0.042937 # mshr miss rate for ReadReq accesses 396system.cpu.dcache.WriteReq_mshr_miss_rate 0.082441 # mshr miss rate for WriteReq accesses 397system.cpu.dcache.demand_mshr_miss_rate 0.057458 # mshr miss rate for demand accesses 398system.cpu.dcache.overall_mshr_miss_rate 0.057458 # mshr miss rate for overall accesses 399system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35108.695652 # average ReadReq mshr miss latency 400system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35857.142857 # average WriteReq mshr miss latency 401system.cpu.dcache.demand_avg_mshr_miss_latency 35503.424658 # average overall mshr miss latency 402system.cpu.dcache.overall_avg_mshr_miss_latency 35503.424658 # average overall mshr miss latency 403system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 404system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 405system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 406system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 407system.cpu.l2cache.replacements 0 # number of replacements 408system.cpu.l2cache.tagsinuse 178.614114 # Cycle average of tags in use 409system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. 410system.cpu.l2cache.sampled_refs 364 # Sample count of references to valid blocks. 411system.cpu.l2cache.avg_refs 0.005495 # Average number of references to valid blocks. 412system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 413system.cpu.l2cache.occ_blocks::0 178.614114 # Average occupied blocks per context 414system.cpu.l2cache.occ_percent::0 0.005451 # Average percentage of cache occupancy 415system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits 416system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits 417system.cpu.l2cache.overall_hits 2 # number of overall hits 418system.cpu.l2cache.ReadReq_misses 365 # number of ReadReq misses 419system.cpu.l2cache.ReadExReq_misses 77 # number of ReadExReq misses 420system.cpu.l2cache.demand_misses 442 # number of demand (read+write) misses 421system.cpu.l2cache.overall_misses 442 # number of overall misses 422system.cpu.l2cache.ReadReq_miss_latency 12494500 # number of ReadReq miss cycles 423system.cpu.l2cache.ReadExReq_miss_latency 2654000 # number of ReadExReq miss cycles 424system.cpu.l2cache.demand_miss_latency 15148500 # number of demand (read+write) miss cycles 425system.cpu.l2cache.overall_miss_latency 15148500 # number of overall miss cycles 426system.cpu.l2cache.ReadReq_accesses 367 # number of ReadReq accesses(hits+misses) 427system.cpu.l2cache.ReadExReq_accesses 77 # number of ReadExReq accesses(hits+misses) 428system.cpu.l2cache.demand_accesses 444 # number of demand (read+write) accesses 429system.cpu.l2cache.overall_accesses 444 # number of overall (read+write) accesses 430system.cpu.l2cache.ReadReq_miss_rate 0.994550 # miss rate for ReadReq accesses 431system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses 432system.cpu.l2cache.demand_miss_rate 0.995495 # miss rate for demand accesses 433system.cpu.l2cache.overall_miss_rate 0.995495 # miss rate for overall accesses 434system.cpu.l2cache.ReadReq_avg_miss_latency 34231.506849 # average ReadReq miss latency 435system.cpu.l2cache.ReadExReq_avg_miss_latency 34467.532468 # average ReadExReq miss latency 436system.cpu.l2cache.demand_avg_miss_latency 34272.624434 # average overall miss latency 437system.cpu.l2cache.overall_avg_miss_latency 34272.624434 # average overall miss latency 438system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 439system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 440system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 441system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 442system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 443system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 444system.cpu.l2cache.fast_writes 0 # number of fast writes performed 445system.cpu.l2cache.cache_copies 0 # number of cache copies performed 446system.cpu.l2cache.writebacks 0 # number of writebacks 447system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 448system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits 449system.cpu.l2cache.ReadReq_mshr_misses 365 # number of ReadReq MSHR misses 450system.cpu.l2cache.ReadExReq_mshr_misses 77 # number of ReadExReq MSHR misses 451system.cpu.l2cache.demand_mshr_misses 442 # number of demand (read+write) MSHR misses 452system.cpu.l2cache.overall_mshr_misses 442 # number of overall MSHR misses 453system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 454system.cpu.l2cache.ReadReq_mshr_miss_latency 11330000 # number of ReadReq MSHR miss cycles 455system.cpu.l2cache.ReadExReq_mshr_miss_latency 2409500 # number of ReadExReq MSHR miss cycles 456system.cpu.l2cache.demand_mshr_miss_latency 13739500 # number of demand (read+write) MSHR miss cycles 457system.cpu.l2cache.overall_mshr_miss_latency 13739500 # number of overall MSHR miss cycles 458system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 459system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994550 # mshr miss rate for ReadReq accesses 460system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses 461system.cpu.l2cache.demand_mshr_miss_rate 0.995495 # mshr miss rate for demand accesses 462system.cpu.l2cache.overall_mshr_miss_rate 0.995495 # mshr miss rate for overall accesses 463system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31041.095890 # average ReadReq mshr miss latency 464system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31292.207792 # average ReadExReq mshr miss latency 465system.cpu.l2cache.demand_avg_mshr_miss_latency 31084.841629 # average overall mshr miss latency 466system.cpu.l2cache.overall_avg_mshr_miss_latency 31084.841629 # average overall mshr miss latency 467system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 468system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 469system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 470system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 471 472---------- End Simulation Statistics ---------- 473