config.ini revision 11731:c473ca7cc650
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17default_p_state=UNDEFINED 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 43work_end_ckpt_count=0 44work_end_exit_count=0 45work_item_id=-1 46system_port=system.membus.slave[0] 47 48[system.clk_domain] 49type=SrcClockDomain 50clock=1000 51domain_id=-1 52eventq_index=0 53init_perf_level=0 54voltage_domain=system.voltage_domain 55 56[system.cpu] 57type=DerivO3CPU 58children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 59LFSTSize=1024 60LQEntries=32 61LSQCheckLoads=true 62LSQDepCheckShift=4 63SQEntries=32 64SSITSize=1024 65activity=0 66backComSize=5 67branchPred=system.cpu.branchPred 68cachePorts=200 69checker=Null 70clk_domain=system.cpu_clk_domain 71commitToDecodeDelay=1 72commitToFetchDelay=1 73commitToIEWDelay=1 74commitToRenameDelay=1 75commitWidth=8 76cpu_id=0 77decodeToFetchDelay=1 78decodeToRenameDelay=1 79decodeWidth=8 80default_p_state=UNDEFINED 81dispatchWidth=8 82do_checkpoint_insts=true 83do_quiesce=true 84do_statistics_insts=true 85dtb=system.cpu.dtb 86eventq_index=0 87fetchBufferSize=64 88fetchQueueSize=32 89fetchToDecodeDelay=1 90fetchTrapLatency=1 91fetchWidth=8 92forwardComSize=5 93fuPool=system.cpu.fuPool 94function_trace=false 95function_trace_start=0 96iewToCommitDelay=1 97iewToDecodeDelay=1 98iewToFetchDelay=1 99iewToRenameDelay=1 100interrupts=system.cpu.interrupts 101isa=system.cpu.isa 102issueToExecuteDelay=1 103issueWidth=8 104itb=system.cpu.itb 105max_insts_all_threads=0 106max_insts_any_thread=0 107max_loads_all_threads=0 108max_loads_any_thread=0 109needsTSO=true 110numIQEntries=64 111numPhysCCRegs=1280 112numPhysFloatRegs=256 113numPhysIntRegs=256 114numROBEntries=192 115numRobs=1 116numThreads=1 117p_state_clk_gate_bins=20 118p_state_clk_gate_max=1000000000000 119p_state_clk_gate_min=1000 120power_model=Null 121profile=0 122progress_interval=0 123renameToDecodeDelay=1 124renameToFetchDelay=1 125renameToIEWDelay=2 126renameToROBDelay=1 127renameWidth=8 128simpoint_start_insts= 129smtCommitPolicy=RoundRobin 130smtFetchPolicy=SingleThread 131smtIQPolicy=Partitioned 132smtIQThreshold=100 133smtLSQPolicy=Partitioned 134smtLSQThreshold=100 135smtNumFetchingThreads=1 136smtROBPolicy=Partitioned 137smtROBThreshold=100 138socket_id=0 139squashWidth=8 140store_set_clear_period=250000 141switched_out=false 142system=system 143tracer=system.cpu.tracer 144trapLatency=13 145wbWidth=8 146workload=system.cpu.workload 147dcache_port=system.cpu.dcache.cpu_side 148icache_port=system.cpu.icache.cpu_side 149 150[system.cpu.apic_clk_domain] 151type=DerivedClockDomain 152clk_divider=16 153clk_domain=system.cpu_clk_domain 154eventq_index=0 155 156[system.cpu.branchPred] 157type=TournamentBP 158BTBEntries=4096 159BTBTagSize=16 160RASSize=16 161choiceCtrBits=2 162choicePredictorSize=8192 163eventq_index=0 164globalCtrBits=2 165globalPredictorSize=8192 166indirectHashGHR=true 167indirectHashTargets=true 168indirectPathLength=3 169indirectSets=256 170indirectTagSize=16 171indirectWays=2 172instShiftAmt=2 173localCtrBits=2 174localHistoryTableSize=2048 175localPredictorSize=2048 176numThreads=1 177useIndirect=true 178 179[system.cpu.dcache] 180type=Cache 181children=tags 182addr_ranges=0:18446744073709551615:0:0:0:0 183assoc=2 184clk_domain=system.cpu_clk_domain 185clusivity=mostly_incl 186data_latency=2 187default_p_state=UNDEFINED 188demand_mshr_reserve=1 189eventq_index=0 190is_read_only=false 191max_miss_count=0 192mshrs=4 193p_state_clk_gate_bins=20 194p_state_clk_gate_max=1000000000000 195p_state_clk_gate_min=1000 196power_model=Null 197prefetch_on_access=false 198prefetcher=Null 199response_latency=2 200sequential_access=false 201size=262144 202system=system 203tag_latency=2 204tags=system.cpu.dcache.tags 205tgts_per_mshr=20 206write_buffers=8 207writeback_clean=false 208cpu_side=system.cpu.dcache_port 209mem_side=system.cpu.toL2Bus.slave[1] 210 211[system.cpu.dcache.tags] 212type=LRU 213assoc=2 214block_size=64 215clk_domain=system.cpu_clk_domain 216data_latency=2 217default_p_state=UNDEFINED 218eventq_index=0 219p_state_clk_gate_bins=20 220p_state_clk_gate_max=1000000000000 221p_state_clk_gate_min=1000 222power_model=Null 223sequential_access=false 224size=262144 225tag_latency=2 226 227[system.cpu.dtb] 228type=X86TLB 229children=walker 230eventq_index=0 231size=64 232walker=system.cpu.dtb.walker 233 234[system.cpu.dtb.walker] 235type=X86PagetableWalker 236clk_domain=system.cpu_clk_domain 237default_p_state=UNDEFINED 238eventq_index=0 239num_squash_per_cycle=4 240p_state_clk_gate_bins=20 241p_state_clk_gate_max=1000000000000 242p_state_clk_gate_min=1000 243power_model=Null 244system=system 245port=system.cpu.toL2Bus.slave[3] 246 247[system.cpu.fuPool] 248type=FUPool 249children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 250FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 251eventq_index=0 252 253[system.cpu.fuPool.FUList0] 254type=FUDesc 255children=opList 256count=6 257eventq_index=0 258opList=system.cpu.fuPool.FUList0.opList 259 260[system.cpu.fuPool.FUList0.opList] 261type=OpDesc 262eventq_index=0 263opClass=IntAlu 264opLat=1 265pipelined=true 266 267[system.cpu.fuPool.FUList1] 268type=FUDesc 269children=opList0 opList1 270count=2 271eventq_index=0 272opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 273 274[system.cpu.fuPool.FUList1.opList0] 275type=OpDesc 276eventq_index=0 277opClass=IntMult 278opLat=3 279pipelined=true 280 281[system.cpu.fuPool.FUList1.opList1] 282type=OpDesc 283eventq_index=0 284opClass=IntDiv 285opLat=1 286pipelined=false 287 288[system.cpu.fuPool.FUList2] 289type=FUDesc 290children=opList0 opList1 opList2 291count=4 292eventq_index=0 293opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 294 295[system.cpu.fuPool.FUList2.opList0] 296type=OpDesc 297eventq_index=0 298opClass=FloatAdd 299opLat=2 300pipelined=true 301 302[system.cpu.fuPool.FUList2.opList1] 303type=OpDesc 304eventq_index=0 305opClass=FloatCmp 306opLat=2 307pipelined=true 308 309[system.cpu.fuPool.FUList2.opList2] 310type=OpDesc 311eventq_index=0 312opClass=FloatCvt 313opLat=2 314pipelined=true 315 316[system.cpu.fuPool.FUList3] 317type=FUDesc 318children=opList0 opList1 opList2 opList3 opList4 319count=2 320eventq_index=0 321opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 322 323[system.cpu.fuPool.FUList3.opList0] 324type=OpDesc 325eventq_index=0 326opClass=FloatMult 327opLat=4 328pipelined=true 329 330[system.cpu.fuPool.FUList3.opList1] 331type=OpDesc 332eventq_index=0 333opClass=FloatMultAcc 334opLat=5 335pipelined=true 336 337[system.cpu.fuPool.FUList3.opList2] 338type=OpDesc 339eventq_index=0 340opClass=FloatMisc 341opLat=3 342pipelined=true 343 344[system.cpu.fuPool.FUList3.opList3] 345type=OpDesc 346eventq_index=0 347opClass=FloatDiv 348opLat=12 349pipelined=false 350 351[system.cpu.fuPool.FUList3.opList4] 352type=OpDesc 353eventq_index=0 354opClass=FloatSqrt 355opLat=24 356pipelined=false 357 358[system.cpu.fuPool.FUList4] 359type=FUDesc 360children=opList0 opList1 361count=0 362eventq_index=0 363opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 364 365[system.cpu.fuPool.FUList4.opList0] 366type=OpDesc 367eventq_index=0 368opClass=MemRead 369opLat=1 370pipelined=true 371 372[system.cpu.fuPool.FUList4.opList1] 373type=OpDesc 374eventq_index=0 375opClass=FloatMemRead 376opLat=1 377pipelined=true 378 379[system.cpu.fuPool.FUList5] 380type=FUDesc 381children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 382count=4 383eventq_index=0 384opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 385 386[system.cpu.fuPool.FUList5.opList00] 387type=OpDesc 388eventq_index=0 389opClass=SimdAdd 390opLat=1 391pipelined=true 392 393[system.cpu.fuPool.FUList5.opList01] 394type=OpDesc 395eventq_index=0 396opClass=SimdAddAcc 397opLat=1 398pipelined=true 399 400[system.cpu.fuPool.FUList5.opList02] 401type=OpDesc 402eventq_index=0 403opClass=SimdAlu 404opLat=1 405pipelined=true 406 407[system.cpu.fuPool.FUList5.opList03] 408type=OpDesc 409eventq_index=0 410opClass=SimdCmp 411opLat=1 412pipelined=true 413 414[system.cpu.fuPool.FUList5.opList04] 415type=OpDesc 416eventq_index=0 417opClass=SimdCvt 418opLat=1 419pipelined=true 420 421[system.cpu.fuPool.FUList5.opList05] 422type=OpDesc 423eventq_index=0 424opClass=SimdMisc 425opLat=1 426pipelined=true 427 428[system.cpu.fuPool.FUList5.opList06] 429type=OpDesc 430eventq_index=0 431opClass=SimdMult 432opLat=1 433pipelined=true 434 435[system.cpu.fuPool.FUList5.opList07] 436type=OpDesc 437eventq_index=0 438opClass=SimdMultAcc 439opLat=1 440pipelined=true 441 442[system.cpu.fuPool.FUList5.opList08] 443type=OpDesc 444eventq_index=0 445opClass=SimdShift 446opLat=1 447pipelined=true 448 449[system.cpu.fuPool.FUList5.opList09] 450type=OpDesc 451eventq_index=0 452opClass=SimdShiftAcc 453opLat=1 454pipelined=true 455 456[system.cpu.fuPool.FUList5.opList10] 457type=OpDesc 458eventq_index=0 459opClass=SimdSqrt 460opLat=1 461pipelined=true 462 463[system.cpu.fuPool.FUList5.opList11] 464type=OpDesc 465eventq_index=0 466opClass=SimdFloatAdd 467opLat=1 468pipelined=true 469 470[system.cpu.fuPool.FUList5.opList12] 471type=OpDesc 472eventq_index=0 473opClass=SimdFloatAlu 474opLat=1 475pipelined=true 476 477[system.cpu.fuPool.FUList5.opList13] 478type=OpDesc 479eventq_index=0 480opClass=SimdFloatCmp 481opLat=1 482pipelined=true 483 484[system.cpu.fuPool.FUList5.opList14] 485type=OpDesc 486eventq_index=0 487opClass=SimdFloatCvt 488opLat=1 489pipelined=true 490 491[system.cpu.fuPool.FUList5.opList15] 492type=OpDesc 493eventq_index=0 494opClass=SimdFloatDiv 495opLat=1 496pipelined=true 497 498[system.cpu.fuPool.FUList5.opList16] 499type=OpDesc 500eventq_index=0 501opClass=SimdFloatMisc 502opLat=1 503pipelined=true 504 505[system.cpu.fuPool.FUList5.opList17] 506type=OpDesc 507eventq_index=0 508opClass=SimdFloatMult 509opLat=1 510pipelined=true 511 512[system.cpu.fuPool.FUList5.opList18] 513type=OpDesc 514eventq_index=0 515opClass=SimdFloatMultAcc 516opLat=1 517pipelined=true 518 519[system.cpu.fuPool.FUList5.opList19] 520type=OpDesc 521eventq_index=0 522opClass=SimdFloatSqrt 523opLat=1 524pipelined=true 525 526[system.cpu.fuPool.FUList6] 527type=FUDesc 528children=opList0 opList1 529count=0 530eventq_index=0 531opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 532 533[system.cpu.fuPool.FUList6.opList0] 534type=OpDesc 535eventq_index=0 536opClass=MemWrite 537opLat=1 538pipelined=true 539 540[system.cpu.fuPool.FUList6.opList1] 541type=OpDesc 542eventq_index=0 543opClass=FloatMemWrite 544opLat=1 545pipelined=true 546 547[system.cpu.fuPool.FUList7] 548type=FUDesc 549children=opList0 opList1 opList2 opList3 550count=4 551eventq_index=0 552opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 553 554[system.cpu.fuPool.FUList7.opList0] 555type=OpDesc 556eventq_index=0 557opClass=MemRead 558opLat=1 559pipelined=true 560 561[system.cpu.fuPool.FUList7.opList1] 562type=OpDesc 563eventq_index=0 564opClass=MemWrite 565opLat=1 566pipelined=true 567 568[system.cpu.fuPool.FUList7.opList2] 569type=OpDesc 570eventq_index=0 571opClass=FloatMemRead 572opLat=1 573pipelined=true 574 575[system.cpu.fuPool.FUList7.opList3] 576type=OpDesc 577eventq_index=0 578opClass=FloatMemWrite 579opLat=1 580pipelined=true 581 582[system.cpu.fuPool.FUList8] 583type=FUDesc 584children=opList 585count=1 586eventq_index=0 587opList=system.cpu.fuPool.FUList8.opList 588 589[system.cpu.fuPool.FUList8.opList] 590type=OpDesc 591eventq_index=0 592opClass=IprAccess 593opLat=3 594pipelined=false 595 596[system.cpu.icache] 597type=Cache 598children=tags 599addr_ranges=0:18446744073709551615:0:0:0:0 600assoc=2 601clk_domain=system.cpu_clk_domain 602clusivity=mostly_incl 603data_latency=2 604default_p_state=UNDEFINED 605demand_mshr_reserve=1 606eventq_index=0 607is_read_only=true 608max_miss_count=0 609mshrs=4 610p_state_clk_gate_bins=20 611p_state_clk_gate_max=1000000000000 612p_state_clk_gate_min=1000 613power_model=Null 614prefetch_on_access=false 615prefetcher=Null 616response_latency=2 617sequential_access=false 618size=131072 619system=system 620tag_latency=2 621tags=system.cpu.icache.tags 622tgts_per_mshr=20 623write_buffers=8 624writeback_clean=true 625cpu_side=system.cpu.icache_port 626mem_side=system.cpu.toL2Bus.slave[0] 627 628[system.cpu.icache.tags] 629type=LRU 630assoc=2 631block_size=64 632clk_domain=system.cpu_clk_domain 633data_latency=2 634default_p_state=UNDEFINED 635eventq_index=0 636p_state_clk_gate_bins=20 637p_state_clk_gate_max=1000000000000 638p_state_clk_gate_min=1000 639power_model=Null 640sequential_access=false 641size=131072 642tag_latency=2 643 644[system.cpu.interrupts] 645type=X86LocalApic 646clk_domain=system.cpu.apic_clk_domain 647default_p_state=UNDEFINED 648eventq_index=0 649int_latency=1000 650p_state_clk_gate_bins=20 651p_state_clk_gate_max=1000000000000 652p_state_clk_gate_min=1000 653pio_addr=2305843009213693952 654pio_latency=100000 655power_model=Null 656system=system 657int_master=system.membus.slave[2] 658int_slave=system.membus.master[2] 659pio=system.membus.master[1] 660 661[system.cpu.isa] 662type=X86ISA 663eventq_index=0 664 665[system.cpu.itb] 666type=X86TLB 667children=walker 668eventq_index=0 669size=64 670walker=system.cpu.itb.walker 671 672[system.cpu.itb.walker] 673type=X86PagetableWalker 674clk_domain=system.cpu_clk_domain 675default_p_state=UNDEFINED 676eventq_index=0 677num_squash_per_cycle=4 678p_state_clk_gate_bins=20 679p_state_clk_gate_max=1000000000000 680p_state_clk_gate_min=1000 681power_model=Null 682system=system 683port=system.cpu.toL2Bus.slave[2] 684 685[system.cpu.l2cache] 686type=Cache 687children=tags 688addr_ranges=0:18446744073709551615:0:0:0:0 689assoc=8 690clk_domain=system.cpu_clk_domain 691clusivity=mostly_incl 692data_latency=20 693default_p_state=UNDEFINED 694demand_mshr_reserve=1 695eventq_index=0 696is_read_only=false 697max_miss_count=0 698mshrs=20 699p_state_clk_gate_bins=20 700p_state_clk_gate_max=1000000000000 701p_state_clk_gate_min=1000 702power_model=Null 703prefetch_on_access=false 704prefetcher=Null 705response_latency=20 706sequential_access=false 707size=2097152 708system=system 709tag_latency=20 710tags=system.cpu.l2cache.tags 711tgts_per_mshr=12 712write_buffers=8 713writeback_clean=false 714cpu_side=system.cpu.toL2Bus.master[0] 715mem_side=system.membus.slave[1] 716 717[system.cpu.l2cache.tags] 718type=LRU 719assoc=8 720block_size=64 721clk_domain=system.cpu_clk_domain 722data_latency=20 723default_p_state=UNDEFINED 724eventq_index=0 725p_state_clk_gate_bins=20 726p_state_clk_gate_max=1000000000000 727p_state_clk_gate_min=1000 728power_model=Null 729sequential_access=false 730size=2097152 731tag_latency=20 732 733[system.cpu.toL2Bus] 734type=CoherentXBar 735children=snoop_filter 736clk_domain=system.cpu_clk_domain 737default_p_state=UNDEFINED 738eventq_index=0 739forward_latency=0 740frontend_latency=1 741p_state_clk_gate_bins=20 742p_state_clk_gate_max=1000000000000 743p_state_clk_gate_min=1000 744point_of_coherency=false 745power_model=Null 746response_latency=1 747snoop_filter=system.cpu.toL2Bus.snoop_filter 748snoop_response_latency=1 749system=system 750use_default_range=false 751width=32 752master=system.cpu.l2cache.cpu_side 753slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 754 755[system.cpu.toL2Bus.snoop_filter] 756type=SnoopFilter 757eventq_index=0 758lookup_latency=0 759max_capacity=8388608 760system=system 761 762[system.cpu.tracer] 763type=ExeTracer 764eventq_index=0 765 766[system.cpu.workload] 767type=LiveProcess 768cmd=hello 769cwd= 770drivers= 771egid=100 772env= 773errout=cerr 774euid=100 775eventq_index=0 776executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello 777gid=100 778input=cin 779kvmInSE=false 780max_stack_size=67108864 781output=cout 782pid=100 783ppid=99 784simpoint=0 785system=system 786uid=100 787useArchPT=false 788 789[system.cpu_clk_domain] 790type=SrcClockDomain 791clock=500 792domain_id=-1 793eventq_index=0 794init_perf_level=0 795voltage_domain=system.voltage_domain 796 797[system.dvfs_handler] 798type=DVFSHandler 799domains= 800enable=false 801eventq_index=0 802sys_clk_domain=system.clk_domain 803transition_latency=100000000 804 805[system.membus] 806type=CoherentXBar 807children=snoop_filter 808clk_domain=system.clk_domain 809default_p_state=UNDEFINED 810eventq_index=0 811forward_latency=4 812frontend_latency=3 813p_state_clk_gate_bins=20 814p_state_clk_gate_max=1000000000000 815p_state_clk_gate_min=1000 816point_of_coherency=true 817power_model=Null 818response_latency=2 819snoop_filter=system.membus.snoop_filter 820snoop_response_latency=4 821system=system 822use_default_range=false 823width=16 824master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave 825slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 826 827[system.membus.snoop_filter] 828type=SnoopFilter 829eventq_index=0 830lookup_latency=1 831max_capacity=8388608 832system=system 833 834[system.physmem] 835type=DRAMCtrl 836IDD0=0.055000 837IDD02=0.000000 838IDD2N=0.032000 839IDD2N2=0.000000 840IDD2P0=0.000000 841IDD2P02=0.000000 842IDD2P1=0.032000 843IDD2P12=0.000000 844IDD3N=0.038000 845IDD3N2=0.000000 846IDD3P0=0.000000 847IDD3P02=0.000000 848IDD3P1=0.038000 849IDD3P12=0.000000 850IDD4R=0.157000 851IDD4R2=0.000000 852IDD4W=0.125000 853IDD4W2=0.000000 854IDD5=0.235000 855IDD52=0.000000 856IDD6=0.020000 857IDD62=0.000000 858VDD=1.500000 859VDD2=0.000000 860activation_limit=4 861addr_mapping=RoRaBaCoCh 862bank_groups_per_rank=0 863banks_per_rank=8 864burst_length=8 865channels=1 866clk_domain=system.clk_domain 867conf_table_reported=true 868default_p_state=UNDEFINED 869device_bus_width=8 870device_rowbuffer_size=1024 871device_size=536870912 872devices_per_rank=8 873dll=true 874eventq_index=0 875in_addr_map=true 876kvm_map=true 877max_accesses_per_row=16 878mem_sched_policy=frfcfs 879min_writes_per_switch=16 880null=false 881p_state_clk_gate_bins=20 882p_state_clk_gate_max=1000000000000 883p_state_clk_gate_min=1000 884page_policy=open_adaptive 885power_model=Null 886range=0:134217727:0:0:0:0 887ranks_per_channel=2 888read_buffer_size=32 889static_backend_latency=10000 890static_frontend_latency=10000 891tBURST=5000 892tCCD_L=0 893tCK=1250 894tCL=13750 895tCS=2500 896tRAS=35000 897tRCD=13750 898tREFI=7800000 899tRFC=260000 900tRP=13750 901tRRD=6000 902tRRD_L=0 903tRTP=7500 904tRTW=2500 905tWR=15000 906tWTR=7500 907tXAW=30000 908tXP=6000 909tXPDLL=0 910tXS=270000 911tXSDLL=0 912write_buffer_size=64 913write_high_thresh_perc=85 914write_low_thresh_perc=50 915port=system.membus.master[0] 916 917[system.voltage_domain] 918type=VoltageDomain 919eventq_index=0 920voltage=1.000000 921 922