config.ini revision 11440:76b5639162af
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18exit_on_work_items=false 19init_param=0 20kernel= 21kernel_addr_check=true 22load_addr_mask=1099511627775 23load_offset=0 24mem_mode=timing 25mem_ranges= 26memories=system.physmem 27mmap_using_noreserve=false 28multi_thread=false 29num_work_ids=16 30readfile= 31symbolfile= 32thermal_components= 33thermal_model=Null 34work_begin_ckpt_count=0 35work_begin_cpu_id_exit=-1 36work_begin_exit_count=0 37work_cpus_ckpt_count=0 38work_end_ckpt_count=0 39work_end_exit_count=0 40work_item_id=-1 41system_port=system.membus.slave[0] 42 43[system.clk_domain] 44type=SrcClockDomain 45clock=1000 46domain_id=-1 47eventq_index=0 48init_perf_level=0 49voltage_domain=system.voltage_domain 50 51[system.cpu] 52type=DerivO3CPU 53children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 54LFSTSize=1024 55LQEntries=32 56LSQCheckLoads=true 57LSQDepCheckShift=4 58SQEntries=32 59SSITSize=1024 60activity=0 61backComSize=5 62branchPred=system.cpu.branchPred 63cachePorts=200 64checker=Null 65clk_domain=system.cpu_clk_domain 66commitToDecodeDelay=1 67commitToFetchDelay=1 68commitToIEWDelay=1 69commitToRenameDelay=1 70commitWidth=8 71cpu_id=0 72decodeToFetchDelay=1 73decodeToRenameDelay=1 74decodeWidth=8 75dispatchWidth=8 76do_checkpoint_insts=true 77do_quiesce=true 78do_statistics_insts=true 79dtb=system.cpu.dtb 80eventq_index=0 81fetchBufferSize=64 82fetchQueueSize=32 83fetchToDecodeDelay=1 84fetchTrapLatency=1 85fetchWidth=8 86forwardComSize=5 87fuPool=system.cpu.fuPool 88function_trace=false 89function_trace_start=0 90iewToCommitDelay=1 91iewToDecodeDelay=1 92iewToFetchDelay=1 93iewToRenameDelay=1 94interrupts=system.cpu.interrupts 95isa=system.cpu.isa 96issueToExecuteDelay=1 97issueWidth=8 98itb=system.cpu.itb 99max_insts_all_threads=0 100max_insts_any_thread=0 101max_loads_all_threads=0 102max_loads_any_thread=0 103needsTSO=true 104numIQEntries=64 105numPhysCCRegs=1280 106numPhysFloatRegs=256 107numPhysIntRegs=256 108numROBEntries=192 109numRobs=1 110numThreads=1 111profile=0 112progress_interval=0 113renameToDecodeDelay=1 114renameToFetchDelay=1 115renameToIEWDelay=2 116renameToROBDelay=1 117renameWidth=8 118simpoint_start_insts= 119smtCommitPolicy=RoundRobin 120smtFetchPolicy=SingleThread 121smtIQPolicy=Partitioned 122smtIQThreshold=100 123smtLSQPolicy=Partitioned 124smtLSQThreshold=100 125smtNumFetchingThreads=1 126smtROBPolicy=Partitioned 127smtROBThreshold=100 128socket_id=0 129squashWidth=8 130store_set_clear_period=250000 131switched_out=false 132system=system 133tracer=system.cpu.tracer 134trapLatency=13 135wbWidth=8 136workload=system.cpu.workload 137dcache_port=system.cpu.dcache.cpu_side 138icache_port=system.cpu.icache.cpu_side 139 140[system.cpu.apic_clk_domain] 141type=DerivedClockDomain 142clk_divider=16 143clk_domain=system.cpu_clk_domain 144eventq_index=0 145 146[system.cpu.branchPred] 147type=TournamentBP 148BTBEntries=4096 149BTBTagSize=16 150RASSize=16 151choiceCtrBits=2 152choicePredictorSize=8192 153eventq_index=0 154globalCtrBits=2 155globalPredictorSize=8192 156indirectHashGHR=true 157indirectHashTargets=true 158indirectPathLength=3 159indirectSets=256 160indirectTagSize=16 161indirectWays=2 162instShiftAmt=2 163localCtrBits=2 164localHistoryTableSize=2048 165localPredictorSize=2048 166numThreads=1 167useIndirect=true 168 169[system.cpu.dcache] 170type=Cache 171children=tags 172addr_ranges=0:18446744073709551615 173assoc=2 174clk_domain=system.cpu_clk_domain 175clusivity=mostly_incl 176demand_mshr_reserve=1 177eventq_index=0 178hit_latency=2 179is_read_only=false 180max_miss_count=0 181mshrs=4 182prefetch_on_access=false 183prefetcher=Null 184response_latency=2 185sequential_access=false 186size=262144 187system=system 188tags=system.cpu.dcache.tags 189tgts_per_mshr=20 190write_buffers=8 191writeback_clean=false 192cpu_side=system.cpu.dcache_port 193mem_side=system.cpu.toL2Bus.slave[1] 194 195[system.cpu.dcache.tags] 196type=LRU 197assoc=2 198block_size=64 199clk_domain=system.cpu_clk_domain 200eventq_index=0 201hit_latency=2 202sequential_access=false 203size=262144 204 205[system.cpu.dtb] 206type=X86TLB 207children=walker 208eventq_index=0 209size=64 210walker=system.cpu.dtb.walker 211 212[system.cpu.dtb.walker] 213type=X86PagetableWalker 214clk_domain=system.cpu_clk_domain 215eventq_index=0 216num_squash_per_cycle=4 217system=system 218port=system.cpu.toL2Bus.slave[3] 219 220[system.cpu.fuPool] 221type=FUPool 222children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 223FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 224eventq_index=0 225 226[system.cpu.fuPool.FUList0] 227type=FUDesc 228children=opList 229count=6 230eventq_index=0 231opList=system.cpu.fuPool.FUList0.opList 232 233[system.cpu.fuPool.FUList0.opList] 234type=OpDesc 235eventq_index=0 236opClass=IntAlu 237opLat=1 238pipelined=true 239 240[system.cpu.fuPool.FUList1] 241type=FUDesc 242children=opList0 opList1 243count=2 244eventq_index=0 245opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 246 247[system.cpu.fuPool.FUList1.opList0] 248type=OpDesc 249eventq_index=0 250opClass=IntMult 251opLat=3 252pipelined=true 253 254[system.cpu.fuPool.FUList1.opList1] 255type=OpDesc 256eventq_index=0 257opClass=IntDiv 258opLat=1 259pipelined=false 260 261[system.cpu.fuPool.FUList2] 262type=FUDesc 263children=opList0 opList1 opList2 264count=4 265eventq_index=0 266opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 267 268[system.cpu.fuPool.FUList2.opList0] 269type=OpDesc 270eventq_index=0 271opClass=FloatAdd 272opLat=2 273pipelined=true 274 275[system.cpu.fuPool.FUList2.opList1] 276type=OpDesc 277eventq_index=0 278opClass=FloatCmp 279opLat=2 280pipelined=true 281 282[system.cpu.fuPool.FUList2.opList2] 283type=OpDesc 284eventq_index=0 285opClass=FloatCvt 286opLat=2 287pipelined=true 288 289[system.cpu.fuPool.FUList3] 290type=FUDesc 291children=opList0 opList1 opList2 292count=2 293eventq_index=0 294opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 295 296[system.cpu.fuPool.FUList3.opList0] 297type=OpDesc 298eventq_index=0 299opClass=FloatMult 300opLat=4 301pipelined=true 302 303[system.cpu.fuPool.FUList3.opList1] 304type=OpDesc 305eventq_index=0 306opClass=FloatDiv 307opLat=12 308pipelined=false 309 310[system.cpu.fuPool.FUList3.opList2] 311type=OpDesc 312eventq_index=0 313opClass=FloatSqrt 314opLat=24 315pipelined=false 316 317[system.cpu.fuPool.FUList4] 318type=FUDesc 319children=opList 320count=0 321eventq_index=0 322opList=system.cpu.fuPool.FUList4.opList 323 324[system.cpu.fuPool.FUList4.opList] 325type=OpDesc 326eventq_index=0 327opClass=MemRead 328opLat=1 329pipelined=true 330 331[system.cpu.fuPool.FUList5] 332type=FUDesc 333children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 334count=4 335eventq_index=0 336opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 337 338[system.cpu.fuPool.FUList5.opList00] 339type=OpDesc 340eventq_index=0 341opClass=SimdAdd 342opLat=1 343pipelined=true 344 345[system.cpu.fuPool.FUList5.opList01] 346type=OpDesc 347eventq_index=0 348opClass=SimdAddAcc 349opLat=1 350pipelined=true 351 352[system.cpu.fuPool.FUList5.opList02] 353type=OpDesc 354eventq_index=0 355opClass=SimdAlu 356opLat=1 357pipelined=true 358 359[system.cpu.fuPool.FUList5.opList03] 360type=OpDesc 361eventq_index=0 362opClass=SimdCmp 363opLat=1 364pipelined=true 365 366[system.cpu.fuPool.FUList5.opList04] 367type=OpDesc 368eventq_index=0 369opClass=SimdCvt 370opLat=1 371pipelined=true 372 373[system.cpu.fuPool.FUList5.opList05] 374type=OpDesc 375eventq_index=0 376opClass=SimdMisc 377opLat=1 378pipelined=true 379 380[system.cpu.fuPool.FUList5.opList06] 381type=OpDesc 382eventq_index=0 383opClass=SimdMult 384opLat=1 385pipelined=true 386 387[system.cpu.fuPool.FUList5.opList07] 388type=OpDesc 389eventq_index=0 390opClass=SimdMultAcc 391opLat=1 392pipelined=true 393 394[system.cpu.fuPool.FUList5.opList08] 395type=OpDesc 396eventq_index=0 397opClass=SimdShift 398opLat=1 399pipelined=true 400 401[system.cpu.fuPool.FUList5.opList09] 402type=OpDesc 403eventq_index=0 404opClass=SimdShiftAcc 405opLat=1 406pipelined=true 407 408[system.cpu.fuPool.FUList5.opList10] 409type=OpDesc 410eventq_index=0 411opClass=SimdSqrt 412opLat=1 413pipelined=true 414 415[system.cpu.fuPool.FUList5.opList11] 416type=OpDesc 417eventq_index=0 418opClass=SimdFloatAdd 419opLat=1 420pipelined=true 421 422[system.cpu.fuPool.FUList5.opList12] 423type=OpDesc 424eventq_index=0 425opClass=SimdFloatAlu 426opLat=1 427pipelined=true 428 429[system.cpu.fuPool.FUList5.opList13] 430type=OpDesc 431eventq_index=0 432opClass=SimdFloatCmp 433opLat=1 434pipelined=true 435 436[system.cpu.fuPool.FUList5.opList14] 437type=OpDesc 438eventq_index=0 439opClass=SimdFloatCvt 440opLat=1 441pipelined=true 442 443[system.cpu.fuPool.FUList5.opList15] 444type=OpDesc 445eventq_index=0 446opClass=SimdFloatDiv 447opLat=1 448pipelined=true 449 450[system.cpu.fuPool.FUList5.opList16] 451type=OpDesc 452eventq_index=0 453opClass=SimdFloatMisc 454opLat=1 455pipelined=true 456 457[system.cpu.fuPool.FUList5.opList17] 458type=OpDesc 459eventq_index=0 460opClass=SimdFloatMult 461opLat=1 462pipelined=true 463 464[system.cpu.fuPool.FUList5.opList18] 465type=OpDesc 466eventq_index=0 467opClass=SimdFloatMultAcc 468opLat=1 469pipelined=true 470 471[system.cpu.fuPool.FUList5.opList19] 472type=OpDesc 473eventq_index=0 474opClass=SimdFloatSqrt 475opLat=1 476pipelined=true 477 478[system.cpu.fuPool.FUList6] 479type=FUDesc 480children=opList 481count=0 482eventq_index=0 483opList=system.cpu.fuPool.FUList6.opList 484 485[system.cpu.fuPool.FUList6.opList] 486type=OpDesc 487eventq_index=0 488opClass=MemWrite 489opLat=1 490pipelined=true 491 492[system.cpu.fuPool.FUList7] 493type=FUDesc 494children=opList0 opList1 495count=4 496eventq_index=0 497opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 498 499[system.cpu.fuPool.FUList7.opList0] 500type=OpDesc 501eventq_index=0 502opClass=MemRead 503opLat=1 504pipelined=true 505 506[system.cpu.fuPool.FUList7.opList1] 507type=OpDesc 508eventq_index=0 509opClass=MemWrite 510opLat=1 511pipelined=true 512 513[system.cpu.fuPool.FUList8] 514type=FUDesc 515children=opList 516count=1 517eventq_index=0 518opList=system.cpu.fuPool.FUList8.opList 519 520[system.cpu.fuPool.FUList8.opList] 521type=OpDesc 522eventq_index=0 523opClass=IprAccess 524opLat=3 525pipelined=false 526 527[system.cpu.icache] 528type=Cache 529children=tags 530addr_ranges=0:18446744073709551615 531assoc=2 532clk_domain=system.cpu_clk_domain 533clusivity=mostly_incl 534demand_mshr_reserve=1 535eventq_index=0 536hit_latency=2 537is_read_only=true 538max_miss_count=0 539mshrs=4 540prefetch_on_access=false 541prefetcher=Null 542response_latency=2 543sequential_access=false 544size=131072 545system=system 546tags=system.cpu.icache.tags 547tgts_per_mshr=20 548write_buffers=8 549writeback_clean=true 550cpu_side=system.cpu.icache_port 551mem_side=system.cpu.toL2Bus.slave[0] 552 553[system.cpu.icache.tags] 554type=LRU 555assoc=2 556block_size=64 557clk_domain=system.cpu_clk_domain 558eventq_index=0 559hit_latency=2 560sequential_access=false 561size=131072 562 563[system.cpu.interrupts] 564type=X86LocalApic 565clk_domain=system.cpu.apic_clk_domain 566eventq_index=0 567int_latency=1000 568pio_addr=2305843009213693952 569pio_latency=100000 570system=system 571int_master=system.membus.slave[2] 572int_slave=system.membus.master[2] 573pio=system.membus.master[1] 574 575[system.cpu.isa] 576type=X86ISA 577eventq_index=0 578 579[system.cpu.itb] 580type=X86TLB 581children=walker 582eventq_index=0 583size=64 584walker=system.cpu.itb.walker 585 586[system.cpu.itb.walker] 587type=X86PagetableWalker 588clk_domain=system.cpu_clk_domain 589eventq_index=0 590num_squash_per_cycle=4 591system=system 592port=system.cpu.toL2Bus.slave[2] 593 594[system.cpu.l2cache] 595type=Cache 596children=tags 597addr_ranges=0:18446744073709551615 598assoc=8 599clk_domain=system.cpu_clk_domain 600clusivity=mostly_incl 601demand_mshr_reserve=1 602eventq_index=0 603hit_latency=20 604is_read_only=false 605max_miss_count=0 606mshrs=20 607prefetch_on_access=false 608prefetcher=Null 609response_latency=20 610sequential_access=false 611size=2097152 612system=system 613tags=system.cpu.l2cache.tags 614tgts_per_mshr=12 615write_buffers=8 616writeback_clean=false 617cpu_side=system.cpu.toL2Bus.master[0] 618mem_side=system.membus.slave[1] 619 620[system.cpu.l2cache.tags] 621type=LRU 622assoc=8 623block_size=64 624clk_domain=system.cpu_clk_domain 625eventq_index=0 626hit_latency=20 627sequential_access=false 628size=2097152 629 630[system.cpu.toL2Bus] 631type=CoherentXBar 632children=snoop_filter 633clk_domain=system.cpu_clk_domain 634eventq_index=0 635forward_latency=0 636frontend_latency=1 637point_of_coherency=false 638response_latency=1 639snoop_filter=system.cpu.toL2Bus.snoop_filter 640snoop_response_latency=1 641system=system 642use_default_range=false 643width=32 644master=system.cpu.l2cache.cpu_side 645slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 646 647[system.cpu.toL2Bus.snoop_filter] 648type=SnoopFilter 649eventq_index=0 650lookup_latency=0 651max_capacity=8388608 652system=system 653 654[system.cpu.tracer] 655type=ExeTracer 656eventq_index=0 657 658[system.cpu.workload] 659type=LiveProcess 660cmd=hello 661cwd= 662drivers= 663egid=100 664env= 665errout=cerr 666euid=100 667eventq_index=0 668executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/x86/linux/hello 669gid=100 670input=cin 671kvmInSE=false 672max_stack_size=67108864 673output=cout 674pid=100 675ppid=99 676simpoint=0 677system=system 678uid=100 679useArchPT=false 680 681[system.cpu_clk_domain] 682type=SrcClockDomain 683clock=500 684domain_id=-1 685eventq_index=0 686init_perf_level=0 687voltage_domain=system.voltage_domain 688 689[system.dvfs_handler] 690type=DVFSHandler 691domains= 692enable=false 693eventq_index=0 694sys_clk_domain=system.clk_domain 695transition_latency=100000000 696 697[system.membus] 698type=CoherentXBar 699clk_domain=system.clk_domain 700eventq_index=0 701forward_latency=4 702frontend_latency=3 703point_of_coherency=true 704response_latency=2 705snoop_filter=Null 706snoop_response_latency=4 707system=system 708use_default_range=false 709width=16 710master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave 711slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 712 713[system.physmem] 714type=DRAMCtrl 715IDD0=0.075000 716IDD02=0.000000 717IDD2N=0.050000 718IDD2N2=0.000000 719IDD2P0=0.000000 720IDD2P02=0.000000 721IDD2P1=0.000000 722IDD2P12=0.000000 723IDD3N=0.057000 724IDD3N2=0.000000 725IDD3P0=0.000000 726IDD3P02=0.000000 727IDD3P1=0.000000 728IDD3P12=0.000000 729IDD4R=0.187000 730IDD4R2=0.000000 731IDD4W=0.165000 732IDD4W2=0.000000 733IDD5=0.220000 734IDD52=0.000000 735IDD6=0.000000 736IDD62=0.000000 737VDD=1.500000 738VDD2=0.000000 739activation_limit=4 740addr_mapping=RoRaBaCoCh 741bank_groups_per_rank=0 742banks_per_rank=8 743burst_length=8 744channels=1 745clk_domain=system.clk_domain 746conf_table_reported=true 747device_bus_width=8 748device_rowbuffer_size=1024 749device_size=536870912 750devices_per_rank=8 751dll=true 752eventq_index=0 753in_addr_map=true 754max_accesses_per_row=16 755mem_sched_policy=frfcfs 756min_writes_per_switch=16 757null=false 758page_policy=open_adaptive 759range=0:134217727 760ranks_per_channel=2 761read_buffer_size=32 762static_backend_latency=10000 763static_frontend_latency=10000 764tBURST=5000 765tCCD_L=0 766tCK=1250 767tCL=13750 768tCS=2500 769tRAS=35000 770tRCD=13750 771tREFI=7800000 772tRFC=260000 773tRP=13750 774tRRD=6000 775tRRD_L=0 776tRTP=7500 777tRTW=2500 778tWR=15000 779tWTR=7500 780tXAW=30000 781tXP=0 782tXPDLL=0 783tXS=0 784tXSDLL=0 785write_buffer_size=64 786write_high_thresh_perc=85 787write_low_thresh_perc=50 788port=system.membus.master[0] 789 790[system.voltage_domain] 791type=VoltageDomain 792eventq_index=0 793voltage=1.000000 794 795