stats.txt revision 10892:bd37e25fb3b7
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000028 # Number of seconds simulated 4sim_ticks 27800500 # Number of ticks simulated 5final_tick 27800500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 428112 # Simulator instruction rate (inst/s) 8host_op_rate 427631 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2229390537 # Simulator tick rate (ticks/s) 10host_mem_usage 290104 # Number of bytes of host memory used 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 5327 # Number of instructions simulated 13sim_ops 5327 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory 18system.physmem.bytes_read::total 24896 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 16320 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 16320 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 389 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 587039801 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 308483660 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 895523462 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 587039801 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 587039801 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 587039801 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 308483660 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 895523462 # Total bandwidth to/from this memory (bytes/s) 32system.cpu_clk_domain.clock 500 # Clock period in ticks 33system.cpu.workload.num_syscalls 11 # Number of system calls 34system.cpu.numCycles 55601 # number of cpu cycles simulated 35system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 36system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 37system.cpu.committedInsts 5327 # Number of instructions committed 38system.cpu.committedOps 5327 # Number of ops (including micro ops) committed 39system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses 40system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 41system.cpu.num_func_calls 146 # number of times a function call or return occured 42system.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls 43system.cpu.num_int_insts 4505 # number of integer instructions 44system.cpu.num_fp_insts 0 # number of float instructions 45system.cpu.num_int_register_reads 10598 # number of times the integer registers were read 46system.cpu.num_int_register_writes 4845 # number of times the integer registers were written 47system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 48system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 49system.cpu.num_mem_refs 1401 # number of memory refs 50system.cpu.num_load_insts 723 # Number of load instructions 51system.cpu.num_store_insts 678 # Number of store instructions 52system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 53system.cpu.num_busy_cycles 55600.998000 # Number of busy cycles 54system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 55system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 56system.cpu.Branches 1121 # Number of branches fetched 57system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction 58system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction 59system.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction 60system.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction 61system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction 62system.cpu.op_class::FloatCmp 0 0.00% 73.91% # Class of executed instruction 63system.cpu.op_class::FloatCvt 0 0.00% 73.91% # Class of executed instruction 64system.cpu.op_class::FloatMult 0 0.00% 73.91% # Class of executed instruction 65system.cpu.op_class::FloatDiv 0 0.00% 73.91% # Class of executed instruction 66system.cpu.op_class::FloatSqrt 0 0.00% 73.91% # Class of executed instruction 67system.cpu.op_class::SimdAdd 0 0.00% 73.91% # Class of executed instruction 68system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% # Class of executed instruction 69system.cpu.op_class::SimdAlu 0 0.00% 73.91% # Class of executed instruction 70system.cpu.op_class::SimdCmp 0 0.00% 73.91% # Class of executed instruction 71system.cpu.op_class::SimdCvt 0 0.00% 73.91% # Class of executed instruction 72system.cpu.op_class::SimdMisc 0 0.00% 73.91% # Class of executed instruction 73system.cpu.op_class::SimdMult 0 0.00% 73.91% # Class of executed instruction 74system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% # Class of executed instruction 75system.cpu.op_class::SimdShift 0 0.00% 73.91% # Class of executed instruction 76system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% # Class of executed instruction 77system.cpu.op_class::SimdSqrt 0 0.00% 73.91% # Class of executed instruction 78system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% # Class of executed instruction 79system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% # Class of executed instruction 80system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% # Class of executed instruction 81system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% # Class of executed instruction 82system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% # Class of executed instruction 83system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% # Class of executed instruction 84system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction 85system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction 86system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction 87system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction 88system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction 89system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 90system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 91system.cpu.op_class::total 5370 # Class of executed instruction 92system.cpu.dcache.tags.replacements 0 # number of replacements 93system.cpu.dcache.tags.tagsinuse 82.112122 # Cycle average of tags in use 94system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. 95system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. 96system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks. 97system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 98system.cpu.dcache.tags.occ_blocks::cpu.data 82.112122 # Average occupied blocks per requestor 99system.cpu.dcache.tags.occ_percent::cpu.data 0.020047 # Average percentage of cache occupancy 100system.cpu.dcache.tags.occ_percent::total 0.020047 # Average percentage of cache occupancy 101system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id 102system.cpu.dcache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id 103system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id 104system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id 105system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses 106system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses 107system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits 108system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits 109system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits 110system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits 111system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits 112system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits 113system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits 114system.cpu.dcache.overall_hits::total 1253 # number of overall hits 115system.cpu.dcache.ReadReq_misses::cpu.data 54 # number of ReadReq misses 116system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses 117system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses 118system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses 119system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses 120system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses 121system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses 122system.cpu.dcache.overall_misses::total 135 # number of overall misses 123system.cpu.dcache.ReadReq_miss_latency::cpu.data 2928000 # number of ReadReq miss cycles 124system.cpu.dcache.ReadReq_miss_latency::total 2928000 # number of ReadReq miss cycles 125system.cpu.dcache.WriteReq_miss_latency::cpu.data 4455000 # number of WriteReq miss cycles 126system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles 127system.cpu.dcache.demand_miss_latency::cpu.data 7383000 # number of demand (read+write) miss cycles 128system.cpu.dcache.demand_miss_latency::total 7383000 # number of demand (read+write) miss cycles 129system.cpu.dcache.overall_miss_latency::cpu.data 7383000 # number of overall miss cycles 130system.cpu.dcache.overall_miss_latency::total 7383000 # number of overall miss cycles 131system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) 132system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) 133system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) 134system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) 135system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses 136system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses 137system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses 138system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses 139system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075524 # miss rate for ReadReq accesses 140system.cpu.dcache.ReadReq_miss_rate::total 0.075524 # miss rate for ReadReq accesses 141system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses 142system.cpu.dcache.WriteReq_miss_rate::total 0.120357 # miss rate for WriteReq accesses 143system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 # miss rate for demand accesses 144system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses 145system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses 146system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses 147system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54222.222222 # average ReadReq miss latency 148system.cpu.dcache.ReadReq_avg_miss_latency::total 54222.222222 # average ReadReq miss latency 149system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency 150system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency 151system.cpu.dcache.demand_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency 152system.cpu.dcache.demand_avg_miss_latency::total 54688.888889 # average overall miss latency 153system.cpu.dcache.overall_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency 154system.cpu.dcache.overall_avg_miss_latency::total 54688.888889 # average overall miss latency 155system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 156system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 157system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 158system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 159system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 160system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 161system.cpu.dcache.fast_writes 0 # number of fast writes performed 162system.cpu.dcache.cache_copies 0 # number of cache copies performed 163system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses 164system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses 165system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses 166system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses 167system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses 168system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses 169system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses 170system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses 171system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2874000 # number of ReadReq MSHR miss cycles 172system.cpu.dcache.ReadReq_mshr_miss_latency::total 2874000 # number of ReadReq MSHR miss cycles 173system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4374000 # number of WriteReq MSHR miss cycles 174system.cpu.dcache.WriteReq_mshr_miss_latency::total 4374000 # number of WriteReq MSHR miss cycles 175system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7248000 # number of demand (read+write) MSHR miss cycles 176system.cpu.dcache.demand_mshr_miss_latency::total 7248000 # number of demand (read+write) MSHR miss cycles 177system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7248000 # number of overall MSHR miss cycles 178system.cpu.dcache.overall_mshr_miss_latency::total 7248000 # number of overall MSHR miss cycles 179system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses 180system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses 181system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses 182system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses 183system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses 184system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses 185system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses 186system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses 187system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53222.222222 # average ReadReq mshr miss latency 188system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53222.222222 # average ReadReq mshr miss latency 189system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency 190system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency 191system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53688.888889 # average overall mshr miss latency 192system.cpu.dcache.demand_avg_mshr_miss_latency::total 53688.888889 # average overall mshr miss latency 193system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53688.888889 # average overall mshr miss latency 194system.cpu.dcache.overall_avg_mshr_miss_latency::total 53688.888889 # average overall mshr miss latency 195system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 196system.cpu.icache.tags.replacements 0 # number of replacements 197system.cpu.icache.tags.tagsinuse 117.032289 # Cycle average of tags in use 198system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks. 199system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks. 200system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks. 201system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 202system.cpu.icache.tags.occ_blocks::cpu.inst 117.032289 # Average occupied blocks per requestor 203system.cpu.icache.tags.occ_percent::cpu.inst 0.057145 # Average percentage of cache occupancy 204system.cpu.icache.tags.occ_percent::total 0.057145 # Average percentage of cache occupancy 205system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id 206system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id 207system.cpu.icache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id 208system.cpu.icache.tags.occ_task_id_percent::1024 0.125488 # Percentage of cache occupancy per task id 209system.cpu.icache.tags.tag_accesses 10999 # Number of tag accesses 210system.cpu.icache.tags.data_accesses 10999 # Number of data accesses 211system.cpu.icache.ReadReq_hits::cpu.inst 5114 # number of ReadReq hits 212system.cpu.icache.ReadReq_hits::total 5114 # number of ReadReq hits 213system.cpu.icache.demand_hits::cpu.inst 5114 # number of demand (read+write) hits 214system.cpu.icache.demand_hits::total 5114 # number of demand (read+write) hits 215system.cpu.icache.overall_hits::cpu.inst 5114 # number of overall hits 216system.cpu.icache.overall_hits::total 5114 # number of overall hits 217system.cpu.icache.ReadReq_misses::cpu.inst 257 # number of ReadReq misses 218system.cpu.icache.ReadReq_misses::total 257 # number of ReadReq misses 219system.cpu.icache.demand_misses::cpu.inst 257 # number of demand (read+write) misses 220system.cpu.icache.demand_misses::total 257 # number of demand (read+write) misses 221system.cpu.icache.overall_misses::cpu.inst 257 # number of overall misses 222system.cpu.icache.overall_misses::total 257 # number of overall misses 223system.cpu.icache.ReadReq_miss_latency::cpu.inst 14051500 # number of ReadReq miss cycles 224system.cpu.icache.ReadReq_miss_latency::total 14051500 # number of ReadReq miss cycles 225system.cpu.icache.demand_miss_latency::cpu.inst 14051500 # number of demand (read+write) miss cycles 226system.cpu.icache.demand_miss_latency::total 14051500 # number of demand (read+write) miss cycles 227system.cpu.icache.overall_miss_latency::cpu.inst 14051500 # number of overall miss cycles 228system.cpu.icache.overall_miss_latency::total 14051500 # number of overall miss cycles 229system.cpu.icache.ReadReq_accesses::cpu.inst 5371 # number of ReadReq accesses(hits+misses) 230system.cpu.icache.ReadReq_accesses::total 5371 # number of ReadReq accesses(hits+misses) 231system.cpu.icache.demand_accesses::cpu.inst 5371 # number of demand (read+write) accesses 232system.cpu.icache.demand_accesses::total 5371 # number of demand (read+write) accesses 233system.cpu.icache.overall_accesses::cpu.inst 5371 # number of overall (read+write) accesses 234system.cpu.icache.overall_accesses::total 5371 # number of overall (read+write) accesses 235system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.047850 # miss rate for ReadReq accesses 236system.cpu.icache.ReadReq_miss_rate::total 0.047850 # miss rate for ReadReq accesses 237system.cpu.icache.demand_miss_rate::cpu.inst 0.047850 # miss rate for demand accesses 238system.cpu.icache.demand_miss_rate::total 0.047850 # miss rate for demand accesses 239system.cpu.icache.overall_miss_rate::cpu.inst 0.047850 # miss rate for overall accesses 240system.cpu.icache.overall_miss_rate::total 0.047850 # miss rate for overall accesses 241system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54675.097276 # average ReadReq miss latency 242system.cpu.icache.ReadReq_avg_miss_latency::total 54675.097276 # average ReadReq miss latency 243system.cpu.icache.demand_avg_miss_latency::cpu.inst 54675.097276 # average overall miss latency 244system.cpu.icache.demand_avg_miss_latency::total 54675.097276 # average overall miss latency 245system.cpu.icache.overall_avg_miss_latency::cpu.inst 54675.097276 # average overall miss latency 246system.cpu.icache.overall_avg_miss_latency::total 54675.097276 # average overall miss latency 247system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 248system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 249system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 250system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 251system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 252system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 253system.cpu.icache.fast_writes 0 # number of fast writes performed 254system.cpu.icache.cache_copies 0 # number of cache copies performed 255system.cpu.icache.ReadReq_mshr_misses::cpu.inst 257 # number of ReadReq MSHR misses 256system.cpu.icache.ReadReq_mshr_misses::total 257 # number of ReadReq MSHR misses 257system.cpu.icache.demand_mshr_misses::cpu.inst 257 # number of demand (read+write) MSHR misses 258system.cpu.icache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses 259system.cpu.icache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses 260system.cpu.icache.overall_mshr_misses::total 257 # number of overall MSHR misses 261system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13794500 # number of ReadReq MSHR miss cycles 262system.cpu.icache.ReadReq_mshr_miss_latency::total 13794500 # number of ReadReq MSHR miss cycles 263system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13794500 # number of demand (read+write) MSHR miss cycles 264system.cpu.icache.demand_mshr_miss_latency::total 13794500 # number of demand (read+write) MSHR miss cycles 265system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13794500 # number of overall MSHR miss cycles 266system.cpu.icache.overall_mshr_miss_latency::total 13794500 # number of overall MSHR miss cycles 267system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for ReadReq accesses 268system.cpu.icache.ReadReq_mshr_miss_rate::total 0.047850 # mshr miss rate for ReadReq accesses 269system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for demand accesses 270system.cpu.icache.demand_mshr_miss_rate::total 0.047850 # mshr miss rate for demand accesses 271system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for overall accesses 272system.cpu.icache.overall_mshr_miss_rate::total 0.047850 # mshr miss rate for overall accesses 273system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53675.097276 # average ReadReq mshr miss latency 274system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53675.097276 # average ReadReq mshr miss latency 275system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53675.097276 # average overall mshr miss latency 276system.cpu.icache.demand_avg_mshr_miss_latency::total 53675.097276 # average overall mshr miss latency 277system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53675.097276 # average overall mshr miss latency 278system.cpu.icache.overall_avg_mshr_miss_latency::total 53675.097276 # average overall mshr miss latency 279system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 280system.cpu.l2cache.tags.replacements 0 # number of replacements 281system.cpu.l2cache.tags.tagsinuse 142.153744 # Cycle average of tags in use 282system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. 283system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. 284system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks. 285system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 286system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.494223 # Average occupied blocks per requestor 287system.cpu.l2cache.tags.occ_blocks::cpu.data 25.659521 # Average occupied blocks per requestor 288system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003555 # Average percentage of cache occupancy 289system.cpu.l2cache.tags.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy 290system.cpu.l2cache.tags.occ_percent::total 0.004338 # Average percentage of cache occupancy 291system.cpu.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id 292system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id 293system.cpu.l2cache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id 294system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009399 # Percentage of cache occupancy per task id 295system.cpu.l2cache.tags.tag_accesses 3525 # Number of tag accesses 296system.cpu.l2cache.tags.data_accesses 3525 # Number of data accesses 297system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits 298system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits 299system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits 300system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits 301system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 302system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits 303system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 304system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 305system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits 306system.cpu.l2cache.overall_hits::total 3 # number of overall hits 307system.cpu.l2cache.ReadExReq_misses::cpu.data 81 # number of ReadExReq misses 308system.cpu.l2cache.ReadExReq_misses::total 81 # number of ReadExReq misses 309system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 255 # number of ReadCleanReq misses 310system.cpu.l2cache.ReadCleanReq_misses::total 255 # number of ReadCleanReq misses 311system.cpu.l2cache.ReadSharedReq_misses::cpu.data 53 # number of ReadSharedReq misses 312system.cpu.l2cache.ReadSharedReq_misses::total 53 # number of ReadSharedReq misses 313system.cpu.l2cache.demand_misses::cpu.inst 255 # number of demand (read+write) misses 314system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses 315system.cpu.l2cache.demand_misses::total 389 # number of demand (read+write) misses 316system.cpu.l2cache.overall_misses::cpu.inst 255 # number of overall misses 317system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses 318system.cpu.l2cache.overall_misses::total 389 # number of overall misses 319system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4252500 # number of ReadExReq miss cycles 320system.cpu.l2cache.ReadExReq_miss_latency::total 4252500 # number of ReadExReq miss cycles 321system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13388000 # number of ReadCleanReq miss cycles 322system.cpu.l2cache.ReadCleanReq_miss_latency::total 13388000 # number of ReadCleanReq miss cycles 323system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2782500 # number of ReadSharedReq miss cycles 324system.cpu.l2cache.ReadSharedReq_miss_latency::total 2782500 # number of ReadSharedReq miss cycles 325system.cpu.l2cache.demand_miss_latency::cpu.inst 13388000 # number of demand (read+write) miss cycles 326system.cpu.l2cache.demand_miss_latency::cpu.data 7035000 # number of demand (read+write) miss cycles 327system.cpu.l2cache.demand_miss_latency::total 20423000 # number of demand (read+write) miss cycles 328system.cpu.l2cache.overall_miss_latency::cpu.inst 13388000 # number of overall miss cycles 329system.cpu.l2cache.overall_miss_latency::cpu.data 7035000 # number of overall miss cycles 330system.cpu.l2cache.overall_miss_latency::total 20423000 # number of overall miss cycles 331system.cpu.l2cache.ReadExReq_accesses::cpu.data 81 # number of ReadExReq accesses(hits+misses) 332system.cpu.l2cache.ReadExReq_accesses::total 81 # number of ReadExReq accesses(hits+misses) 333system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 257 # number of ReadCleanReq accesses(hits+misses) 334system.cpu.l2cache.ReadCleanReq_accesses::total 257 # number of ReadCleanReq accesses(hits+misses) 335system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 54 # number of ReadSharedReq accesses(hits+misses) 336system.cpu.l2cache.ReadSharedReq_accesses::total 54 # number of ReadSharedReq accesses(hits+misses) 337system.cpu.l2cache.demand_accesses::cpu.inst 257 # number of demand (read+write) accesses 338system.cpu.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses 339system.cpu.l2cache.demand_accesses::total 392 # number of demand (read+write) accesses 340system.cpu.l2cache.overall_accesses::cpu.inst 257 # number of overall (read+write) accesses 341system.cpu.l2cache.overall_accesses::cpu.data 135 # number of overall (read+write) accesses 342system.cpu.l2cache.overall_accesses::total 392 # number of overall (read+write) accesses 343system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 344system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 345system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.992218 # miss rate for ReadCleanReq accesses 346system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.992218 # miss rate for ReadCleanReq accesses 347system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.981481 # miss rate for ReadSharedReq accesses 348system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.981481 # miss rate for ReadSharedReq accesses 349system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992218 # miss rate for demand accesses 350system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses 351system.cpu.l2cache.demand_miss_rate::total 0.992347 # miss rate for demand accesses 352system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992218 # miss rate for overall accesses 353system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses 354system.cpu.l2cache.overall_miss_rate::total 0.992347 # miss rate for overall accesses 355system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency 356system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency 357system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52501.960784 # average ReadCleanReq miss latency 358system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52501.960784 # average ReadCleanReq miss latency 359system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency 360system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency 361system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.960784 # average overall miss latency 362system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency 363system.cpu.l2cache.demand_avg_miss_latency::total 52501.285347 # average overall miss latency 364system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.960784 # average overall miss latency 365system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency 366system.cpu.l2cache.overall_avg_miss_latency::total 52501.285347 # average overall miss latency 367system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 368system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 369system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 370system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 371system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 372system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 373system.cpu.l2cache.fast_writes 0 # number of fast writes performed 374system.cpu.l2cache.cache_copies 0 # number of cache copies performed 375system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 81 # number of ReadExReq MSHR misses 376system.cpu.l2cache.ReadExReq_mshr_misses::total 81 # number of ReadExReq MSHR misses 377system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 255 # number of ReadCleanReq MSHR misses 378system.cpu.l2cache.ReadCleanReq_mshr_misses::total 255 # number of ReadCleanReq MSHR misses 379system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 53 # number of ReadSharedReq MSHR misses 380system.cpu.l2cache.ReadSharedReq_mshr_misses::total 53 # number of ReadSharedReq MSHR misses 381system.cpu.l2cache.demand_mshr_misses::cpu.inst 255 # number of demand (read+write) MSHR misses 382system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses 383system.cpu.l2cache.demand_mshr_misses::total 389 # number of demand (read+write) MSHR misses 384system.cpu.l2cache.overall_mshr_misses::cpu.inst 255 # number of overall MSHR misses 385system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses 386system.cpu.l2cache.overall_mshr_misses::total 389 # number of overall MSHR misses 387system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3442500 # number of ReadExReq MSHR miss cycles 388system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3442500 # number of ReadExReq MSHR miss cycles 389system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10838000 # number of ReadCleanReq MSHR miss cycles 390system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10838000 # number of ReadCleanReq MSHR miss cycles 391system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2252500 # number of ReadSharedReq MSHR miss cycles 392system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2252500 # number of ReadSharedReq MSHR miss cycles 393system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10838000 # number of demand (read+write) MSHR miss cycles 394system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5695000 # number of demand (read+write) MSHR miss cycles 395system.cpu.l2cache.demand_mshr_miss_latency::total 16533000 # number of demand (read+write) MSHR miss cycles 396system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10838000 # number of overall MSHR miss cycles 397system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5695000 # number of overall MSHR miss cycles 398system.cpu.l2cache.overall_mshr_miss_latency::total 16533000 # number of overall MSHR miss cycles 399system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 400system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 401system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for ReadCleanReq accesses 402system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.992218 # mshr miss rate for ReadCleanReq accesses 403system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadSharedReq accesses 404system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.981481 # mshr miss rate for ReadSharedReq accesses 405system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for demand accesses 406system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses 407system.cpu.l2cache.demand_mshr_miss_rate::total 0.992347 # mshr miss rate for demand accesses 408system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for overall accesses 409system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses 410system.cpu.l2cache.overall_mshr_miss_rate::total 0.992347 # mshr miss rate for overall accesses 411system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency 412system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency 413system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42501.960784 # average ReadCleanReq mshr miss latency 414system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42501.960784 # average ReadCleanReq mshr miss latency 415system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency 416system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency 417system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.960784 # average overall mshr miss latency 418system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency 419system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.285347 # average overall mshr miss latency 420system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.960784 # average overall mshr miss latency 421system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency 422system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.285347 # average overall mshr miss latency 423system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 424system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution 425system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution 426system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution 427system.cpu.toL2Bus.trans_dist::ReadCleanReq 257 # Transaction distribution 428system.cpu.toL2Bus.trans_dist::ReadSharedReq 54 # Transaction distribution 429system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 514 # Packet count per connected master and slave (bytes) 430system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) 431system.cpu.toL2Bus.pkt_count::total 784 # Packet count per connected master and slave (bytes) 432system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16448 # Cumulative packet size per connected master and slave (bytes) 433system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) 434system.cpu.toL2Bus.pkt_size::total 25088 # Cumulative packet size per connected master and slave (bytes) 435system.cpu.toL2Bus.snoops 0 # Total snoops (count) 436system.cpu.toL2Bus.snoop_fanout::samples 392 # Request fanout histogram 437system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 438system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 439system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 440system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 441system.cpu.toL2Bus.snoop_fanout::1 392 100.00% 100.00% # Request fanout histogram 442system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 443system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 444system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 445system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 446system.cpu.toL2Bus.snoop_fanout::total 392 # Request fanout histogram 447system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks) 448system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 449system.cpu.toL2Bus.respLayer0.occupancy 385500 # Layer occupancy (ticks) 450system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) 451system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks) 452system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) 453system.membus.trans_dist::ReadResp 308 # Transaction distribution 454system.membus.trans_dist::ReadExReq 81 # Transaction distribution 455system.membus.trans_dist::ReadExResp 81 # Transaction distribution 456system.membus.trans_dist::ReadSharedReq 308 # Transaction distribution 457system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes) 458system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes) 459system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes) 460system.membus.pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes) 461system.membus.snoops 0 # Total snoops (count) 462system.membus.snoop_fanout::samples 389 # Request fanout histogram 463system.membus.snoop_fanout::mean 0 # Request fanout histogram 464system.membus.snoop_fanout::stdev 0 # Request fanout histogram 465system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 466system.membus.snoop_fanout::0 389 100.00% 100.00% # Request fanout histogram 467system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 468system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 469system.membus.snoop_fanout::min_value 0 # Request fanout histogram 470system.membus.snoop_fanout::max_value 0 # Request fanout histogram 471system.membus.snoop_fanout::total 389 # Request fanout histogram 472system.membus.reqLayer0.occupancy 389500 # Layer occupancy (ticks) 473system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) 474system.membus.respLayer1.occupancy 1945500 # Layer occupancy (ticks) 475system.membus.respLayer1.utilization 7.0 # Layer utilization (%) 476 477---------- End Simulation Statistics ---------- 478