stats.txt revision 12062
111731Sjason@lowepower.com 211731Sjason@lowepower.com---------- Begin Simulation Statistics ---------- 312062Sar4jc@virginia.edusim_seconds 0.000003 412062Sar4jc@virginia.edusim_ticks 2783000 512062Sar4jc@virginia.edufinal_tick 2783000 612062Sar4jc@virginia.edusim_freq 1000000000000 712062Sar4jc@virginia.eduhost_inst_rate 86590 812062Sar4jc@virginia.eduhost_op_rate 86699 912062Sar4jc@virginia.eduhost_tick_rate 43405073 1012062Sar4jc@virginia.eduhost_mem_usage 264628 1112062Sar4jc@virginia.eduhost_seconds 0.06 1212062Sar4jc@virginia.edusim_insts 5550 1312062Sar4jc@virginia.edusim_ops 5558 1412062Sar4jc@virginia.edusystem.voltage_domain.voltage 1 1512062Sar4jc@virginia.edusystem.clk_domain.clock 1000 1612062Sar4jc@virginia.edusystem.physmem.pwrStateResidencyTicks::UNDEFINED 2783000 1712062Sar4jc@virginia.edusystem.physmem.bytes_read::cpu.inst 22236 1812062Sar4jc@virginia.edusystem.physmem.bytes_read::cpu.data 7346 1912062Sar4jc@virginia.edusystem.physmem.bytes_read::total 29582 2012062Sar4jc@virginia.edusystem.physmem.bytes_inst_read::cpu.inst 22236 2112062Sar4jc@virginia.edusystem.physmem.bytes_inst_read::total 22236 2212062Sar4jc@virginia.edusystem.physmem.bytes_written::cpu.data 8138 2312062Sar4jc@virginia.edusystem.physmem.bytes_written::total 8138 2412062Sar4jc@virginia.edusystem.physmem.num_reads::cpu.inst 5559 2512062Sar4jc@virginia.edusystem.physmem.num_reads::cpu.data 1101 2612062Sar4jc@virginia.edusystem.physmem.num_reads::total 6660 2712062Sar4jc@virginia.edusystem.physmem.num_writes::cpu.data 1097 2812062Sar4jc@virginia.edusystem.physmem.num_writes::total 1097 2912062Sar4jc@virginia.edusystem.physmem.bw_read::cpu.inst 7989938915 3012062Sar4jc@virginia.edusystem.physmem.bw_read::cpu.data 2639597557 3112062Sar4jc@virginia.edusystem.physmem.bw_read::total 10629536471 3212062Sar4jc@virginia.edusystem.physmem.bw_inst_read::cpu.inst 7989938915 3312062Sar4jc@virginia.edusystem.physmem.bw_inst_read::total 7989938915 3412062Sar4jc@virginia.edusystem.physmem.bw_write::cpu.data 2924182537 3512062Sar4jc@virginia.edusystem.physmem.bw_write::total 2924182537 3612062Sar4jc@virginia.edusystem.physmem.bw_total::cpu.inst 7989938915 3712062Sar4jc@virginia.edusystem.physmem.bw_total::cpu.data 5563780093 3812062Sar4jc@virginia.edusystem.physmem.bw_total::total 13553719008 3912062Sar4jc@virginia.edusystem.pwrStateResidencyTicks::UNDEFINED 2783000 4012062Sar4jc@virginia.edusystem.cpu_clk_domain.clock 500 4112062Sar4jc@virginia.edusystem.cpu.dtb.read_hits 0 4212062Sar4jc@virginia.edusystem.cpu.dtb.read_misses 0 4312062Sar4jc@virginia.edusystem.cpu.dtb.read_accesses 0 4412062Sar4jc@virginia.edusystem.cpu.dtb.write_hits 0 4512062Sar4jc@virginia.edusystem.cpu.dtb.write_misses 0 4612062Sar4jc@virginia.edusystem.cpu.dtb.write_accesses 0 4712062Sar4jc@virginia.edusystem.cpu.dtb.hits 0 4812062Sar4jc@virginia.edusystem.cpu.dtb.misses 0 4912062Sar4jc@virginia.edusystem.cpu.dtb.accesses 0 5012062Sar4jc@virginia.edusystem.cpu.itb.read_hits 0 5112062Sar4jc@virginia.edusystem.cpu.itb.read_misses 0 5212062Sar4jc@virginia.edusystem.cpu.itb.read_accesses 0 5312062Sar4jc@virginia.edusystem.cpu.itb.write_hits 0 5412062Sar4jc@virginia.edusystem.cpu.itb.write_misses 0 5512062Sar4jc@virginia.edusystem.cpu.itb.write_accesses 0 5612062Sar4jc@virginia.edusystem.cpu.itb.hits 0 5712062Sar4jc@virginia.edusystem.cpu.itb.misses 0 5812062Sar4jc@virginia.edusystem.cpu.itb.accesses 0 5912062Sar4jc@virginia.edusystem.cpu.workload.numSyscalls 9 6012062Sar4jc@virginia.edusystem.cpu.pwrStateResidencyTicks::ON 2783000 6112062Sar4jc@virginia.edusystem.cpu.numCycles 5567 6212062Sar4jc@virginia.edusystem.cpu.numWorkItemsStarted 0 6312062Sar4jc@virginia.edusystem.cpu.numWorkItemsCompleted 0 6412062Sar4jc@virginia.edusystem.cpu.committedInsts 5550 6512062Sar4jc@virginia.edusystem.cpu.committedOps 5558 6612062Sar4jc@virginia.edusystem.cpu.num_int_alu_accesses 5557 6712062Sar4jc@virginia.edusystem.cpu.num_fp_alu_accesses 12 6812062Sar4jc@virginia.edusystem.cpu.num_func_calls 291 6912062Sar4jc@virginia.edusystem.cpu.num_conditional_control_insts 914 7012062Sar4jc@virginia.edusystem.cpu.num_int_insts 5557 7112062Sar4jc@virginia.edusystem.cpu.num_fp_insts 12 7212062Sar4jc@virginia.edusystem.cpu.num_int_register_reads 7540 7312062Sar4jc@virginia.edusystem.cpu.num_int_register_writes 3562 7412062Sar4jc@virginia.edusystem.cpu.num_fp_register_reads 12 7512062Sar4jc@virginia.edusystem.cpu.num_fp_register_writes 0 7612062Sar4jc@virginia.edusystem.cpu.num_mem_refs 2198 7712062Sar4jc@virginia.edusystem.cpu.num_load_insts 1101 7812062Sar4jc@virginia.edusystem.cpu.num_store_insts 1097 7912062Sar4jc@virginia.edusystem.cpu.num_idle_cycles 0 8012062Sar4jc@virginia.edusystem.cpu.num_busy_cycles 5567 8112062Sar4jc@virginia.edusystem.cpu.not_idle_fraction 1 8212062Sar4jc@virginia.edusystem.cpu.idle_fraction 0 8312062Sar4jc@virginia.edusystem.cpu.Branches 1205 8412062Sar4jc@virginia.edusystem.cpu.op_class::No_OpClass 10 0.18% 0.18% 8512062Sar4jc@virginia.edusystem.cpu.op_class::IntAlu 3353 60.23% 60.41% 8612062Sar4jc@virginia.edusystem.cpu.op_class::IntMult 2 0.04% 60.45% 8712062Sar4jc@virginia.edusystem.cpu.op_class::IntDiv 4 0.07% 60.52% 8812062Sar4jc@virginia.edusystem.cpu.op_class::FloatAdd 0 0.00% 60.52% 8912062Sar4jc@virginia.edusystem.cpu.op_class::FloatCmp 0 0.00% 60.52% 9012062Sar4jc@virginia.edusystem.cpu.op_class::FloatCvt 0 0.00% 60.52% 9112062Sar4jc@virginia.edusystem.cpu.op_class::FloatMult 0 0.00% 60.52% 9212062Sar4jc@virginia.edusystem.cpu.op_class::FloatMultAcc 0 0.00% 60.52% 9312062Sar4jc@virginia.edusystem.cpu.op_class::FloatDiv 0 0.00% 60.52% 9412062Sar4jc@virginia.edusystem.cpu.op_class::FloatMisc 0 0.00% 60.52% 9512062Sar4jc@virginia.edusystem.cpu.op_class::FloatSqrt 0 0.00% 60.52% 9612062Sar4jc@virginia.edusystem.cpu.op_class::SimdAdd 0 0.00% 60.52% 9712062Sar4jc@virginia.edusystem.cpu.op_class::SimdAddAcc 0 0.00% 60.52% 9812062Sar4jc@virginia.edusystem.cpu.op_class::SimdAlu 0 0.00% 60.52% 9912062Sar4jc@virginia.edusystem.cpu.op_class::SimdCmp 0 0.00% 60.52% 10012062Sar4jc@virginia.edusystem.cpu.op_class::SimdCvt 0 0.00% 60.52% 10112062Sar4jc@virginia.edusystem.cpu.op_class::SimdMisc 0 0.00% 60.52% 10212062Sar4jc@virginia.edusystem.cpu.op_class::SimdMult 0 0.00% 60.52% 10312062Sar4jc@virginia.edusystem.cpu.op_class::SimdMultAcc 0 0.00% 60.52% 10412062Sar4jc@virginia.edusystem.cpu.op_class::SimdShift 0 0.00% 60.52% 10512062Sar4jc@virginia.edusystem.cpu.op_class::SimdShiftAcc 0 0.00% 60.52% 10612062Sar4jc@virginia.edusystem.cpu.op_class::SimdSqrt 0 0.00% 60.52% 10712062Sar4jc@virginia.edusystem.cpu.op_class::SimdFloatAdd 0 0.00% 60.52% 10812062Sar4jc@virginia.edusystem.cpu.op_class::SimdFloatAlu 0 0.00% 60.52% 10912062Sar4jc@virginia.edusystem.cpu.op_class::SimdFloatCmp 0 0.00% 60.52% 11012062Sar4jc@virginia.edusystem.cpu.op_class::SimdFloatCvt 0 0.00% 60.52% 11112062Sar4jc@virginia.edusystem.cpu.op_class::SimdFloatDiv 0 0.00% 60.52% 11212062Sar4jc@virginia.edusystem.cpu.op_class::SimdFloatMisc 0 0.00% 60.52% 11312062Sar4jc@virginia.edusystem.cpu.op_class::SimdFloatMult 0 0.00% 60.52% 11412062Sar4jc@virginia.edusystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.52% 11512062Sar4jc@virginia.edusystem.cpu.op_class::SimdFloatSqrt 0 0.00% 60.52% 11612062Sar4jc@virginia.edusystem.cpu.op_class::MemRead 1101 19.78% 80.29% 11712062Sar4jc@virginia.edusystem.cpu.op_class::MemWrite 1085 19.49% 99.78% 11812062Sar4jc@virginia.edusystem.cpu.op_class::FloatMemRead 0 0.00% 99.78% 11912062Sar4jc@virginia.edusystem.cpu.op_class::FloatMemWrite 12 0.22% 100.00% 12012062Sar4jc@virginia.edusystem.cpu.op_class::IprAccess 0 0.00% 100.00% 12112062Sar4jc@virginia.edusystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% 12212062Sar4jc@virginia.edusystem.cpu.op_class::total 5567 12312062Sar4jc@virginia.edusystem.membus.snoop_filter.tot_requests 0 12412062Sar4jc@virginia.edusystem.membus.snoop_filter.hit_single_requests 0 12512062Sar4jc@virginia.edusystem.membus.snoop_filter.hit_multi_requests 0 12612062Sar4jc@virginia.edusystem.membus.snoop_filter.tot_snoops 0 12712062Sar4jc@virginia.edusystem.membus.snoop_filter.hit_single_snoops 0 12812062Sar4jc@virginia.edusystem.membus.snoop_filter.hit_multi_snoops 0 12912062Sar4jc@virginia.edusystem.membus.pwrStateResidencyTicks::UNDEFINED 2783000 13012062Sar4jc@virginia.edusystem.membus.trans_dist::ReadReq 6652 13112062Sar4jc@virginia.edusystem.membus.trans_dist::ReadResp 6660 13212062Sar4jc@virginia.edusystem.membus.trans_dist::WriteReq 1089 13312062Sar4jc@virginia.edusystem.membus.trans_dist::WriteResp 1089 13412062Sar4jc@virginia.edusystem.membus.trans_dist::LoadLockedReq 8 13512062Sar4jc@virginia.edusystem.membus.trans_dist::StoreCondReq 8 13612062Sar4jc@virginia.edusystem.membus.trans_dist::StoreCondResp 8 13712062Sar4jc@virginia.edusystem.membus.pkt_count_system.cpu.icache_port::system.physmem.port 11118 13812062Sar4jc@virginia.edusystem.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4396 13912062Sar4jc@virginia.edusystem.membus.pkt_count::total 15514 14012062Sar4jc@virginia.edusystem.membus.pkt_size_system.cpu.icache_port::system.physmem.port 22236 14112062Sar4jc@virginia.edusystem.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 15484 14212062Sar4jc@virginia.edusystem.membus.pkt_size::total 37720 14312062Sar4jc@virginia.edusystem.membus.snoops 0 14412062Sar4jc@virginia.edusystem.membus.snoopTraffic 0 14512062Sar4jc@virginia.edusystem.membus.snoop_fanout::samples 7757 14612062Sar4jc@virginia.edusystem.membus.snoop_fanout::mean 0 14712062Sar4jc@virginia.edusystem.membus.snoop_fanout::stdev 0 14812062Sar4jc@virginia.edusystem.membus.snoop_fanout::underflows 0 0.00% 0.00% 14912062Sar4jc@virginia.edusystem.membus.snoop_fanout::0 7757 100.00% 100.00% 15012062Sar4jc@virginia.edusystem.membus.snoop_fanout::1 0 0.00% 100.00% 15112062Sar4jc@virginia.edusystem.membus.snoop_fanout::overflows 0 0.00% 100.00% 15212062Sar4jc@virginia.edusystem.membus.snoop_fanout::min_value 0 15312062Sar4jc@virginia.edusystem.membus.snoop_fanout::max_value 0 15412062Sar4jc@virginia.edusystem.membus.snoop_fanout::total 7757 15511731Sjason@lowepower.com 15611731Sjason@lowepower.com---------- End Simulation Statistics ---------- 157