simout revision 11731
111731Sjason@lowepower.comRedirecting stdout to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/o3-timing/simout 211731Sjason@lowepower.comRedirecting stderr to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/o3-timing/simerr 311731Sjason@lowepower.comgem5 Simulator System. http://gem5.org 411731Sjason@lowepower.comgem5 is copyrighted software; use the --copyright option for details. 511731Sjason@lowepower.com 611731Sjason@lowepower.comgem5 compiled Nov 30 2016 14:33:35 711731Sjason@lowepower.comgem5 started Nov 30 2016 16:18:28 811731Sjason@lowepower.comgem5 executing on zizzer, pid 34057 911731Sjason@lowepower.comcommand line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/riscv/linux/o3-timing 1011731Sjason@lowepower.com 1111731Sjason@lowepower.comGlobal frequency set at 1000000000000 ticks per second 1211731Sjason@lowepower.cominfo: Entering event queue @ 0. Starting simulation... 1311731Sjason@lowepower.cominfo: Increasing stack size by one page. 1411731Sjason@lowepower.comHello world! 1511731Sjason@lowepower.comExiting @ tick 7939500 because target called exit() 16