config.json revision 11731
1{ 2 "name": null, 3 "sim_quantum": 0, 4 "system": { 5 "kernel": "", 6 "mmap_using_noreserve": false, 7 "kernel_addr_check": true, 8 "membus": { 9 "point_of_coherency": true, 10 "system": "system", 11 "response_latency": 2, 12 "cxx_class": "CoherentXBar", 13 "forward_latency": 4, 14 "clk_domain": "system.clk_domain", 15 "width": 16, 16 "eventq_index": 0, 17 "default_p_state": "UNDEFINED", 18 "p_state_clk_gate_max": 1000000000000, 19 "master": { 20 "peer": [ 21 "system.physmem.port" 22 ], 23 "role": "MASTER" 24 }, 25 "type": "CoherentXBar", 26 "frontend_latency": 3, 27 "slave": { 28 "peer": [ 29 "system.system_port", 30 "system.cpu.l2cache.mem_side" 31 ], 32 "role": "SLAVE" 33 }, 34 "p_state_clk_gate_min": 1000, 35 "snoop_filter": { 36 "name": "snoop_filter", 37 "system": "system", 38 "max_capacity": 8388608, 39 "eventq_index": 0, 40 "cxx_class": "SnoopFilter", 41 "path": "system.membus.snoop_filter", 42 "type": "SnoopFilter", 43 "lookup_latency": 1 44 }, 45 "power_model": null, 46 "path": "system.membus", 47 "snoop_response_latency": 4, 48 "name": "membus", 49 "p_state_clk_gate_bins": 20, 50 "use_default_range": false 51 }, 52 "symbolfile": "", 53 "readfile": "", 54 "thermal_model": null, 55 "cxx_class": "System", 56 "work_begin_cpu_id_exit": -1, 57 "load_offset": 0, 58 "work_begin_exit_count": 0, 59 "p_state_clk_gate_min": 1000, 60 "memories": [ 61 "system.physmem" 62 ], 63 "work_begin_ckpt_count": 0, 64 "clk_domain": { 65 "name": "clk_domain", 66 "clock": [ 67 1000 68 ], 69 "init_perf_level": 0, 70 "voltage_domain": "system.voltage_domain", 71 "eventq_index": 0, 72 "cxx_class": "SrcClockDomain", 73 "path": "system.clk_domain", 74 "type": "SrcClockDomain", 75 "domain_id": -1 76 }, 77 "mem_ranges": [], 78 "eventq_index": 0, 79 "default_p_state": "UNDEFINED", 80 "p_state_clk_gate_max": 1000000000000, 81 "dvfs_handler": { 82 "enable": false, 83 "name": "dvfs_handler", 84 "sys_clk_domain": "system.clk_domain", 85 "transition_latency": 100000000, 86 "eventq_index": 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