stats.txt revision 11731
111731Sjason@lowepower.com 211731Sjason@lowepower.com---------- Begin Simulation Statistics ---------- 311731Sjason@lowepower.comsim_seconds 0.000014 # Number of seconds simulated 411731Sjason@lowepower.comsim_ticks 14435000 # Number of ticks simulated 511731Sjason@lowepower.comfinal_tick 14435000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611731Sjason@lowepower.comsim_freq 1000000000000 # Frequency of simulated ticks 711731Sjason@lowepower.comhost_inst_rate 13240 # Simulator instruction rate (inst/s) 811731Sjason@lowepower.comhost_op_rate 13237 # Simulator op (including micro ops) rate (op/s) 911731Sjason@lowepower.comhost_tick_rate 119615611 # Simulator tick rate (ticks/s) 1011731Sjason@lowepower.comhost_mem_usage 232036 # Number of bytes of host memory used 1111731Sjason@lowepower.comhost_seconds 0.12 # Real time elapsed on the host 1211731Sjason@lowepower.comsim_insts 1597 # Number of instructions simulated 1311731Sjason@lowepower.comsim_ops 1597 # Number of ops (including micro ops) simulated 1411731Sjason@lowepower.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511731Sjason@lowepower.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611731Sjason@lowepower.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states 1711731Sjason@lowepower.comsystem.physmem.bytes_read::cpu.inst 9984 # Number of bytes read from this memory 1811731Sjason@lowepower.comsystem.physmem.bytes_read::cpu.data 2048 # Number of bytes read from this memory 1911731Sjason@lowepower.comsystem.physmem.bytes_read::total 12032 # Number of bytes read from this memory 2011731Sjason@lowepower.comsystem.physmem.bytes_inst_read::cpu.inst 9984 # Number of instructions bytes read from this memory 2111731Sjason@lowepower.comsystem.physmem.bytes_inst_read::total 9984 # Number of instructions bytes read from this memory 2211731Sjason@lowepower.comsystem.physmem.num_reads::cpu.inst 156 # Number of read requests responded to by this memory 2311731Sjason@lowepower.comsystem.physmem.num_reads::cpu.data 32 # Number of read requests responded to by this memory 2411731Sjason@lowepower.comsystem.physmem.num_reads::total 188 # Number of read requests responded to by this memory 2511731Sjason@lowepower.comsystem.physmem.bw_read::cpu.inst 691652234 # Total read bandwidth from this memory (bytes/s) 2611731Sjason@lowepower.comsystem.physmem.bw_read::cpu.data 141877381 # Total read bandwidth from this memory (bytes/s) 2711731Sjason@lowepower.comsystem.physmem.bw_read::total 833529616 # Total read bandwidth from this memory (bytes/s) 2811731Sjason@lowepower.comsystem.physmem.bw_inst_read::cpu.inst 691652234 # Instruction read bandwidth from this memory (bytes/s) 2911731Sjason@lowepower.comsystem.physmem.bw_inst_read::total 691652234 # Instruction read bandwidth from this memory (bytes/s) 3011731Sjason@lowepower.comsystem.physmem.bw_total::cpu.inst 691652234 # Total bandwidth to/from this memory (bytes/s) 3111731Sjason@lowepower.comsystem.physmem.bw_total::cpu.data 141877381 # Total bandwidth to/from this memory (bytes/s) 3211731Sjason@lowepower.comsystem.physmem.bw_total::total 833529616 # Total bandwidth to/from this memory (bytes/s) 3311731Sjason@lowepower.comsystem.physmem.readReqs 188 # Number of read requests accepted 3411731Sjason@lowepower.comsystem.physmem.writeReqs 0 # Number of write requests accepted 3511731Sjason@lowepower.comsystem.physmem.readBursts 188 # Number of DRAM read bursts, including those serviced by the write queue 3611731Sjason@lowepower.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 3711731Sjason@lowepower.comsystem.physmem.bytesReadDRAM 12032 # Total number of bytes read from DRAM 3811731Sjason@lowepower.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 3911731Sjason@lowepower.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 4011731Sjason@lowepower.comsystem.physmem.bytesReadSys 12032 # Total read bytes from the system interface side 4111731Sjason@lowepower.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 4211731Sjason@lowepower.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 4311731Sjason@lowepower.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 4411731Sjason@lowepower.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 4511731Sjason@lowepower.comsystem.physmem.perBankRdBursts::0 97 # Per bank write bursts 4611731Sjason@lowepower.comsystem.physmem.perBankRdBursts::1 64 # Per bank write bursts 4711731Sjason@lowepower.comsystem.physmem.perBankRdBursts::2 18 # Per bank write bursts 4811731Sjason@lowepower.comsystem.physmem.perBankRdBursts::3 9 # Per bank write bursts 4911731Sjason@lowepower.comsystem.physmem.perBankRdBursts::4 0 # Per bank write bursts 5011731Sjason@lowepower.comsystem.physmem.perBankRdBursts::5 0 # Per bank write bursts 5111731Sjason@lowepower.comsystem.physmem.perBankRdBursts::6 0 # Per bank write bursts 5211731Sjason@lowepower.comsystem.physmem.perBankRdBursts::7 0 # Per bank write bursts 5311731Sjason@lowepower.comsystem.physmem.perBankRdBursts::8 0 # Per bank write bursts 5411731Sjason@lowepower.comsystem.physmem.perBankRdBursts::9 0 # Per bank write bursts 5511731Sjason@lowepower.comsystem.physmem.perBankRdBursts::10 0 # Per bank write bursts 5611731Sjason@lowepower.comsystem.physmem.perBankRdBursts::11 0 # Per bank write bursts 5711731Sjason@lowepower.comsystem.physmem.perBankRdBursts::12 0 # Per bank write bursts 5811731Sjason@lowepower.comsystem.physmem.perBankRdBursts::13 0 # Per bank write bursts 5911731Sjason@lowepower.comsystem.physmem.perBankRdBursts::14 0 # Per bank write bursts 6011731Sjason@lowepower.comsystem.physmem.perBankRdBursts::15 0 # Per bank write bursts 6111731Sjason@lowepower.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 6211731Sjason@lowepower.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 6311731Sjason@lowepower.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 6411731Sjason@lowepower.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 6511731Sjason@lowepower.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 6611731Sjason@lowepower.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 6711731Sjason@lowepower.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 6811731Sjason@lowepower.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 6911731Sjason@lowepower.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 7011731Sjason@lowepower.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 7111731Sjason@lowepower.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 7211731Sjason@lowepower.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 7311731Sjason@lowepower.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 7411731Sjason@lowepower.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 7511731Sjason@lowepower.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 7611731Sjason@lowepower.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 7711731Sjason@lowepower.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 7811731Sjason@lowepower.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 7911731Sjason@lowepower.comsystem.physmem.totGap 14206000 # Total gap between requests 8011731Sjason@lowepower.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 8111731Sjason@lowepower.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 8211731Sjason@lowepower.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 8311731Sjason@lowepower.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 8411731Sjason@lowepower.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 8511731Sjason@lowepower.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 8611731Sjason@lowepower.comsystem.physmem.readPktSize::6 188 # Read request sizes (log2) 8711731Sjason@lowepower.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 8811731Sjason@lowepower.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 8911731Sjason@lowepower.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 9011731Sjason@lowepower.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 9111731Sjason@lowepower.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 9211731Sjason@lowepower.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 9311731Sjason@lowepower.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9411731Sjason@lowepower.comsystem.physmem.rdQLenPdf::0 161 # What read queue length does an incoming req see 9511731Sjason@lowepower.comsystem.physmem.rdQLenPdf::1 25 # What read queue length does an incoming req see 9611731Sjason@lowepower.comsystem.physmem.rdQLenPdf::2 2 # What read queue length does an incoming req see 9711731Sjason@lowepower.comsystem.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 9811731Sjason@lowepower.comsystem.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 9911731Sjason@lowepower.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 10011731Sjason@lowepower.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 10111731Sjason@lowepower.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 10211731Sjason@lowepower.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 10311731Sjason@lowepower.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 10411731Sjason@lowepower.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 10511731Sjason@lowepower.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 10611731Sjason@lowepower.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 10711731Sjason@lowepower.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 10811731Sjason@lowepower.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 10911731Sjason@lowepower.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 11011731Sjason@lowepower.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 11111731Sjason@lowepower.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 11211731Sjason@lowepower.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 11311731Sjason@lowepower.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 11411731Sjason@lowepower.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 11511731Sjason@lowepower.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 11611731Sjason@lowepower.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 11711731Sjason@lowepower.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 11811731Sjason@lowepower.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 11911731Sjason@lowepower.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 12011731Sjason@lowepower.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 12111731Sjason@lowepower.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 12211731Sjason@lowepower.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 12311731Sjason@lowepower.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 12411731Sjason@lowepower.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 12511731Sjason@lowepower.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 12611731Sjason@lowepower.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 12711731Sjason@lowepower.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 12811731Sjason@lowepower.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 12911731Sjason@lowepower.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 13011731Sjason@lowepower.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 13111731Sjason@lowepower.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 13211731Sjason@lowepower.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 13311731Sjason@lowepower.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 13411731Sjason@lowepower.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 13511731Sjason@lowepower.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 13611731Sjason@lowepower.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 13711731Sjason@lowepower.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 13811731Sjason@lowepower.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 13911731Sjason@lowepower.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 14011731Sjason@lowepower.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 14111731Sjason@lowepower.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 14211731Sjason@lowepower.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 14311731Sjason@lowepower.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 14411731Sjason@lowepower.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 14511731Sjason@lowepower.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 14611731Sjason@lowepower.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 14711731Sjason@lowepower.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 14811731Sjason@lowepower.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 14911731Sjason@lowepower.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 15011731Sjason@lowepower.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 15111731Sjason@lowepower.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 15211731Sjason@lowepower.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 15311731Sjason@lowepower.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 15411731Sjason@lowepower.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 15511731Sjason@lowepower.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 15611731Sjason@lowepower.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 15711731Sjason@lowepower.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 15811731Sjason@lowepower.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 15911731Sjason@lowepower.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 16011731Sjason@lowepower.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16111731Sjason@lowepower.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16211731Sjason@lowepower.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16311731Sjason@lowepower.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16411731Sjason@lowepower.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16511731Sjason@lowepower.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16611731Sjason@lowepower.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 16711731Sjason@lowepower.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 16811731Sjason@lowepower.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 16911731Sjason@lowepower.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 17011731Sjason@lowepower.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17111731Sjason@lowepower.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17211731Sjason@lowepower.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17311731Sjason@lowepower.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17411731Sjason@lowepower.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17511731Sjason@lowepower.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17611731Sjason@lowepower.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 17711731Sjason@lowepower.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 17811731Sjason@lowepower.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 17911731Sjason@lowepower.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 18011731Sjason@lowepower.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18111731Sjason@lowepower.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18211731Sjason@lowepower.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18311731Sjason@lowepower.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18411731Sjason@lowepower.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18511731Sjason@lowepower.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18611731Sjason@lowepower.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 18711731Sjason@lowepower.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 18811731Sjason@lowepower.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 18911731Sjason@lowepower.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 19011731Sjason@lowepower.comsystem.physmem.bytesPerActivate::samples 13 # Bytes accessed per row activation 19111731Sjason@lowepower.comsystem.physmem.bytesPerActivate::mean 817.230769 # Bytes accessed per row activation 19211731Sjason@lowepower.comsystem.physmem.bytesPerActivate::gmean 665.111831 # Bytes accessed per row activation 19311731Sjason@lowepower.comsystem.physmem.bytesPerActivate::stdev 349.717542 # Bytes accessed per row activation 19411731Sjason@lowepower.comsystem.physmem.bytesPerActivate::0-127 1 7.69% 7.69% # Bytes accessed per row activation 19511731Sjason@lowepower.comsystem.physmem.bytesPerActivate::128-255 1 7.69% 15.38% # Bytes accessed per row activation 19611731Sjason@lowepower.comsystem.physmem.bytesPerActivate::512-639 1 7.69% 23.08% # Bytes accessed per row activation 19711731Sjason@lowepower.comsystem.physmem.bytesPerActivate::640-767 1 7.69% 30.77% # Bytes accessed per row activation 19811731Sjason@lowepower.comsystem.physmem.bytesPerActivate::1024-1151 9 69.23% 100.00% # Bytes accessed per row activation 19911731Sjason@lowepower.comsystem.physmem.bytesPerActivate::total 13 # Bytes accessed per row activation 20011731Sjason@lowepower.comsystem.physmem.totQLat 1580250 # Total ticks spent queuing 20111731Sjason@lowepower.comsystem.physmem.totMemAccLat 5105250 # Total ticks spent from burst creation until serviced by the DRAM 20211731Sjason@lowepower.comsystem.physmem.totBusLat 940000 # Total ticks spent in databus transfers 20311731Sjason@lowepower.comsystem.physmem.avgQLat 8405.59 # Average queueing delay per DRAM burst 20411731Sjason@lowepower.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 20511731Sjason@lowepower.comsystem.physmem.avgMemAccLat 27155.59 # Average memory access latency per DRAM burst 20611731Sjason@lowepower.comsystem.physmem.avgRdBW 833.53 # Average DRAM read bandwidth in MiByte/s 20711731Sjason@lowepower.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 20811731Sjason@lowepower.comsystem.physmem.avgRdBWSys 833.53 # Average system read bandwidth in MiByte/s 20911731Sjason@lowepower.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 21011731Sjason@lowepower.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21111731Sjason@lowepower.comsystem.physmem.busUtil 6.51 # Data bus utilization in percentage 21211731Sjason@lowepower.comsystem.physmem.busUtilRead 6.51 # Data bus utilization in percentage for reads 21311731Sjason@lowepower.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 21411731Sjason@lowepower.comsystem.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing 21511731Sjason@lowepower.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 21611731Sjason@lowepower.comsystem.physmem.readRowHits 171 # Number of row buffer hits during reads 21711731Sjason@lowepower.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 21811731Sjason@lowepower.comsystem.physmem.readRowHitRate 90.96 # Row buffer hit rate for reads 21911731Sjason@lowepower.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22011731Sjason@lowepower.comsystem.physmem.avgGap 75563.83 # Average gap between requests 22111731Sjason@lowepower.comsystem.physmem.pageHitRate 90.96 # Row buffer hit rate, read and write combined 22211731Sjason@lowepower.comsystem.physmem_0.actEnergy 121380 # Energy for activate commands per rank (pJ) 22311731Sjason@lowepower.comsystem.physmem_0.preEnergy 49335 # Energy for precharge commands per rank (pJ) 22411731Sjason@lowepower.comsystem.physmem_0.readEnergy 1342320 # Energy for read commands per rank (pJ) 22511731Sjason@lowepower.comsystem.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 22611731Sjason@lowepower.comsystem.physmem_0.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) 22711731Sjason@lowepower.comsystem.physmem_0.actBackEnergy 2281140 # Energy for active background per rank (pJ) 22811731Sjason@lowepower.comsystem.physmem_0.preBackEnergy 17760 # Energy for precharge background per rank (pJ) 22911731Sjason@lowepower.comsystem.physmem_0.actPowerDownEnergy 4279560 # Energy for active power-down per rank (pJ) 23011731Sjason@lowepower.comsystem.physmem_0.prePowerDownEnergy 480 # Energy for precharge power-down per rank (pJ) 23111731Sjason@lowepower.comsystem.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 23211731Sjason@lowepower.comsystem.physmem_0.totalEnergy 8706615 # Total energy per rank (pJ) 23311731Sjason@lowepower.comsystem.physmem_0.averagePower 603.160028 # Core power per rank (mW) 23411731Sjason@lowepower.comsystem.physmem_0.totalIdleTime 9188750 # Total Idle time Per DRAM Rank 23511731Sjason@lowepower.comsystem.physmem_0.memoryStateTime::IDLE 18000 # Time in different power states 23611731Sjason@lowepower.comsystem.physmem_0.memoryStateTime::REF 260000 # Time in different power states 23711731Sjason@lowepower.comsystem.physmem_0.memoryStateTime::SREF 0 # Time in different power states 23811731Sjason@lowepower.comsystem.physmem_0.memoryStateTime::PRE_PDN 1250 # Time in different power states 23911731Sjason@lowepower.comsystem.physmem_0.memoryStateTime::ACT 4776000 # Time in different power states 24011731Sjason@lowepower.comsystem.physmem_0.memoryStateTime::ACT_PDN 9379750 # Time in different power states 24111731Sjason@lowepower.comsystem.physmem_1.actEnergy 0 # Energy for activate commands per rank (pJ) 24211731Sjason@lowepower.comsystem.physmem_1.preEnergy 0 # Energy for precharge commands per rank (pJ) 24311731Sjason@lowepower.comsystem.physmem_1.readEnergy 0 # Energy for read commands per rank (pJ) 24411731Sjason@lowepower.comsystem.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 24511731Sjason@lowepower.comsystem.physmem_1.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) 24611731Sjason@lowepower.comsystem.physmem_1.actBackEnergy 112290 # Energy for active background per rank (pJ) 24711731Sjason@lowepower.comsystem.physmem_1.preBackEnergy 2995200 # Energy for precharge background per rank (pJ) 24811731Sjason@lowepower.comsystem.physmem_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) 24911731Sjason@lowepower.comsystem.physmem_1.prePowerDownEnergy 2453280 # Energy for precharge power-down per rank (pJ) 25011731Sjason@lowepower.comsystem.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 25111731Sjason@lowepower.comsystem.physmem_1.totalEnergy 6175410 # Total energy per rank (pJ) 25211731Sjason@lowepower.comsystem.physmem_1.averagePower 427.808105 # Core power per rank (mW) 25311731Sjason@lowepower.comsystem.physmem_1.totalIdleTime 0 # Total Idle time Per DRAM Rank 25411731Sjason@lowepower.comsystem.physmem_1.memoryStateTime::IDLE 7786250 # Time in different power states 25511731Sjason@lowepower.comsystem.physmem_1.memoryStateTime::REF 260000 # Time in different power states 25611731Sjason@lowepower.comsystem.physmem_1.memoryStateTime::SREF 0 # Time in different power states 25711731Sjason@lowepower.comsystem.physmem_1.memoryStateTime::PRE_PDN 6388750 # Time in different power states 25811731Sjason@lowepower.comsystem.physmem_1.memoryStateTime::ACT 0 # Time in different power states 25911731Sjason@lowepower.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 26011731Sjason@lowepower.comsystem.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states 26111731Sjason@lowepower.comsystem.cpu.branchPred.lookups 995 # Number of BP lookups 26211731Sjason@lowepower.comsystem.cpu.branchPred.condPredicted 543 # Number of conditional branches predicted 26311731Sjason@lowepower.comsystem.cpu.branchPred.condIncorrect 229 # Number of conditional branches incorrect 26411731Sjason@lowepower.comsystem.cpu.branchPred.BTBLookups 945 # Number of BTB lookups 26511731Sjason@lowepower.comsystem.cpu.branchPred.BTBHits 100 # Number of BTB hits 26611731Sjason@lowepower.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 26711731Sjason@lowepower.comsystem.cpu.branchPred.BTBHitPct 10.582011 # BTB Hit Percentage 26811731Sjason@lowepower.comsystem.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. 26911731Sjason@lowepower.comsystem.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. 27011731Sjason@lowepower.comsystem.cpu.branchPred.indirectLookups 204 # Number of indirect predictor lookups. 27111731Sjason@lowepower.comsystem.cpu.branchPred.indirectHits 11 # Number of indirect target hits. 27211731Sjason@lowepower.comsystem.cpu.branchPred.indirectMisses 193 # Number of indirect misses. 27311731Sjason@lowepower.comsystem.cpu.branchPredindirectMispredicted 64 # Number of mispredicted indirect branches. 27411731Sjason@lowepower.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 27511731Sjason@lowepower.comsystem.cpu.dtb.read_hits 0 # DTB read hits 27611731Sjason@lowepower.comsystem.cpu.dtb.read_misses 0 # DTB read misses 27711731Sjason@lowepower.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 27811731Sjason@lowepower.comsystem.cpu.dtb.write_hits 0 # DTB write hits 27911731Sjason@lowepower.comsystem.cpu.dtb.write_misses 0 # DTB write misses 28011731Sjason@lowepower.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 28111731Sjason@lowepower.comsystem.cpu.dtb.hits 0 # DTB hits 28211731Sjason@lowepower.comsystem.cpu.dtb.misses 0 # DTB misses 28311731Sjason@lowepower.comsystem.cpu.dtb.accesses 0 # DTB accesses 28411731Sjason@lowepower.comsystem.cpu.itb.read_hits 0 # DTB read hits 28511731Sjason@lowepower.comsystem.cpu.itb.read_misses 0 # DTB read misses 28611731Sjason@lowepower.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 28711731Sjason@lowepower.comsystem.cpu.itb.write_hits 0 # DTB write hits 28811731Sjason@lowepower.comsystem.cpu.itb.write_misses 0 # DTB write misses 28911731Sjason@lowepower.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 29011731Sjason@lowepower.comsystem.cpu.itb.hits 0 # DTB hits 29111731Sjason@lowepower.comsystem.cpu.itb.misses 0 # DTB misses 29211731Sjason@lowepower.comsystem.cpu.itb.accesses 0 # DTB accesses 29311731Sjason@lowepower.comsystem.cpu.workload.num_syscalls 9 # Number of system calls 29411731Sjason@lowepower.comsystem.cpu.pwrStateResidencyTicks::ON 14435000 # Cumulative time (in ticks) in various power states 29511731Sjason@lowepower.comsystem.cpu.numCycles 28870 # number of cpu cycles simulated 29611731Sjason@lowepower.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 29711731Sjason@lowepower.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 29811731Sjason@lowepower.comsystem.cpu.committedInsts 1597 # Number of instructions committed 29911731Sjason@lowepower.comsystem.cpu.committedOps 1597 # Number of ops (including micro ops) committed 30011731Sjason@lowepower.comsystem.cpu.discardedOps 744 # Number of ops (including micro ops) which were discarded before commit 30111731Sjason@lowepower.comsystem.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 30211731Sjason@lowepower.comsystem.cpu.cpi 18.077646 # CPI: cycles per instruction 30311731Sjason@lowepower.comsystem.cpu.ipc 0.055317 # IPC: instructions per cycle 30411731Sjason@lowepower.comsystem.cpu.op_class_0::No_OpClass 9 0.56% 0.56% # Class of committed instruction 30511731Sjason@lowepower.comsystem.cpu.op_class_0::IntAlu 1019 63.81% 64.37% # Class of committed instruction 30611731Sjason@lowepower.comsystem.cpu.op_class_0::IntMult 0 0.00% 64.37% # Class of committed instruction 30711731Sjason@lowepower.comsystem.cpu.op_class_0::IntDiv 0 0.00% 64.37% # Class of committed instruction 30811731Sjason@lowepower.comsystem.cpu.op_class_0::FloatAdd 0 0.00% 64.37% # Class of committed instruction 30911731Sjason@lowepower.comsystem.cpu.op_class_0::FloatCmp 0 0.00% 64.37% # Class of committed instruction 31011731Sjason@lowepower.comsystem.cpu.op_class_0::FloatCvt 0 0.00% 64.37% # Class of committed instruction 31111731Sjason@lowepower.comsystem.cpu.op_class_0::FloatMult 0 0.00% 64.37% # Class of committed instruction 31211731Sjason@lowepower.comsystem.cpu.op_class_0::FloatMultAcc 0 0.00% 64.37% # Class of committed instruction 31311731Sjason@lowepower.comsystem.cpu.op_class_0::FloatDiv 0 0.00% 64.37% # Class of committed instruction 31411731Sjason@lowepower.comsystem.cpu.op_class_0::FloatMisc 0 0.00% 64.37% # Class of committed instruction 31511731Sjason@lowepower.comsystem.cpu.op_class_0::FloatSqrt 0 0.00% 64.37% # Class of committed instruction 31611731Sjason@lowepower.comsystem.cpu.op_class_0::SimdAdd 0 0.00% 64.37% # Class of committed instruction 31711731Sjason@lowepower.comsystem.cpu.op_class_0::SimdAddAcc 0 0.00% 64.37% # Class of committed instruction 31811731Sjason@lowepower.comsystem.cpu.op_class_0::SimdAlu 0 0.00% 64.37% # Class of committed instruction 31911731Sjason@lowepower.comsystem.cpu.op_class_0::SimdCmp 0 0.00% 64.37% # Class of committed instruction 32011731Sjason@lowepower.comsystem.cpu.op_class_0::SimdCvt 0 0.00% 64.37% # Class of committed instruction 32111731Sjason@lowepower.comsystem.cpu.op_class_0::SimdMisc 0 0.00% 64.37% # Class of committed instruction 32211731Sjason@lowepower.comsystem.cpu.op_class_0::SimdMult 0 0.00% 64.37% # Class of committed instruction 32311731Sjason@lowepower.comsystem.cpu.op_class_0::SimdMultAcc 0 0.00% 64.37% # Class of committed instruction 32411731Sjason@lowepower.comsystem.cpu.op_class_0::SimdShift 0 0.00% 64.37% # Class of committed instruction 32511731Sjason@lowepower.comsystem.cpu.op_class_0::SimdShiftAcc 0 0.00% 64.37% # Class of committed instruction 32611731Sjason@lowepower.comsystem.cpu.op_class_0::SimdSqrt 0 0.00% 64.37% # Class of committed instruction 32711731Sjason@lowepower.comsystem.cpu.op_class_0::SimdFloatAdd 0 0.00% 64.37% # Class of committed instruction 32811731Sjason@lowepower.comsystem.cpu.op_class_0::SimdFloatAlu 0 0.00% 64.37% # Class of committed instruction 32911731Sjason@lowepower.comsystem.cpu.op_class_0::SimdFloatCmp 0 0.00% 64.37% # Class of committed instruction 33011731Sjason@lowepower.comsystem.cpu.op_class_0::SimdFloatCvt 0 0.00% 64.37% # Class of committed instruction 33111731Sjason@lowepower.comsystem.cpu.op_class_0::SimdFloatDiv 0 0.00% 64.37% # Class of committed instruction 33211731Sjason@lowepower.comsystem.cpu.op_class_0::SimdFloatMisc 0 0.00% 64.37% # Class of committed instruction 33311731Sjason@lowepower.comsystem.cpu.op_class_0::SimdFloatMult 0 0.00% 64.37% # Class of committed instruction 33411731Sjason@lowepower.comsystem.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 64.37% # Class of committed instruction 33511731Sjason@lowepower.comsystem.cpu.op_class_0::SimdFloatSqrt 0 0.00% 64.37% # Class of committed instruction 33611731Sjason@lowepower.comsystem.cpu.op_class_0::MemRead 289 18.10% 82.47% # Class of committed instruction 33711731Sjason@lowepower.comsystem.cpu.op_class_0::MemWrite 280 17.53% 100.00% # Class of committed instruction 33811731Sjason@lowepower.comsystem.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction 33911731Sjason@lowepower.comsystem.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction 34011731Sjason@lowepower.comsystem.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 34111731Sjason@lowepower.comsystem.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 34211731Sjason@lowepower.comsystem.cpu.op_class_0::total 1597 # Class of committed instruction 34311731Sjason@lowepower.comsystem.cpu.tickCycles 4106 # Number of cycles that the object actually ticked 34411731Sjason@lowepower.comsystem.cpu.idleCycles 24764 # Total number of cycles that the object has spent stopped 34511731Sjason@lowepower.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states 34611731Sjason@lowepower.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 34711731Sjason@lowepower.comsystem.cpu.dcache.tags.tagsinuse 24.135470 # Cycle average of tags in use 34811731Sjason@lowepower.comsystem.cpu.dcache.tags.total_refs 645 # Total number of references to valid blocks. 34911731Sjason@lowepower.comsystem.cpu.dcache.tags.sampled_refs 33 # Sample count of references to valid blocks. 35011731Sjason@lowepower.comsystem.cpu.dcache.tags.avg_refs 19.545455 # Average number of references to valid blocks. 35111731Sjason@lowepower.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 35211731Sjason@lowepower.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 24.135470 # Average occupied blocks per requestor 35311731Sjason@lowepower.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.005892 # Average percentage of cache occupancy 35411731Sjason@lowepower.comsystem.cpu.dcache.tags.occ_percent::total 0.005892 # Average percentage of cache occupancy 35511731Sjason@lowepower.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 33 # Occupied blocks per task id 35611731Sjason@lowepower.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id 35711731Sjason@lowepower.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id 35811731Sjason@lowepower.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 0.008057 # Percentage of cache occupancy per task id 35911731Sjason@lowepower.comsystem.cpu.dcache.tags.tag_accesses 1411 # Number of tag accesses 36011731Sjason@lowepower.comsystem.cpu.dcache.tags.data_accesses 1411 # Number of data accesses 36111731Sjason@lowepower.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states 36211731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_hits::cpu.data 394 # number of ReadReq hits 36311731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_hits::total 394 # number of ReadReq hits 36411731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_hits::cpu.data 251 # number of WriteReq hits 36511731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_hits::total 251 # number of WriteReq hits 36611731Sjason@lowepower.comsystem.cpu.dcache.demand_hits::cpu.data 645 # number of demand (read+write) hits 36711731Sjason@lowepower.comsystem.cpu.dcache.demand_hits::total 645 # number of demand (read+write) hits 36811731Sjason@lowepower.comsystem.cpu.dcache.overall_hits::cpu.data 645 # number of overall hits 36911731Sjason@lowepower.comsystem.cpu.dcache.overall_hits::total 645 # number of overall hits 37011731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_misses::cpu.data 16 # number of ReadReq misses 37111731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_misses::total 16 # number of ReadReq misses 37211731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_misses::cpu.data 28 # number of WriteReq misses 37311731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_misses::total 28 # number of WriteReq misses 37411731Sjason@lowepower.comsystem.cpu.dcache.demand_misses::cpu.data 44 # number of demand (read+write) misses 37511731Sjason@lowepower.comsystem.cpu.dcache.demand_misses::total 44 # number of demand (read+write) misses 37611731Sjason@lowepower.comsystem.cpu.dcache.overall_misses::cpu.data 44 # number of overall misses 37711731Sjason@lowepower.comsystem.cpu.dcache.overall_misses::total 44 # number of overall misses 37811731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 1268000 # number of ReadReq miss cycles 37911731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_miss_latency::total 1268000 # number of ReadReq miss cycles 38011731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 2223500 # number of WriteReq miss cycles 38111731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_miss_latency::total 2223500 # number of WriteReq miss cycles 38211731Sjason@lowepower.comsystem.cpu.dcache.demand_miss_latency::cpu.data 3491500 # number of demand (read+write) miss cycles 38311731Sjason@lowepower.comsystem.cpu.dcache.demand_miss_latency::total 3491500 # number of demand (read+write) miss cycles 38411731Sjason@lowepower.comsystem.cpu.dcache.overall_miss_latency::cpu.data 3491500 # number of overall miss cycles 38511731Sjason@lowepower.comsystem.cpu.dcache.overall_miss_latency::total 3491500 # number of overall miss cycles 38611731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 410 # number of ReadReq accesses(hits+misses) 38711731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_accesses::total 410 # number of ReadReq accesses(hits+misses) 38811731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 279 # number of WriteReq accesses(hits+misses) 38911731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_accesses::total 279 # number of WriteReq accesses(hits+misses) 39011731Sjason@lowepower.comsystem.cpu.dcache.demand_accesses::cpu.data 689 # number of demand (read+write) accesses 39111731Sjason@lowepower.comsystem.cpu.dcache.demand_accesses::total 689 # number of demand (read+write) accesses 39211731Sjason@lowepower.comsystem.cpu.dcache.overall_accesses::cpu.data 689 # number of overall (read+write) accesses 39311731Sjason@lowepower.comsystem.cpu.dcache.overall_accesses::total 689 # number of overall (read+write) accesses 39411731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039024 # miss rate for ReadReq accesses 39511731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.039024 # miss rate for ReadReq accesses 39611731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.100358 # miss rate for WriteReq accesses 39711731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.100358 # miss rate for WriteReq accesses 39811731Sjason@lowepower.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.063861 # miss rate for demand accesses 39911731Sjason@lowepower.comsystem.cpu.dcache.demand_miss_rate::total 0.063861 # miss rate for demand accesses 40011731Sjason@lowepower.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.063861 # miss rate for overall accesses 40111731Sjason@lowepower.comsystem.cpu.dcache.overall_miss_rate::total 0.063861 # miss rate for overall accesses 40211731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79250 # average ReadReq miss latency 40311731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 79250 # average ReadReq miss latency 40411731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79410.714286 # average WriteReq miss latency 40511731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 79410.714286 # average WriteReq miss latency 40611731Sjason@lowepower.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 79352.272727 # average overall miss latency 40711731Sjason@lowepower.comsystem.cpu.dcache.demand_avg_miss_latency::total 79352.272727 # average overall miss latency 40811731Sjason@lowepower.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 79352.272727 # average overall miss latency 40911731Sjason@lowepower.comsystem.cpu.dcache.overall_avg_miss_latency::total 79352.272727 # average overall miss latency 41011731Sjason@lowepower.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 41111731Sjason@lowepower.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 41211731Sjason@lowepower.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 41311731Sjason@lowepower.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 41411731Sjason@lowepower.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 41511731Sjason@lowepower.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 41611731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 11 # number of WriteReq MSHR hits 41711731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_hits::total 11 # number of WriteReq MSHR hits 41811731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 11 # number of demand (read+write) MSHR hits 41911731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits 42011731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 11 # number of overall MSHR hits 42111731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_hits::total 11 # number of overall MSHR hits 42211731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 16 # number of ReadReq MSHR misses 42311731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_misses::total 16 # number of ReadReq MSHR misses 42411731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 17 # number of WriteReq MSHR misses 42511731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_misses::total 17 # number of WriteReq MSHR misses 42611731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 33 # number of demand (read+write) MSHR misses 42711731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_misses::total 33 # number of demand (read+write) MSHR misses 42811731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 33 # number of overall MSHR misses 42911731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_misses::total 33 # number of overall MSHR misses 43011731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1252000 # number of ReadReq MSHR miss cycles 43111731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 1252000 # number of ReadReq MSHR miss cycles 43211731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1342000 # number of WriteReq MSHR miss cycles 43311731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 1342000 # number of WriteReq MSHR miss cycles 43411731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 2594000 # number of demand (read+write) MSHR miss cycles 43511731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_miss_latency::total 2594000 # number of demand (read+write) MSHR miss cycles 43611731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 2594000 # number of overall MSHR miss cycles 43711731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_miss_latency::total 2594000 # number of overall MSHR miss cycles 43811731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039024 # mshr miss rate for ReadReq accesses 43911731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039024 # mshr miss rate for ReadReq accesses 44011731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.060932 # mshr miss rate for WriteReq accesses 44111731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.060932 # mshr miss rate for WriteReq accesses 44211731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.047896 # mshr miss rate for demand accesses 44311731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.047896 # mshr miss rate for demand accesses 44411731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.047896 # mshr miss rate for overall accesses 44511731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.047896 # mshr miss rate for overall accesses 44611731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78250 # average ReadReq mshr miss latency 44711731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78250 # average ReadReq mshr miss latency 44811731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78941.176471 # average WriteReq mshr miss latency 44911731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78941.176471 # average WriteReq mshr miss latency 45011731Sjason@lowepower.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78606.060606 # average overall mshr miss latency 45111731Sjason@lowepower.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 78606.060606 # average overall mshr miss latency 45211731Sjason@lowepower.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78606.060606 # average overall mshr miss latency 45311731Sjason@lowepower.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 78606.060606 # average overall mshr miss latency 45411731Sjason@lowepower.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states 45511731Sjason@lowepower.comsystem.cpu.icache.tags.replacements 0 # number of replacements 45611731Sjason@lowepower.comsystem.cpu.icache.tags.tagsinuse 79.926884 # Cycle average of tags in use 45711731Sjason@lowepower.comsystem.cpu.icache.tags.total_refs 709 # Total number of references to valid blocks. 45811731Sjason@lowepower.comsystem.cpu.icache.tags.sampled_refs 157 # Sample count of references to valid blocks. 45911731Sjason@lowepower.comsystem.cpu.icache.tags.avg_refs 4.515924 # Average number of references to valid blocks. 46011731Sjason@lowepower.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 46111731Sjason@lowepower.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 79.926884 # Average occupied blocks per requestor 46211731Sjason@lowepower.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.039027 # Average percentage of cache occupancy 46311731Sjason@lowepower.comsystem.cpu.icache.tags.occ_percent::total 0.039027 # Average percentage of cache occupancy 46411731Sjason@lowepower.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 157 # Occupied blocks per task id 46511731Sjason@lowepower.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id 46611731Sjason@lowepower.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 49 # Occupied blocks per task id 46711731Sjason@lowepower.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.076660 # Percentage of cache occupancy per task id 46811731Sjason@lowepower.comsystem.cpu.icache.tags.tag_accesses 1889 # Number of tag accesses 46911731Sjason@lowepower.comsystem.cpu.icache.tags.data_accesses 1889 # Number of data accesses 47011731Sjason@lowepower.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states 47111731Sjason@lowepower.comsystem.cpu.icache.ReadReq_hits::cpu.inst 709 # number of ReadReq hits 47211731Sjason@lowepower.comsystem.cpu.icache.ReadReq_hits::total 709 # number of ReadReq hits 47311731Sjason@lowepower.comsystem.cpu.icache.demand_hits::cpu.inst 709 # number of demand (read+write) hits 47411731Sjason@lowepower.comsystem.cpu.icache.demand_hits::total 709 # number of demand (read+write) hits 47511731Sjason@lowepower.comsystem.cpu.icache.overall_hits::cpu.inst 709 # number of overall hits 47611731Sjason@lowepower.comsystem.cpu.icache.overall_hits::total 709 # number of overall hits 47711731Sjason@lowepower.comsystem.cpu.icache.ReadReq_misses::cpu.inst 157 # number of ReadReq misses 47811731Sjason@lowepower.comsystem.cpu.icache.ReadReq_misses::total 157 # number of ReadReq misses 47911731Sjason@lowepower.comsystem.cpu.icache.demand_misses::cpu.inst 157 # number of demand (read+write) misses 48011731Sjason@lowepower.comsystem.cpu.icache.demand_misses::total 157 # number of demand (read+write) misses 48111731Sjason@lowepower.comsystem.cpu.icache.overall_misses::cpu.inst 157 # number of overall misses 48211731Sjason@lowepower.comsystem.cpu.icache.overall_misses::total 157 # number of overall misses 48311731Sjason@lowepower.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 12560500 # number of ReadReq miss cycles 48411731Sjason@lowepower.comsystem.cpu.icache.ReadReq_miss_latency::total 12560500 # number of ReadReq miss cycles 48511731Sjason@lowepower.comsystem.cpu.icache.demand_miss_latency::cpu.inst 12560500 # number of demand (read+write) miss cycles 48611731Sjason@lowepower.comsystem.cpu.icache.demand_miss_latency::total 12560500 # number of demand (read+write) miss cycles 48711731Sjason@lowepower.comsystem.cpu.icache.overall_miss_latency::cpu.inst 12560500 # number of overall miss cycles 48811731Sjason@lowepower.comsystem.cpu.icache.overall_miss_latency::total 12560500 # number of overall miss cycles 48911731Sjason@lowepower.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 866 # number of ReadReq accesses(hits+misses) 49011731Sjason@lowepower.comsystem.cpu.icache.ReadReq_accesses::total 866 # number of ReadReq accesses(hits+misses) 49111731Sjason@lowepower.comsystem.cpu.icache.demand_accesses::cpu.inst 866 # number of demand (read+write) accesses 49211731Sjason@lowepower.comsystem.cpu.icache.demand_accesses::total 866 # number of demand (read+write) accesses 49311731Sjason@lowepower.comsystem.cpu.icache.overall_accesses::cpu.inst 866 # number of overall (read+write) accesses 49411731Sjason@lowepower.comsystem.cpu.icache.overall_accesses::total 866 # number of overall (read+write) accesses 49511731Sjason@lowepower.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.181293 # miss rate for ReadReq accesses 49611731Sjason@lowepower.comsystem.cpu.icache.ReadReq_miss_rate::total 0.181293 # miss rate for ReadReq accesses 49711731Sjason@lowepower.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.181293 # miss rate for demand accesses 49811731Sjason@lowepower.comsystem.cpu.icache.demand_miss_rate::total 0.181293 # miss rate for demand accesses 49911731Sjason@lowepower.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.181293 # miss rate for overall accesses 50011731Sjason@lowepower.comsystem.cpu.icache.overall_miss_rate::total 0.181293 # miss rate for overall accesses 50111731Sjason@lowepower.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80003.184713 # average ReadReq miss latency 50211731Sjason@lowepower.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 80003.184713 # average ReadReq miss latency 50311731Sjason@lowepower.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 80003.184713 # average overall miss latency 50411731Sjason@lowepower.comsystem.cpu.icache.demand_avg_miss_latency::total 80003.184713 # average overall miss latency 50511731Sjason@lowepower.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 80003.184713 # average overall miss latency 50611731Sjason@lowepower.comsystem.cpu.icache.overall_avg_miss_latency::total 80003.184713 # average overall miss latency 50711731Sjason@lowepower.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 50811731Sjason@lowepower.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 50911731Sjason@lowepower.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 51011731Sjason@lowepower.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 51111731Sjason@lowepower.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 51211731Sjason@lowepower.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 51311731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 157 # number of ReadReq MSHR misses 51411731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_misses::total 157 # number of ReadReq MSHR misses 51511731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 157 # number of demand (read+write) MSHR misses 51611731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_misses::total 157 # number of demand (read+write) MSHR misses 51711731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 157 # number of overall MSHR misses 51811731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_misses::total 157 # number of overall MSHR misses 51911731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12403500 # number of ReadReq MSHR miss cycles 52011731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 12403500 # number of ReadReq MSHR miss cycles 52111731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 12403500 # number of demand (read+write) MSHR miss cycles 52211731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_miss_latency::total 12403500 # number of demand (read+write) MSHR miss cycles 52311731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 12403500 # number of overall MSHR miss cycles 52411731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_miss_latency::total 12403500 # number of overall MSHR miss cycles 52511731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.181293 # mshr miss rate for ReadReq accesses 52611731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.181293 # mshr miss rate for ReadReq accesses 52711731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.181293 # mshr miss rate for demand accesses 52811731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.181293 # mshr miss rate for demand accesses 52911731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.181293 # mshr miss rate for overall accesses 53011731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.181293 # mshr miss rate for overall accesses 53111731Sjason@lowepower.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79003.184713 # average ReadReq mshr miss latency 53211731Sjason@lowepower.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79003.184713 # average ReadReq mshr miss latency 53311731Sjason@lowepower.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79003.184713 # average overall mshr miss latency 53411731Sjason@lowepower.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 79003.184713 # average overall mshr miss latency 53511731Sjason@lowepower.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79003.184713 # average overall mshr miss latency 53611731Sjason@lowepower.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 79003.184713 # average overall mshr miss latency 53711731Sjason@lowepower.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states 53811731Sjason@lowepower.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 53911731Sjason@lowepower.comsystem.cpu.l2cache.tags.tagsinuse 102.489649 # Cycle average of tags in use 54011731Sjason@lowepower.comsystem.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 54111731Sjason@lowepower.comsystem.cpu.l2cache.tags.sampled_refs 188 # Sample count of references to valid blocks. 54211731Sjason@lowepower.comsystem.cpu.l2cache.tags.avg_refs 0.010638 # Average number of references to valid blocks. 54311731Sjason@lowepower.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 54411731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 79.179084 # Average occupied blocks per requestor 54511731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 23.310565 # Average occupied blocks per requestor 54611731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.002416 # Average percentage of cache occupancy 54711731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.000711 # Average percentage of cache occupancy 54811731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_percent::total 0.003128 # Average percentage of cache occupancy 54911731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id 55011731Sjason@lowepower.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id 55111731Sjason@lowepower.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id 55211731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.005737 # Percentage of cache occupancy per task id 55311731Sjason@lowepower.comsystem.cpu.l2cache.tags.tag_accesses 1708 # Number of tag accesses 55411731Sjason@lowepower.comsystem.cpu.l2cache.tags.data_accesses 1708 # Number of data accesses 55511731Sjason@lowepower.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states 55611731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 55711731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 55811731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits 55911731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits 56011731Sjason@lowepower.comsystem.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 56111731Sjason@lowepower.comsystem.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits 56211731Sjason@lowepower.comsystem.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 56311731Sjason@lowepower.comsystem.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 56411731Sjason@lowepower.comsystem.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits 56511731Sjason@lowepower.comsystem.cpu.l2cache.overall_hits::total 2 # number of overall hits 56611731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 17 # number of ReadExReq misses 56711731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_misses::total 17 # number of ReadExReq misses 56811731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 156 # number of ReadCleanReq misses 56911731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_misses::total 156 # number of ReadCleanReq misses 57011731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 15 # number of ReadSharedReq misses 57111731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_misses::total 15 # number of ReadSharedReq misses 57211731Sjason@lowepower.comsystem.cpu.l2cache.demand_misses::cpu.inst 156 # number of demand (read+write) misses 57311731Sjason@lowepower.comsystem.cpu.l2cache.demand_misses::cpu.data 32 # number of demand (read+write) misses 57411731Sjason@lowepower.comsystem.cpu.l2cache.demand_misses::total 188 # number of demand (read+write) misses 57511731Sjason@lowepower.comsystem.cpu.l2cache.overall_misses::cpu.inst 156 # number of overall misses 57611731Sjason@lowepower.comsystem.cpu.l2cache.overall_misses::cpu.data 32 # number of overall misses 57711731Sjason@lowepower.comsystem.cpu.l2cache.overall_misses::total 188 # number of overall misses 57811731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1316500 # number of ReadExReq miss cycles 57911731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 1316500 # number of ReadExReq miss cycles 58011731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 12156500 # number of ReadCleanReq miss cycles 58111731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 12156500 # number of ReadCleanReq miss cycles 58211731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1215500 # number of ReadSharedReq miss cycles 58311731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 1215500 # number of ReadSharedReq miss cycles 58411731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 12156500 # number of demand (read+write) miss cycles 58511731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 2532000 # number of demand (read+write) miss cycles 58611731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_latency::total 14688500 # number of demand (read+write) miss cycles 58711731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 12156500 # number of overall miss cycles 58811731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 2532000 # number of overall miss cycles 58911731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_latency::total 14688500 # number of overall miss cycles 59011731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 17 # number of ReadExReq accesses(hits+misses) 59111731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_accesses::total 17 # number of ReadExReq accesses(hits+misses) 59211731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 157 # number of ReadCleanReq accesses(hits+misses) 59311731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 157 # number of ReadCleanReq accesses(hits+misses) 59411731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 16 # number of ReadSharedReq accesses(hits+misses) 59511731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 16 # number of ReadSharedReq accesses(hits+misses) 59611731Sjason@lowepower.comsystem.cpu.l2cache.demand_accesses::cpu.inst 157 # number of demand (read+write) accesses 59711731Sjason@lowepower.comsystem.cpu.l2cache.demand_accesses::cpu.data 33 # number of demand (read+write) accesses 59811731Sjason@lowepower.comsystem.cpu.l2cache.demand_accesses::total 190 # number of demand (read+write) accesses 59911731Sjason@lowepower.comsystem.cpu.l2cache.overall_accesses::cpu.inst 157 # number of overall (read+write) accesses 60011731Sjason@lowepower.comsystem.cpu.l2cache.overall_accesses::cpu.data 33 # number of overall (read+write) accesses 60111731Sjason@lowepower.comsystem.cpu.l2cache.overall_accesses::total 190 # number of overall (read+write) accesses 60211731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 60311731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 60411731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.993631 # miss rate for ReadCleanReq accesses 60511731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993631 # miss rate for ReadCleanReq accesses 60611731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.937500 # miss rate for ReadSharedReq accesses 60711731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.937500 # miss rate for ReadSharedReq accesses 60811731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.993631 # miss rate for demand accesses 60911731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.969697 # miss rate for demand accesses 61011731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_rate::total 0.989474 # miss rate for demand accesses 61111731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.993631 # miss rate for overall accesses 61211731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.969697 # miss rate for overall accesses 61311731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_rate::total 0.989474 # miss rate for overall accesses 61411731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77441.176471 # average ReadExReq miss latency 61511731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 77441.176471 # average ReadExReq miss latency 61611731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77926.282051 # average ReadCleanReq miss latency 61711731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77926.282051 # average ReadCleanReq miss latency 61811731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81033.333333 # average ReadSharedReq miss latency 61911731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81033.333333 # average ReadSharedReq miss latency 62011731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77926.282051 # average overall miss latency 62111731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 79125 # average overall miss latency 62211731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_miss_latency::total 78130.319149 # average overall miss latency 62311731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77926.282051 # average overall miss latency 62411731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 79125 # average overall miss latency 62511731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_miss_latency::total 78130.319149 # average overall miss latency 62611731Sjason@lowepower.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 62711731Sjason@lowepower.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 62811731Sjason@lowepower.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 62911731Sjason@lowepower.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 63011731Sjason@lowepower.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 63111731Sjason@lowepower.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 63211731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 17 # number of ReadExReq MSHR misses 63311731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 17 # number of ReadExReq MSHR misses 63411731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 156 # number of ReadCleanReq MSHR misses 63511731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 156 # number of ReadCleanReq MSHR misses 63611731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 15 # number of ReadSharedReq MSHR misses 63711731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 15 # number of ReadSharedReq MSHR misses 63811731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 156 # number of demand (read+write) MSHR misses 63911731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 32 # number of demand (read+write) MSHR misses 64011731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses 64111731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 156 # number of overall MSHR misses 64211731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 32 # number of overall MSHR misses 64311731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_misses::total 188 # number of overall MSHR misses 64411731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1146500 # number of ReadExReq MSHR miss cycles 64511731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1146500 # number of ReadExReq MSHR miss cycles 64611731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10596500 # number of ReadCleanReq MSHR miss cycles 64711731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10596500 # number of ReadCleanReq MSHR miss cycles 64811731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1065500 # number of ReadSharedReq MSHR miss cycles 64911731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1065500 # number of ReadSharedReq MSHR miss cycles 65011731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10596500 # number of demand (read+write) MSHR miss cycles 65111731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2212000 # number of demand (read+write) MSHR miss cycles 65211731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 12808500 # number of demand (read+write) MSHR miss cycles 65311731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10596500 # number of overall MSHR miss cycles 65411731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2212000 # number of overall MSHR miss cycles 65511731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 12808500 # number of overall MSHR miss cycles 65611731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 65711731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 65811731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993631 # mshr miss rate for ReadCleanReq accesses 65911731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993631 # mshr miss rate for ReadCleanReq accesses 66011731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.937500 # mshr miss rate for ReadSharedReq accesses 66111731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.937500 # mshr miss rate for ReadSharedReq accesses 66211731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993631 # mshr miss rate for demand accesses 66311731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.969697 # mshr miss rate for demand accesses 66411731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.989474 # mshr miss rate for demand accesses 66511731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993631 # mshr miss rate for overall accesses 66611731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.969697 # mshr miss rate for overall accesses 66711731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.989474 # mshr miss rate for overall accesses 66811731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67441.176471 # average ReadExReq mshr miss latency 66911731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67441.176471 # average ReadExReq mshr miss latency 67011731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67926.282051 # average ReadCleanReq mshr miss latency 67111731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67926.282051 # average ReadCleanReq mshr miss latency 67211731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71033.333333 # average ReadSharedReq mshr miss latency 67311731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71033.333333 # average ReadSharedReq mshr miss latency 67411731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67926.282051 # average overall mshr miss latency 67511731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69125 # average overall mshr miss latency 67611731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 68130.319149 # average overall mshr miss latency 67711731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67926.282051 # average overall mshr miss latency 67811731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69125 # average overall mshr miss latency 67911731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 68130.319149 # average overall mshr miss latency 68011731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 190 # Total number of requests made to the snoop filter. 68111731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. 68211731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 68311731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 68411731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 68511731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 68611731Sjason@lowepower.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states 68711731Sjason@lowepower.comsystem.cpu.toL2Bus.trans_dist::ReadResp 173 # Transaction distribution 68811731Sjason@lowepower.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 17 # Transaction distribution 68911731Sjason@lowepower.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 17 # Transaction distribution 69011731Sjason@lowepower.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 157 # Transaction distribution 69111731Sjason@lowepower.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 16 # Transaction distribution 69211731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 314 # Packet count per connected master and slave (bytes) 69311731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 66 # Packet count per connected master and slave (bytes) 69411731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_count::total 380 # Packet count per connected master and slave (bytes) 69511731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10048 # Cumulative packet size per connected master and slave (bytes) 69611731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2112 # Cumulative packet size per connected master and slave (bytes) 69711731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_size::total 12160 # Cumulative packet size per connected master and slave (bytes) 69811731Sjason@lowepower.comsystem.cpu.toL2Bus.snoops 0 # Total snoops (count) 69911731Sjason@lowepower.comsystem.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) 70011731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::samples 190 # Request fanout histogram 70111731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.010526 # Request fanout histogram 70211731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.102326 # Request fanout histogram 70311731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 70411731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::0 188 98.95% 98.95% # Request fanout histogram 70511731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::1 2 1.05% 100.00% # Request fanout histogram 70611731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 70711731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 70811731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 70911731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 71011731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::total 190 # Request fanout histogram 71111731Sjason@lowepower.comsystem.cpu.toL2Bus.reqLayer0.occupancy 95000 # Layer occupancy (ticks) 71211731Sjason@lowepower.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 71311731Sjason@lowepower.comsystem.cpu.toL2Bus.respLayer0.occupancy 235500 # Layer occupancy (ticks) 71411731Sjason@lowepower.comsystem.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%) 71511731Sjason@lowepower.comsystem.cpu.toL2Bus.respLayer1.occupancy 49500 # Layer occupancy (ticks) 71611731Sjason@lowepower.comsystem.cpu.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) 71711731Sjason@lowepower.comsystem.membus.snoop_filter.tot_requests 188 # Total number of requests made to the snoop filter. 71811731Sjason@lowepower.comsystem.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 71911731Sjason@lowepower.comsystem.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 72011731Sjason@lowepower.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 72111731Sjason@lowepower.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 72211731Sjason@lowepower.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 72311731Sjason@lowepower.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states 72411731Sjason@lowepower.comsystem.membus.trans_dist::ReadResp 171 # Transaction distribution 72511731Sjason@lowepower.comsystem.membus.trans_dist::ReadExReq 17 # Transaction distribution 72611731Sjason@lowepower.comsystem.membus.trans_dist::ReadExResp 17 # Transaction distribution 72711731Sjason@lowepower.comsystem.membus.trans_dist::ReadSharedReq 171 # Transaction distribution 72811731Sjason@lowepower.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 376 # Packet count per connected master and slave (bytes) 72911731Sjason@lowepower.comsystem.membus.pkt_count::total 376 # Packet count per connected master and slave (bytes) 73011731Sjason@lowepower.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 12032 # Cumulative packet size per connected master and slave (bytes) 73111731Sjason@lowepower.comsystem.membus.pkt_size::total 12032 # Cumulative packet size per connected master and slave (bytes) 73211731Sjason@lowepower.comsystem.membus.snoops 0 # Total snoops (count) 73311731Sjason@lowepower.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 73411731Sjason@lowepower.comsystem.membus.snoop_fanout::samples 188 # Request fanout histogram 73511731Sjason@lowepower.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 73611731Sjason@lowepower.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 73711731Sjason@lowepower.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 73811731Sjason@lowepower.comsystem.membus.snoop_fanout::0 188 100.00% 100.00% # Request fanout histogram 73911731Sjason@lowepower.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 74011731Sjason@lowepower.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 74111731Sjason@lowepower.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 74211731Sjason@lowepower.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 74311731Sjason@lowepower.comsystem.membus.snoop_fanout::total 188 # Request fanout histogram 74411731Sjason@lowepower.comsystem.membus.reqLayer0.occupancy 217500 # Layer occupancy (ticks) 74511731Sjason@lowepower.comsystem.membus.reqLayer0.utilization 1.5 # Layer utilization (%) 74611731Sjason@lowepower.comsystem.membus.respLayer1.occupancy 991750 # Layer occupancy (ticks) 74711731Sjason@lowepower.comsystem.membus.respLayer1.utilization 6.9 # Layer utilization (%) 74811731Sjason@lowepower.com 74911731Sjason@lowepower.com---------- End Simulation Statistics ---------- 750