config.json revision 11731:c473ca7cc650
1{ 2 "name": null, 3 "sim_quantum": 0, 4 "system": { 5 "kernel": "", 6 "mmap_using_noreserve": false, 7 "kernel_addr_check": true, 8 "membus": { 9 "point_of_coherency": true, 10 "system": "system", 11 "response_latency": 2, 12 "cxx_class": "CoherentXBar", 13 "forward_latency": 4, 14 "clk_domain": "system.clk_domain", 15 "width": 16, 16 "eventq_index": 0, 17 "default_p_state": "UNDEFINED", 18 "p_state_clk_gate_max": 1000000000000, 19 "master": { 20 "peer": [ 21 "system.physmem.port" 22 ], 23 "role": "MASTER" 24 }, 25 "type": "CoherentXBar", 26 "frontend_latency": 3, 27 "slave": { 28 "peer": [ 29 "system.system_port", 30 "system.cpu.l2cache.mem_side" 31 ], 32 "role": "SLAVE" 33 }, 34 "p_state_clk_gate_min": 1000, 35 "snoop_filter": { 36 "name": "snoop_filter", 37 "system": "system", 38 "max_capacity": 8388608, 39 "eventq_index": 0, 40 "cxx_class": "SnoopFilter", 41 "path": "system.membus.snoop_filter", 42 "type": "SnoopFilter", 43 "lookup_latency": 1 44 }, 45 "power_model": null, 46 "path": "system.membus", 47 "snoop_response_latency": 4, 48 "name": "membus", 49 "p_state_clk_gate_bins": 20, 50 "use_default_range": false 51 }, 52 "symbolfile": "", 53 "readfile": "", 54 "thermal_model": null, 55 "cxx_class": "System", 56 "work_begin_cpu_id_exit": -1, 57 "load_offset": 0, 58 "work_begin_exit_count": 0, 59 "p_state_clk_gate_min": 1000, 60 "memories": [ 61 "system.physmem" 62 ], 63 "work_begin_ckpt_count": 0, 64 "clk_domain": { 65 "name": "clk_domain", 66 "clock": [ 67 1000 68 ], 69 "init_perf_level": 0, 70 "voltage_domain": "system.voltage_domain", 71 "eventq_index": 0, 72 "cxx_class": "SrcClockDomain", 73 "path": "system.clk_domain", 74 "type": "SrcClockDomain", 75 "domain_id": -1 76 }, 77 "mem_ranges": [], 78 "eventq_index": 0, 79 "default_p_state": "UNDEFINED", 80 "p_state_clk_gate_max": 1000000000000, 81 "dvfs_handler": { 82 "enable": false, 83 "name": "dvfs_handler", 84 "sys_clk_domain": "system.clk_domain", 85 "transition_latency": 100000000, 86 "eventq_index": 0, 87 "cxx_class": "DVFSHandler", 88 "domains": [], 89 "path": "system.dvfs_handler", 90 "type": "DVFSHandler" 91 }, 92 "work_end_exit_count": 0, 93 "type": "System", 94 "voltage_domain": { 95 "name": "voltage_domain", 96 "eventq_index": 0, 97 "voltage": [ 98 "1.0" 99 ], 100 "cxx_class": "VoltageDomain", 101 "path": "system.voltage_domain", 102 "type": "VoltageDomain" 103 }, 104 "cache_line_size": 64, 105 "boot_osflags": "a", 106 "system_port": { 107 "peer": "system.membus.slave[0]", 108 "role": "MASTER" 109 }, 110 "physmem": { 111 "static_frontend_latency": 10000, 112 "tRFC": 260000, 113 "activation_limit": 4, 114 "in_addr_map": true, 115 "IDD3N2": "0.0", 116 "tWTR": 7500, 117 "IDD52": "0.0", 118 "clk_domain": "system.clk_domain", 119 "channels": 1, 120 "write_buffer_size": 64, 121 "device_bus_width": 8, 122 "VDD": "1.5", 123 "write_high_thresh_perc": 85, 124 "cxx_class": "DRAMCtrl", 125 "bank_groups_per_rank": 0, 126 "IDD2N2": "0.0", 127 "port": { 128 "peer": "system.membus.master[0]", 129 "role": "SLAVE" 130 }, 131 "tCCD_L": 0, 132 "IDD2N": "0.032", 133 "p_state_clk_gate_min": 1000, 134 "null": false, 135 "IDD2P1": "0.032", 136 "eventq_index": 0, 137 "tRRD": 6000, 138 "tRTW": 2500, 139 "IDD4R": "0.157", 140 "burst_length": 8, 141 "tRTP": 7500, 142 "IDD4W": "0.125", 143 "tWR": 15000, 144 "banks_per_rank": 8, 145 "devices_per_rank": 8, 146 "IDD2P02": "0.0", 147 "default_p_state": "UNDEFINED", 148 "p_state_clk_gate_max": 1000000000000, 149 "IDD6": "0.02", 150 "IDD5": "0.235", 151 "tRCD": 13750, 152 "type": "DRAMCtrl", 153 "IDD3P02": "0.0", 154 "tRRD_L": 0, 155 "IDD0": "0.055", 156 "IDD62": "0.0", 157 "min_writes_per_switch": 16, 158 "mem_sched_policy": "frfcfs", 159 "IDD02": "0.0", 160 "IDD2P0": "0.0", 161 "ranks_per_channel": 2, 162 "page_policy": "open_adaptive", 163 "IDD4W2": "0.0", 164 "tCS": 2500, 165 "power_model": null, 166 "tCL": 13750, 167 "read_buffer_size": 32, 168 "conf_table_reported": true, 169 "tCK": 1250, 170 "tRAS": 35000, 171 "tRP": 13750, 172 "tBURST": 5000, 173 "path": "system.physmem", 174 "tXP": 6000, 175 "tXS": 270000, 176 "addr_mapping": "RoRaBaCoCh", 177 "IDD3P0": "0.0", 178 "IDD3P1": "0.038", 179 "IDD3N": "0.038", 180 "name": "physmem", 181 "tXSDLL": 0, 182 "device_size": 536870912, 183 "kvm_map": true, 184 "dll": true, 185 "tXAW": 30000, 186 "write_low_thresh_perc": 50, 187 "range": "0:134217727:0:0:0:0", 188 "VDD2": "0.0", 189 "IDD2P12": "0.0", 190 "p_state_clk_gate_bins": 20, 191 "tXPDLL": 0, 192 "IDD4R2": "0.0", 193 "device_rowbuffer_size": 1024, 194 "static_backend_latency": 10000, 195 "max_accesses_per_row": 16, 196 "IDD3P12": "0.0", 197 "tREFI": 7800000 198 }, 199 "power_model": null, 200 "work_cpus_ckpt_count": 0, 201 "thermal_components": [], 202 "path": "system", 203 "cpu_clk_domain": { 204 "name": "cpu_clk_domain", 205 "clock": [ 206 500 207 ], 208 "init_perf_level": 0, 209 "voltage_domain": "system.voltage_domain", 210 "eventq_index": 0, 211 "cxx_class": "SrcClockDomain", 212 "path": "system.cpu_clk_domain", 213 "type": "SrcClockDomain", 214 "domain_id": -1 215 }, 216 "work_end_ckpt_count": 0, 217 "mem_mode": "timing", 218 "name": "system", 219 "init_param": 0, 220 "p_state_clk_gate_bins": 20, 221 "load_addr_mask": 1099511627775, 222 "cpu": [ 223 { 224 "max_insts_any_thread": 0, 225 "do_statistics_insts": true, 226 "numThreads": 1, 227 "fetch1LineSnapWidth": 0, 228 "fetch1ToFetch2BackwardDelay": 1, 229 "fetch1FetchLimit": 1, 230 "executeIssueLimit": 2, 231 "system": "system", 232 "executeLSQMaxStoreBufferStoresPerCycle": 2, 233 "icache": { 234 "cpu_side": { 235 "peer": "system.cpu.icache_port", 236 "role": "SLAVE" 237 }, 238 "clusivity": "mostly_incl", 239 "prefetcher": null, 240 "system": "system", 241 "write_buffers": 8, 242 "response_latency": 2, 243 "cxx_class": "Cache", 244 "size": 131072, 245 "type": "Cache", 246 "clk_domain": "system.cpu_clk_domain", 247 "max_miss_count": 0, 248 "eventq_index": 0, 249 "default_p_state": "UNDEFINED", 250 "p_state_clk_gate_max": 1000000000000, 251 "mem_side": { 252 "peer": "system.cpu.toL2Bus.slave[0]", 253 "role": "MASTER" 254 }, 255 "mshrs": 4, 256 "writeback_clean": true, 257 "p_state_clk_gate_min": 1000, 258 "tags": { 259 "size": 131072, 260 "tag_latency": 2, 261 "name": "tags", 262 "p_state_clk_gate_min": 1000, 263 "eventq_index": 0, 264 "p_state_clk_gate_bins": 20, 265 "default_p_state": "UNDEFINED", 266 "clk_domain": "system.cpu_clk_domain", 267 "power_model": null, 268 "sequential_access": false, 269 "assoc": 2, 270 "cxx_class": "LRU", 271 "p_state_clk_gate_max": 1000000000000, 272 "path": "system.cpu.icache.tags", 273 "block_size": 64, 274 "type": "LRU", 275 "data_latency": 2 276 }, 277 "tgts_per_mshr": 20, 278 "demand_mshr_reserve": 1, 279 "power_model": null, 280 "addr_ranges": [ 281 "0:18446744073709551615:0:0:0:0" 282 ], 283 "is_read_only": true, 284 "prefetch_on_access": false, 285 "path": "system.cpu.icache", 286 "data_latency": 2, 287 "tag_latency": 2, 288 "name": "icache", 289 "p_state_clk_gate_bins": 20, 290 "sequential_access": false, 291 "assoc": 2 292 }, 293 "function_trace": false, 294 "do_checkpoint_insts": true, 295 "decodeInputWidth": 2, 296 "cxx_class": "MinorCPU", 297 "max_loads_all_threads": 0, 298 "executeMemoryIssueLimit": 1, 299 "decodeCycleInput": true, 300 "max_loads_any_thread": 0, 301 "executeLSQTransfersQueueSize": 2, 302 "p_state_clk_gate_max": 1000000000000, 303 "clk_domain": "system.cpu_clk_domain", 304 "function_trace_start": 0, 305 "cpu_id": 0, 306 "checker": null, 307 "eventq_index": 0, 308 "executeMemoryWidth": 0, 309 "default_p_state": "UNDEFINED", 310 "executeBranchDelay": 1, 311 "executeMemoryCommitLimit": 1, 312 "l2cache": { 313 "cpu_side": { 314 "peer": "system.cpu.toL2Bus.master[0]", 315 "role": "SLAVE" 316 }, 317 "clusivity": "mostly_incl", 318 "prefetcher": null, 319 "system": "system", 320 "write_buffers": 8, 321 "response_latency": 20, 322 "cxx_class": "Cache", 323 "size": 2097152, 324 "type": "Cache", 325 "clk_domain": "system.cpu_clk_domain", 326 "max_miss_count": 0, 327 "eventq_index": 0, 328 "default_p_state": "UNDEFINED", 329 "p_state_clk_gate_max": 1000000000000, 330 "mem_side": { 331 "peer": "system.membus.slave[1]", 332 "role": "MASTER" 333 }, 334 "mshrs": 20, 335 "writeback_clean": false, 336 "p_state_clk_gate_min": 1000, 337 "tags": { 338 "size": 2097152, 339 "tag_latency": 20, 340 "name": "tags", 341 "p_state_clk_gate_min": 1000, 342 "eventq_index": 0, 343 "p_state_clk_gate_bins": 20, 344 "default_p_state": "UNDEFINED", 345 "clk_domain": "system.cpu_clk_domain", 346 "power_model": null, 347 "sequential_access": false, 348 "assoc": 8, 349 "cxx_class": "LRU", 350 "p_state_clk_gate_max": 1000000000000, 351 "path": "system.cpu.l2cache.tags", 352 "block_size": 64, 353 "type": "LRU", 354 "data_latency": 20 355 }, 356 "tgts_per_mshr": 12, 357 "demand_mshr_reserve": 1, 358 "power_model": null, 359 "addr_ranges": [ 360 "0:18446744073709551615:0:0:0:0" 361 ], 362 "is_read_only": false, 363 "prefetch_on_access": false, 364 "path": "system.cpu.l2cache", 365 "data_latency": 20, 366 "tag_latency": 20, 367 "name": "l2cache", 368 "p_state_clk_gate_bins": 20, 369 "sequential_access": false, 370 "assoc": 8 371 }, 372 "do_quiesce": true, 373 "type": "MinorCPU", 374 "executeCycleInput": true, 375 "executeAllowEarlyMemoryIssue": true, 376 "executeInputBufferSize": 7, 377 "icache_port": { 378 "peer": "system.cpu.icache.cpu_side", 379 "role": "MASTER" 380 }, 381 "p_state_clk_gate_bins": 20, 382 "socket_id": 0, 383 "progress_interval": 0, 384 "p_state_clk_gate_min": 1000, 385 "toL2Bus": { 386 "point_of_coherency": false, 387 "system": "system", 388 "response_latency": 1, 389 "cxx_class": "CoherentXBar", 390 "forward_latency": 0, 391 "clk_domain": "system.cpu_clk_domain", 392 "width": 32, 393 "eventq_index": 0, 394 "default_p_state": "UNDEFINED", 395 "p_state_clk_gate_max": 1000000000000, 396 "master": { 397 "peer": [ 398 "system.cpu.l2cache.cpu_side" 399 ], 400 "role": "MASTER" 401 }, 402 "type": "CoherentXBar", 403 "frontend_latency": 1, 404 "slave": { 405 "peer": [ 406 "system.cpu.icache.mem_side", 407 "system.cpu.dcache.mem_side" 408 ], 409 "role": "SLAVE" 410 }, 411 "p_state_clk_gate_min": 1000, 412 "snoop_filter": { 413 "name": "snoop_filter", 414 "system": "system", 415 "max_capacity": 8388608, 416 "eventq_index": 0, 417 "cxx_class": "SnoopFilter", 418 "path": "system.cpu.toL2Bus.snoop_filter", 419 "type": "SnoopFilter", 420 "lookup_latency": 0 421 }, 422 "power_model": null, 423 "path": "system.cpu.toL2Bus", 424 "snoop_response_latency": 1, 425 "name": "toL2Bus", 426 "p_state_clk_gate_bins": 20, 427 "use_default_range": false 428 }, 429 "isa": [ 430 { 431 "eventq_index": 0, 432 "path": "system.cpu.isa", 433 "type": "RiscvISA", 434 "name": "isa", 435 "cxx_class": "RiscvISA::ISA" 436 } 437 ], 438 "itb": { 439 "name": "itb", 440 "eventq_index": 0, 441 "cxx_class": "RiscvISA::TLB", 442 "path": "system.cpu.itb", 443 "type": "RiscvTLB", 444 "size": 64 445 }, 446 "interrupts": [ 447 { 448 "eventq_index": 0, 449 "path": "system.cpu.interrupts", 450 "type": "RiscvInterrupts", 451 "name": "interrupts", 452 "cxx_class": "RiscvISA::Interrupts" 453 } 454 ], 455 "dcache_port": { 456 "peer": "system.cpu.dcache.cpu_side", 457 "role": "MASTER" 458 }, 459 "executeFuncUnits": { 460 "name": "executeFuncUnits", 461 "eventq_index": 0, 462 "cxx_class": "MinorFUPool", 463 "path": "system.cpu.executeFuncUnits", 464 "funcUnits": [ 465 { 466 "issueLat": 1, 467 "opLat": 3, 468 "name": "funcUnits0", 469 "cantForwardFromFUIndices": [], 470 "opClasses": { 471 "name": "opClasses", 472 "opClasses": [ 473 { 474 "opClass": "IntAlu", 475 "name": "opClasses", 476 "eventq_index": 0, 477 "cxx_class": "MinorOpClass", 478 "path": "system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses", 479 "type": "MinorOpClass" 480 } 481 ], 482 "eventq_index": 0, 483 "cxx_class": "MinorOpClassSet", 484 "path": "system.cpu.executeFuncUnits.funcUnits0.opClasses", 485 "type": "MinorOpClassSet" 486 }, 487 "eventq_index": 0, 488 "timings": [ 489 { 490 "extraAssumedLat": 0, 491 "description": "Int", 492 "srcRegsRelativeLats": [ 493 2 494 ], 495 "suppress": false, 496 "mask": 0, 497 "extraCommitLat": 0, 498 "eventq_index": 0, 499 "opClasses": { 500 "name": "opClasses", 501 "opClasses": [], 502 "eventq_index": 0, 503 "cxx_class": "MinorOpClassSet", 504 "path": "system.cpu.executeFuncUnits.funcUnits0.timings.opClasses", 505 "type": "MinorOpClassSet" 506 }, 507 "cxx_class": "MinorFUTiming", 508 "path": "system.cpu.executeFuncUnits.funcUnits0.timings", 509 "extraCommitLatExpr": null, 510 "type": "MinorFUTiming", 511 "match": 0, 512 "name": "timings" 513 } 514 ], 515 "cxx_class": "MinorFU", 516 "path": "system.cpu.executeFuncUnits.funcUnits0", 517 "type": "MinorFU" 518 }, 519 { 520 "issueLat": 1, 521 "opLat": 3, 522 "name": "funcUnits1", 523 "cantForwardFromFUIndices": [], 524 "opClasses": { 525 "name": "opClasses", 526 "opClasses": [ 527 { 528 "opClass": "IntAlu", 529 "name": "opClasses", 530 "eventq_index": 0, 531 "cxx_class": "MinorOpClass", 532 "path": "system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses", 533 "type": "MinorOpClass" 534 } 535 ], 536 "eventq_index": 0, 537 "cxx_class": "MinorOpClassSet", 538 "path": "system.cpu.executeFuncUnits.funcUnits1.opClasses", 539 "type": "MinorOpClassSet" 540 }, 541 "eventq_index": 0, 542 "timings": [ 543 { 544 "extraAssumedLat": 0, 545 "description": "Int", 546 "srcRegsRelativeLats": [ 547 2 548 ], 549 "suppress": false, 550 "mask": 0, 551 "extraCommitLat": 0, 552 "eventq_index": 0, 553 "opClasses": { 554 "name": "opClasses", 555 "opClasses": [], 556 "eventq_index": 0, 557 "cxx_class": "MinorOpClassSet", 558 "path": "system.cpu.executeFuncUnits.funcUnits1.timings.opClasses", 559 "type": "MinorOpClassSet" 560 }, 561 "cxx_class": "MinorFUTiming", 562 "path": "system.cpu.executeFuncUnits.funcUnits1.timings", 563 "extraCommitLatExpr": null, 564 "type": "MinorFUTiming", 565 "match": 0, 566 "name": "timings" 567 } 568 ], 569 "cxx_class": "MinorFU", 570 "path": "system.cpu.executeFuncUnits.funcUnits1", 571 "type": "MinorFU" 572 }, 573 { 574 "issueLat": 1, 575 "opLat": 3, 576 "name": "funcUnits2", 577 "cantForwardFromFUIndices": [], 578 "opClasses": { 579 "name": "opClasses", 580 "opClasses": [ 581 { 582 "opClass": "IntMult", 583 "name": "opClasses", 584 "eventq_index": 0, 585 "cxx_class": "MinorOpClass", 586 "path": "system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses", 587 "type": "MinorOpClass" 588 } 589 ], 590 "eventq_index": 0, 591 "cxx_class": "MinorOpClassSet", 592 "path": "system.cpu.executeFuncUnits.funcUnits2.opClasses", 593 "type": "MinorOpClassSet" 594 }, 595 "eventq_index": 0, 596 "timings": [ 597 { 598 "extraAssumedLat": 0, 599 "description": "Mul", 600 "srcRegsRelativeLats": [ 601 0 602 ], 603 "suppress": false, 604 "mask": 0, 605 "extraCommitLat": 0, 606 "eventq_index": 0, 607 "opClasses": { 608 "name": "opClasses", 609 "opClasses": [], 610 "eventq_index": 0, 611 "cxx_class": "MinorOpClassSet", 612 "path": "system.cpu.executeFuncUnits.funcUnits2.timings.opClasses", 613 "type": "MinorOpClassSet" 614 }, 615 "cxx_class": "MinorFUTiming", 616 "path": "system.cpu.executeFuncUnits.funcUnits2.timings", 617 "extraCommitLatExpr": null, 618 "type": "MinorFUTiming", 619 "match": 0, 620 "name": "timings" 621 } 622 ], 623 "cxx_class": "MinorFU", 624 "path": "system.cpu.executeFuncUnits.funcUnits2", 625 "type": "MinorFU" 626 }, 627 { 628 "issueLat": 9, 629 "opLat": 9, 630 "name": "funcUnits3", 631 "cantForwardFromFUIndices": [], 632 "opClasses": { 633 "name": "opClasses", 634 "opClasses": [ 635 { 636 "opClass": "IntDiv", 637 "name": "opClasses", 638 "eventq_index": 0, 639 "cxx_class": "MinorOpClass", 640 "path": "system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses", 641 "type": "MinorOpClass" 642 } 643 ], 644 "eventq_index": 0, 645 "cxx_class": "MinorOpClassSet", 646 "path": "system.cpu.executeFuncUnits.funcUnits3.opClasses", 647 "type": "MinorOpClassSet" 648 }, 649 "eventq_index": 0, 650 "timings": [], 651 "cxx_class": "MinorFU", 652 "path": "system.cpu.executeFuncUnits.funcUnits3", 653 "type": "MinorFU" 654 }, 655 { 656 "issueLat": 1, 657 "opLat": 6, 658 "name": "funcUnits4", 659 "cantForwardFromFUIndices": [], 660 "opClasses": { 661 "name": "opClasses", 662 "opClasses": [ 663 { 664 "opClass": "FloatAdd", 665 "name": "opClasses00", 666 "eventq_index": 0, 667 "cxx_class": "MinorOpClass", 668 "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00", 669 "type": "MinorOpClass" 670 }, 671 { 672 "opClass": "FloatCmp", 673 "name": "opClasses01", 674 "eventq_index": 0, 675 "cxx_class": "MinorOpClass", 676 "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01", 677 "type": "MinorOpClass" 678 }, 679 { 680 "opClass": "FloatCvt", 681 "name": "opClasses02", 682 "eventq_index": 0, 683 "cxx_class": "MinorOpClass", 684 "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02", 685 "type": "MinorOpClass" 686 }, 687 { 688 "opClass": "FloatMisc", 689 "name": "opClasses03", 690 "eventq_index": 0, 691 "cxx_class": "MinorOpClass", 692 "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03", 693 "type": "MinorOpClass" 694 }, 695 { 696 "opClass": "FloatMult", 697 "name": "opClasses04", 698 "eventq_index": 0, 699 "cxx_class": "MinorOpClass", 700 "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04", 701 "type": "MinorOpClass" 702 }, 703 { 704 "opClass": "FloatMultAcc", 705 "name": "opClasses05", 706 "eventq_index": 0, 707 "cxx_class": "MinorOpClass", 708 "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05", 709 "type": "MinorOpClass" 710 }, 711 { 712 "opClass": "FloatDiv", 713 "name": "opClasses06", 714 "eventq_index": 0, 715 "cxx_class": "MinorOpClass", 716 "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06", 717 "type": "MinorOpClass" 718 }, 719 { 720 "opClass": "FloatSqrt", 721 "name": "opClasses07", 722 "eventq_index": 0, 723 "cxx_class": "MinorOpClass", 724 "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07", 725 "type": "MinorOpClass" 726 }, 727 { 728 "opClass": "SimdAdd", 729 "name": "opClasses08", 730 "eventq_index": 0, 731 "cxx_class": "MinorOpClass", 732 "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08", 733 "type": "MinorOpClass" 734 }, 735 { 736 "opClass": "SimdAddAcc", 737 "name": "opClasses09", 738 "eventq_index": 0, 739 "cxx_class": "MinorOpClass", 740 "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09", 741 "type": "MinorOpClass" 742 }, 743 { 744 "opClass": "SimdAlu", 745 "name": "opClasses10", 746 "eventq_index": 0, 747 "cxx_class": "MinorOpClass", 748 "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10", 749 "type": "MinorOpClass" 750 }, 751 { 752 "opClass": "SimdCmp", 753 "name": "opClasses11", 754 "eventq_index": 0, 755 "cxx_class": "MinorOpClass", 756 "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11", 757 "type": "MinorOpClass" 758 }, 759 { 760 "opClass": "SimdCvt", 761 "name": "opClasses12", 762 "eventq_index": 0, 763 "cxx_class": "MinorOpClass", 764 "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12", 765 "type": "MinorOpClass" 766 }, 767 { 768 "opClass": "SimdMisc", 769 "name": "opClasses13", 770 "eventq_index": 0, 771 "cxx_class": "MinorOpClass", 772 "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13", 773 "type": "MinorOpClass" 774 }, 775 { 776 "opClass": "SimdMult", 777 "name": "opClasses14", 778 "eventq_index": 0, 779 "cxx_class": "MinorOpClass", 780 "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14", 781 "type": "MinorOpClass" 782 }, 783 { 784 "opClass": "SimdMultAcc", 785 "name": "opClasses15", 786 "eventq_index": 0, 787 "cxx_class": "MinorOpClass", 788 "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15", 789 "type": "MinorOpClass" 790 }, 791 { 792 "opClass": "SimdShift", 793 "name": "opClasses16", 794 "eventq_index": 0, 795 "cxx_class": "MinorOpClass", 796 "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16", 797 "type": "MinorOpClass" 798 }, 799 { 800 "opClass": "SimdShiftAcc", 801 "name": "opClasses17", 802 "eventq_index": 0, 803 "cxx_class": "MinorOpClass", 804 "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17", 805 "type": "MinorOpClass" 806 }, 807 { 808 "opClass": "SimdSqrt", 809 "name": "opClasses18", 810 "eventq_index": 0, 811 "cxx_class": "MinorOpClass", 812 "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18", 813 "type": "MinorOpClass" 814 }, 815 { 816 "opClass": "SimdFloatAdd", 817 "name": "opClasses19", 818 "eventq_index": 0, 819 "cxx_class": "MinorOpClass", 820 "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19", 821 "type": "MinorOpClass" 822 }, 823 { 824 "opClass": "SimdFloatAlu", 825 "name": "opClasses20", 826 "eventq_index": 0, 827 "cxx_class": "MinorOpClass", 828 "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20", 829 "type": "MinorOpClass" 830 }, 831 { 832 "opClass": "SimdFloatCmp", 833 "name": "opClasses21", 834 "eventq_index": 0, 835 "cxx_class": "MinorOpClass", 836 "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21", 837 "type": "MinorOpClass" 838 }, 839 { 840 "opClass": "SimdFloatCvt", 841 "name": "opClasses22", 842 "eventq_index": 0, 843 "cxx_class": "MinorOpClass", 844 "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22", 845 "type": "MinorOpClass" 846 }, 847 { 848 "opClass": "SimdFloatDiv", 849 "name": "opClasses23", 850 "eventq_index": 0, 851 "cxx_class": "MinorOpClass", 852 "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23", 853 "type": "MinorOpClass" 854 }, 855 { 856 "opClass": "SimdFloatMisc", 857 "name": "opClasses24", 858 "eventq_index": 0, 859 "cxx_class": "MinorOpClass", 860 "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24", 861 "type": "MinorOpClass" 862 }, 863 { 864 "opClass": "SimdFloatMult", 865 "name": "opClasses25", 866 "eventq_index": 0, 867 "cxx_class": "MinorOpClass", 868 "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25", 869 "type": "MinorOpClass" 870 }, 871 { 872 "opClass": "SimdFloatMultAcc", 873 "name": "opClasses26", 874 "eventq_index": 0, 875 "cxx_class": "MinorOpClass", 876 "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26", 877 "type": "MinorOpClass" 878 }, 879 { 880 "opClass": "SimdFloatSqrt", 881 "name": "opClasses27", 882 "eventq_index": 0, 883 "cxx_class": "MinorOpClass", 884 "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27", 885 "type": "MinorOpClass" 886 } 887 ], 888 "eventq_index": 0, 889 "cxx_class": "MinorOpClassSet", 890 "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses", 891 "type": "MinorOpClassSet" 892 }, 893 "eventq_index": 0, 894 "timings": [ 895 { 896 "extraAssumedLat": 0, 897 "description": "FloatSimd", 898 "srcRegsRelativeLats": [ 899 2 900 ], 901 "suppress": false, 902 "mask": 0, 903 "extraCommitLat": 0, 904 "eventq_index": 0, 905 "opClasses": { 906 "name": "opClasses", 907 "opClasses": [], 908 "eventq_index": 0, 909 "cxx_class": "MinorOpClassSet", 910 "path": "system.cpu.executeFuncUnits.funcUnits4.timings.opClasses", 911 "type": "MinorOpClassSet" 912 }, 913 "cxx_class": "MinorFUTiming", 914 "path": "system.cpu.executeFuncUnits.funcUnits4.timings", 915 "extraCommitLatExpr": null, 916 "type": "MinorFUTiming", 917 "match": 0, 918 "name": "timings" 919 } 920 ], 921 "cxx_class": "MinorFU", 922 "path": "system.cpu.executeFuncUnits.funcUnits4", 923 "type": "MinorFU" 924 }, 925 { 926 "issueLat": 1, 927 "opLat": 1, 928 "name": "funcUnits5", 929 "cantForwardFromFUIndices": [], 930 "opClasses": { 931 "name": "opClasses", 932 "opClasses": [ 933 { 934 "opClass": "MemRead", 935 "name": "opClasses0", 936 "eventq_index": 0, 937 "cxx_class": "MinorOpClass", 938 "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0", 939 "type": "MinorOpClass" 940 }, 941 { 942 "opClass": "MemWrite", 943 "name": "opClasses1", 944 "eventq_index": 0, 945 "cxx_class": "MinorOpClass", 946 "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1", 947 "type": "MinorOpClass" 948 }, 949 { 950 "opClass": "FloatMemRead", 951 "name": "opClasses2", 952 "eventq_index": 0, 953 "cxx_class": "MinorOpClass", 954 "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2", 955 "type": "MinorOpClass" 956 }, 957 { 958 "opClass": "FloatMemWrite", 959 "name": "opClasses3", 960 "eventq_index": 0, 961 "cxx_class": "MinorOpClass", 962 "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3", 963 "type": "MinorOpClass" 964 } 965 ], 966 "eventq_index": 0, 967 "cxx_class": "MinorOpClassSet", 968 "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses", 969 "type": "MinorOpClassSet" 970 }, 971 "eventq_index": 0, 972 "timings": [ 973 { 974 "extraAssumedLat": 2, 975 "description": "Mem", 976 "srcRegsRelativeLats": [ 977 1 978 ], 979 "suppress": false, 980 "mask": 0, 981 "extraCommitLat": 0, 982 "eventq_index": 0, 983 "opClasses": { 984 "name": "opClasses", 985 "opClasses": [], 986 "eventq_index": 0, 987 "cxx_class": "MinorOpClassSet", 988 "path": "system.cpu.executeFuncUnits.funcUnits5.timings.opClasses", 989 "type": "MinorOpClassSet" 990 }, 991 "cxx_class": "MinorFUTiming", 992 "path": "system.cpu.executeFuncUnits.funcUnits5.timings", 993 "extraCommitLatExpr": null, 994 "type": "MinorFUTiming", 995 "match": 0, 996 "name": "timings" 997 } 998 ], 999 "cxx_class": "MinorFU", 1000 "path": "system.cpu.executeFuncUnits.funcUnits5", 1001 "type": "MinorFU" 1002 }, 1003 { 1004 "issueLat": 1, 1005 "opLat": 1, 1006 "name": "funcUnits6", 1007 "cantForwardFromFUIndices": [], 1008 "opClasses": { 1009 "name": "opClasses", 1010 "opClasses": [ 1011 { 1012 "opClass": "IprAccess", 1013 "name": "opClasses0", 1014 "eventq_index": 0, 1015 "cxx_class": "MinorOpClass", 1016 "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0", 1017 "type": "MinorOpClass" 1018 }, 1019 { 1020 "opClass": "InstPrefetch", 1021 "name": "opClasses1", 1022 "eventq_index": 0, 1023 "cxx_class": "MinorOpClass", 1024 "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1", 1025 "type": "MinorOpClass" 1026 } 1027 ], 1028 "eventq_index": 0, 1029 "cxx_class": "MinorOpClassSet", 1030 "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses", 1031 "type": "MinorOpClassSet" 1032 }, 1033 "eventq_index": 0, 1034 "timings": [], 1035 "cxx_class": "MinorFU", 1036 "path": "system.cpu.executeFuncUnits.funcUnits6", 1037 "type": "MinorFU" 1038 } 1039 ], 1040 "type": "MinorFUPool" 1041 }, 1042 "switched_out": false, 1043 "power_model": null, 1044 "max_insts_all_threads": 0, 1045 "executeSetTraceTimeOnIssue": false, 1046 "fetch2InputBufferSize": 2, 1047 "profile": 0, 1048 "fetch2ToDecodeForwardDelay": 1, 1049 "executeInputWidth": 2, 1050 "decodeToExecuteForwardDelay": 1, 1051 "executeLSQRequestsQueueSize": 1, 1052 "fetch2CycleInput": true, 1053 "executeMaxAccessesInMemory": 2, 1054 "enableIdling": true, 1055 "executeLSQStoreBufferSize": 5, 1056 "workload": [ 1057 { 1058 "uid": 100, 1059 "pid": 100, 1060 "kvmInSE": false, 1061 "cxx_class": "LiveProcess", 1062 "executable": "/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello", 1063 "drivers": [], 1064 "system": "system", 1065 "gid": 100, 1066 "eventq_index": 0, 1067 "env": [], 1068 "input": "cin", 1069 "ppid": 99, 1070 "type": "LiveProcess", 1071 "cwd": "", 1072 "simpoint": 0, 1073 "euid": 100, 1074 "path": "system.cpu.workload", 1075 "max_stack_size": 67108864, 1076 "name": "workload", 1077 "cmd": [ 1078 "hello" 1079 ], 1080 "errout": "cerr", 1081 "useArchPT": false, 1082 "egid": 100, 1083 "output": "cout" 1084 } 1085 ], 1086 "name": "cpu", 1087 "dtb": { 1088 "name": "dtb", 1089 "eventq_index": 0, 1090 "cxx_class": "RiscvISA::TLB", 1091 "path": "system.cpu.dtb", 1092 "type": "RiscvTLB", 1093 "size": 64 1094 }, 1095 "simpoint_start_insts": [], 1096 "executeSetTraceTimeOnCommit": true, 1097 "tracer": { 1098 "eventq_index": 0, 1099 "path": "system.cpu.tracer", 1100 "type": "ExeTracer", 1101 "name": "tracer", 1102 "cxx_class": "Trace::ExeTracer" 1103 }, 1104 "threadPolicy": "RoundRobin", 1105 "executeCommitLimit": 2, 1106 "fetch1LineWidth": 0, 1107 "branchPred": { 1108 "numThreads": 1, 1109 "BTBEntries": 4096, 1110 "cxx_class": "TournamentBP", 1111 "indirectPathLength": 3, 1112 "globalCtrBits": 2, 1113 "choicePredictorSize": 8192, 1114 "indirectHashGHR": true, 1115 "eventq_index": 0, 1116 "localHistoryTableSize": 2048, 1117 "type": "TournamentBP", 1118 "indirectSets": 256, 1119 "indirectWays": 2, 1120 "choiceCtrBits": 2, 1121 "useIndirect": true, 1122 "localCtrBits": 2, 1123 "path": "system.cpu.branchPred", 1124 "localPredictorSize": 2048, 1125 "RASSize": 16, 1126 "globalPredictorSize": 8192, 1127 "name": "branchPred", 1128 "indirectHashTargets": true, 1129 "instShiftAmt": 2, 1130 "indirectTagSize": 16, 1131 "BTBTagSize": 16 1132 }, 1133 "dcache": { 1134 "cpu_side": { 1135 "peer": "system.cpu.dcache_port", 1136 "role": "SLAVE" 1137 }, 1138 "clusivity": "mostly_incl", 1139 "prefetcher": null, 1140 "system": "system", 1141 "write_buffers": 8, 1142 "response_latency": 2, 1143 "cxx_class": "Cache", 1144 "size": 262144, 1145 "type": "Cache", 1146 "clk_domain": "system.cpu_clk_domain", 1147 "max_miss_count": 0, 1148 "eventq_index": 0, 1149 "default_p_state": "UNDEFINED", 1150 "p_state_clk_gate_max": 1000000000000, 1151 "mem_side": { 1152 "peer": "system.cpu.toL2Bus.slave[1]", 1153 "role": "MASTER" 1154 }, 1155 "mshrs": 4, 1156 "writeback_clean": false, 1157 "p_state_clk_gate_min": 1000, 1158 "tags": { 1159 "size": 262144, 1160 "tag_latency": 2, 1161 "name": "tags", 1162 "p_state_clk_gate_min": 1000, 1163 "eventq_index": 0, 1164 "p_state_clk_gate_bins": 20, 1165 "default_p_state": "UNDEFINED", 1166 "clk_domain": "system.cpu_clk_domain", 1167 "power_model": null, 1168 "sequential_access": false, 1169 "assoc": 2, 1170 "cxx_class": "LRU", 1171 "p_state_clk_gate_max": 1000000000000, 1172 "path": "system.cpu.dcache.tags", 1173 "block_size": 64, 1174 "type": "LRU", 1175 "data_latency": 2 1176 }, 1177 "tgts_per_mshr": 20, 1178 "demand_mshr_reserve": 1, 1179 "power_model": null, 1180 "addr_ranges": [ 1181 "0:18446744073709551615:0:0:0:0" 1182 ], 1183 "is_read_only": false, 1184 "prefetch_on_access": false, 1185 "path": "system.cpu.dcache", 1186 "data_latency": 2, 1187 "tag_latency": 2, 1188 "name": "dcache", 1189 "p_state_clk_gate_bins": 20, 1190 "sequential_access": false, 1191 "assoc": 2 1192 }, 1193 "path": "system.cpu", 1194 "fetch1ToFetch2ForwardDelay": 1, 1195 "decodeInputBufferSize": 3 1196 } 1197 ], 1198 "multi_thread": false, 1199 "exit_on_work_items": false, 1200 "work_item_id": -1, 1201 "num_work_ids": 16 1202 }, 1203 "time_sync_period": 100000000000, 1204 "eventq_index": 0, 1205 "time_sync_spin_threshold": 100000000, 1206 "cxx_class": "Root", 1207 "path": "root", 1208 "time_sync_enable": false, 1209 "type": "Root", 1210 "full_system": false 1211}