stats.txt revision 9797:9cd5f91e7a79
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000018 # Number of seconds simulated 4sim_ticks 18469500 # Number of ticks simulated 5final_tick 18469500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 54927 # Simulator instruction rate (inst/s) 8host_op_rate 54916 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 175080000 # Simulator tick rate (ticks/s) 10host_mem_usage 224296 # Number of bytes of host memory used 11host_seconds 0.11 # Real time elapsed on the host 12sim_insts 5792 # Number of instructions simulated 13sim_ops 5792 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory 16system.physmem.bytes_read::total 28544 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 22080 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 22080 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 345 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 446 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1195484447 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 349982403 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1545466851 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1195484447 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1195484447 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1195484447 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 349982403 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1545466851 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 446 # Total number of read requests seen 31system.physmem.writeReqs 0 # Total number of write requests seen 32system.physmem.cpureqs 446 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 28544 # Total number of bytes read from memory 34system.physmem.bytesWritten 0 # Total number of bytes written to memory 35system.physmem.bytesConsumedRd 28544 # bytesRead derated as per pkt->getSize() 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 39system.physmem.perBankRdReqs::0 70 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 42 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 54 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 59 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 53 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 61 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 52 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 13 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 8 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 28 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 2 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 4 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 73system.physmem.totGap 18341000 # Total gap between requests 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 446 # Categorize read packet sizes 81system.physmem.writePktSize::0 0 # Categorize write packet sizes 82system.physmem.writePktSize::1 0 # Categorize write packet sizes 83system.physmem.writePktSize::2 0 # Categorize write packet sizes 84system.physmem.writePktSize::3 0 # Categorize write packet sizes 85system.physmem.writePktSize::4 0 # Categorize write packet sizes 86system.physmem.writePktSize::5 0 # Categorize write packet sizes 87system.physmem.writePktSize::6 0 # Categorize write packet sizes 88system.physmem.rdQLenPdf::0 248 # What read queue length does an incoming req see 89system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::2 40 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 120system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 121system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 122system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 123system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 124system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 125system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 152system.physmem.bytesPerActivate::samples 66 # Bytes accessed per row activation 153system.physmem.bytesPerActivate::mean 306.424242 # Bytes accessed per row activation 154system.physmem.bytesPerActivate::gmean 157.375410 # Bytes accessed per row activation 155system.physmem.bytesPerActivate::stdev 461.580898 # Bytes accessed per row activation 156system.physmem.bytesPerActivate::64 31 46.97% 46.97% # Bytes accessed per row activation 157system.physmem.bytesPerActivate::128 7 10.61% 57.58% # Bytes accessed per row activation 158system.physmem.bytesPerActivate::192 7 10.61% 68.18% # Bytes accessed per row activation 159system.physmem.bytesPerActivate::256 4 6.06% 74.24% # Bytes accessed per row activation 160system.physmem.bytesPerActivate::320 2 3.03% 77.27% # Bytes accessed per row activation 161system.physmem.bytesPerActivate::384 1 1.52% 78.79% # Bytes accessed per row activation 162system.physmem.bytesPerActivate::448 1 1.52% 80.30% # Bytes accessed per row activation 163system.physmem.bytesPerActivate::512 2 3.03% 83.33% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::576 3 4.55% 87.88% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::704 2 3.03% 90.91% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::960 1 1.52% 92.42% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::1088 2 3.03% 95.45% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::1920 1 1.52% 96.97% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::1984 1 1.52% 98.48% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::2304 1 1.52% 100.00% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::total 66 # Bytes accessed per row activation 172system.physmem.totQLat 1996500 # Total cycles spent in queuing delays 173system.physmem.totMemAccLat 10991500 # Sum of mem lat for all requests 174system.physmem.totBusLat 2230000 # Total cycles spent in databus access 175system.physmem.totBankLat 6765000 # Total cycles spent in bank access 176system.physmem.avgQLat 4476.46 # Average queueing delay per request 177system.physmem.avgBankLat 15168.16 # Average bank access latency per request 178system.physmem.avgBusLat 5000.00 # Average bus latency per request 179system.physmem.avgMemAccLat 24644.62 # Average memory access latency 180system.physmem.avgRdBW 1545.47 # Average achieved read bandwidth in MB/s 181system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 182system.physmem.avgConsumedRdBW 1545.47 # Average consumed read bandwidth in MB/s 183system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 184system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 185system.physmem.busUtil 12.07 # Data bus utilization in percentage 186system.physmem.avgRdQLen 0.60 # Average read queue length over time 187system.physmem.avgWrQLen 0.00 # Average write queue length over time 188system.physmem.readRowHits 380 # Number of row buffer hits during reads 189system.physmem.writeRowHits 0 # Number of row buffer hits during writes 190system.physmem.readRowHitRate 85.20 # Row buffer hit rate for reads 191system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 192system.physmem.avgGap 41123.32 # Average gap between requests 193system.membus.throughput 1545466851 # Throughput (bytes/s) 194system.membus.trans_dist::ReadReq 399 # Transaction distribution 195system.membus.trans_dist::ReadResp 399 # Transaction distribution 196system.membus.trans_dist::ReadExReq 47 # Transaction distribution 197system.membus.trans_dist::ReadExResp 47 # Transaction distribution 198system.membus.pkt_count_system.cpu.l2cache.mem_side 892 # Packet count per connected master and slave (bytes) 199system.membus.pkt_count 892 # Packet count per connected master and slave (bytes) 200system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 28544 # Cumulative packet size per connected master and slave (bytes) 201system.membus.tot_pkt_size 28544 # Cumulative packet size per connected master and slave (bytes) 202system.membus.data_through_bus 28544 # Total data (bytes) 203system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 204system.membus.reqLayer0.occupancy 565000 # Layer occupancy (ticks) 205system.membus.reqLayer0.utilization 3.1 # Layer utilization (%) 206system.membus.respLayer1.occupancy 4183750 # Layer occupancy (ticks) 207system.membus.respLayer1.utilization 22.7 # Layer utilization (%) 208system.cpu.branchPred.lookups 2238 # Number of BP lookups 209system.cpu.branchPred.condPredicted 1804 # Number of conditional branches predicted 210system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect 211system.cpu.branchPred.BTBLookups 1851 # Number of BTB lookups 212system.cpu.branchPred.BTBHits 603 # Number of BTB hits 213system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 214system.cpu.branchPred.BTBHitPct 32.576985 # BTB Hit Percentage 215system.cpu.branchPred.usedRAS 199 # Number of times the RAS was used to get a target. 216system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions. 217system.cpu.dtb.read_hits 0 # DTB read hits 218system.cpu.dtb.read_misses 0 # DTB read misses 219system.cpu.dtb.read_accesses 0 # DTB read accesses 220system.cpu.dtb.write_hits 0 # DTB write hits 221system.cpu.dtb.write_misses 0 # DTB write misses 222system.cpu.dtb.write_accesses 0 # DTB write accesses 223system.cpu.dtb.hits 0 # DTB hits 224system.cpu.dtb.misses 0 # DTB misses 225system.cpu.dtb.accesses 0 # DTB accesses 226system.cpu.itb.read_hits 0 # DTB read hits 227system.cpu.itb.read_misses 0 # DTB read misses 228system.cpu.itb.read_accesses 0 # DTB read accesses 229system.cpu.itb.write_hits 0 # DTB write hits 230system.cpu.itb.write_misses 0 # DTB write misses 231system.cpu.itb.write_accesses 0 # DTB write accesses 232system.cpu.itb.hits 0 # DTB hits 233system.cpu.itb.misses 0 # DTB misses 234system.cpu.itb.accesses 0 # DTB accesses 235system.cpu.workload.num_syscalls 9 # Number of system calls 236system.cpu.numCycles 36940 # number of cpu cycles simulated 237system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 238system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 239system.cpu.fetch.icacheStallCycles 7468 # Number of cycles fetch is stalled on an Icache miss 240system.cpu.fetch.Insts 13161 # Number of instructions fetch has processed 241system.cpu.fetch.Branches 2238 # Number of branches that fetch encountered 242system.cpu.fetch.predictedBranches 802 # Number of branches that fetch has predicted taken 243system.cpu.fetch.Cycles 2263 # Number of cycles fetch has run and was not squashing or blocked 244system.cpu.fetch.SquashCycles 1291 # Number of cycles fetch has spent squashing 245system.cpu.fetch.BlockedCycles 1215 # Number of cycles fetch has spent blocked 246system.cpu.fetch.CacheLines 1814 # Number of cache lines fetched 247system.cpu.fetch.IcacheSquashes 312 # Number of outstanding Icache misses that were squashed 248system.cpu.fetch.rateDist::samples 11808 # Number of instructions fetched each cycle (Total) 249system.cpu.fetch.rateDist::mean 1.114583 # Number of instructions fetched each cycle (Total) 250system.cpu.fetch.rateDist::stdev 2.531247 # Number of instructions fetched each cycle (Total) 251system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 252system.cpu.fetch.rateDist::0 9545 80.84% 80.84% # Number of instructions fetched each cycle (Total) 253system.cpu.fetch.rateDist::1 178 1.51% 82.34% # Number of instructions fetched each cycle (Total) 254system.cpu.fetch.rateDist::2 176 1.49% 83.83% # Number of instructions fetched each cycle (Total) 255system.cpu.fetch.rateDist::3 142 1.20% 85.04% # Number of instructions fetched each cycle (Total) 256system.cpu.fetch.rateDist::4 227 1.92% 86.96% # Number of instructions fetched each cycle (Total) 257system.cpu.fetch.rateDist::5 133 1.13% 88.08% # Number of instructions fetched each cycle (Total) 258system.cpu.fetch.rateDist::6 257 2.18% 90.26% # Number of instructions fetched each cycle (Total) 259system.cpu.fetch.rateDist::7 110 0.93% 91.19% # Number of instructions fetched each cycle (Total) 260system.cpu.fetch.rateDist::8 1040 8.81% 100.00% # Number of instructions fetched each cycle (Total) 261system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 262system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 263system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 264system.cpu.fetch.rateDist::total 11808 # Number of instructions fetched each cycle (Total) 265system.cpu.fetch.branchRate 0.060585 # Number of branch fetches per cycle 266system.cpu.fetch.rate 0.356280 # Number of inst fetches per cycle 267system.cpu.decode.IdleCycles 7545 # Number of cycles decode is idle 268system.cpu.decode.BlockedCycles 1376 # Number of cycles decode is blocked 269system.cpu.decode.RunCycles 2098 # Number of cycles decode is running 270system.cpu.decode.UnblockCycles 80 # Number of cycles decode is unblocking 271system.cpu.decode.SquashCycles 709 # Number of cycles decode is squashing 272system.cpu.decode.BranchResolved 341 # Number of times decode resolved a branch 273system.cpu.decode.BranchMispred 154 # Number of times decode detected a branch misprediction 274system.cpu.decode.DecodedInsts 11726 # Number of instructions handled by decode 275system.cpu.decode.SquashedInsts 436 # Number of squashed instructions handled by decode 276system.cpu.rename.SquashCycles 709 # Number of cycles rename is squashing 277system.cpu.rename.IdleCycles 7731 # Number of cycles rename is idle 278system.cpu.rename.BlockCycles 670 # Number of cycles rename is blocking 279system.cpu.rename.serializeStallCycles 446 # count of cycles rename stalled for serializing inst 280system.cpu.rename.RunCycles 1987 # Number of cycles rename is running 281system.cpu.rename.UnblockCycles 265 # Number of cycles rename is unblocking 282system.cpu.rename.RenamedInsts 11308 # Number of instructions processed by rename 283system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full 284system.cpu.rename.LSQFullEvents 226 # Number of times rename has blocked due to LSQ full 285system.cpu.rename.RenamedOperands 9701 # Number of destination operands rename has renamed 286system.cpu.rename.RenameLookups 18192 # Number of register rename lookups that rename has made 287system.cpu.rename.int_rename_lookups 18137 # Number of integer rename lookups 288system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups 289system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed 290system.cpu.rename.UndoneMaps 4703 # Number of HB maps that are undone due to squashing 291system.cpu.rename.serializingInsts 27 # count of serializing insts renamed 292system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed 293system.cpu.rename.skidInsts 575 # count of insts added to the skid buffer 294system.cpu.memDep0.insertedLoads 2023 # Number of loads inserted to the mem dependence unit. 295system.cpu.memDep0.insertedStores 1831 # Number of stores inserted to the mem dependence unit. 296system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. 297system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores. 298system.cpu.iq.iqInstsAdded 10305 # Number of instructions added to the IQ (excludes non-spec) 299system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ 300system.cpu.iq.iqInstsIssued 8903 # Number of instructions issued 301system.cpu.iq.iqSquashedInstsIssued 241 # Number of squashed instructions issued 302system.cpu.iq.iqSquashedInstsExamined 4250 # Number of squashed instructions iterated over during squash; mainly for profiling 303system.cpu.iq.iqSquashedOperandsExamined 3488 # Number of squashed operands that are examined and possibly removed from graph 304system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed 305system.cpu.iq.issued_per_cycle::samples 11808 # Number of insts issued each cycle 306system.cpu.iq.issued_per_cycle::mean 0.753980 # Number of insts issued each cycle 307system.cpu.iq.issued_per_cycle::stdev 1.485434 # Number of insts issued each cycle 308system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 309system.cpu.iq.issued_per_cycle::0 8446 71.53% 71.53% # Number of insts issued each cycle 310system.cpu.iq.issued_per_cycle::1 1102 9.33% 80.86% # Number of insts issued each cycle 311system.cpu.iq.issued_per_cycle::2 787 6.66% 87.53% # Number of insts issued each cycle 312system.cpu.iq.issued_per_cycle::3 501 4.24% 91.77% # Number of insts issued each cycle 313system.cpu.iq.issued_per_cycle::4 457 3.87% 95.64% # Number of insts issued each cycle 314system.cpu.iq.issued_per_cycle::5 305 2.58% 98.22% # Number of insts issued each cycle 315system.cpu.iq.issued_per_cycle::6 132 1.12% 99.34% # Number of insts issued each cycle 316system.cpu.iq.issued_per_cycle::7 45 0.38% 99.72% # Number of insts issued each cycle 317system.cpu.iq.issued_per_cycle::8 33 0.28% 100.00% # Number of insts issued each cycle 318system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 319system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 320system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 321system.cpu.iq.issued_per_cycle::total 11808 # Number of insts issued each cycle 322system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 323system.cpu.iq.fu_full::IntAlu 8 4.68% 4.68% # attempts to use FU when none available 324system.cpu.iq.fu_full::IntMult 0 0.00% 4.68% # attempts to use FU when none available 325system.cpu.iq.fu_full::IntDiv 0 0.00% 4.68% # attempts to use FU when none available 326system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.68% # attempts to use FU when none available 327system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.68% # attempts to use FU when none available 328system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.68% # attempts to use FU when none available 329system.cpu.iq.fu_full::FloatMult 0 0.00% 4.68% # attempts to use FU when none available 330system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.68% # attempts to use FU when none available 331system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.68% # attempts to use FU when none available 332system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.68% # attempts to use FU when none available 333system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.68% # attempts to use FU when none available 334system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.68% # attempts to use FU when none available 335system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.68% # attempts to use FU when none available 336system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.68% # attempts to use FU when none available 337system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.68% # attempts to use FU when none available 338system.cpu.iq.fu_full::SimdMult 0 0.00% 4.68% # attempts to use FU when none available 339system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.68% # attempts to use FU when none available 340system.cpu.iq.fu_full::SimdShift 0 0.00% 4.68% # attempts to use FU when none available 341system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.68% # attempts to use FU when none available 342system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.68% # attempts to use FU when none available 343system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.68% # attempts to use FU when none available 344system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.68% # attempts to use FU when none available 345system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.68% # attempts to use FU when none available 346system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.68% # attempts to use FU when none available 347system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.68% # attempts to use FU when none available 348system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.68% # attempts to use FU when none available 349system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.68% # attempts to use FU when none available 350system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.68% # attempts to use FU when none available 351system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.68% # attempts to use FU when none available 352system.cpu.iq.fu_full::MemRead 71 41.52% 46.20% # attempts to use FU when none available 353system.cpu.iq.fu_full::MemWrite 92 53.80% 100.00% # attempts to use FU when none available 354system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 355system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 356system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 357system.cpu.iq.FU_type_0::IntAlu 5478 61.53% 61.53% # Type of FU issued 358system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.53% # Type of FU issued 359system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.53% # Type of FU issued 360system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.55% # Type of FU issued 361system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.55% # Type of FU issued 362system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.55% # Type of FU issued 363system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.55% # Type of FU issued 364system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.55% # Type of FU issued 365system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.55% # Type of FU issued 366system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.55% # Type of FU issued 367system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.55% # Type of FU issued 368system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.55% # Type of FU issued 369system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.55% # Type of FU issued 370system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.55% # Type of FU issued 371system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.55% # Type of FU issued 372system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.55% # Type of FU issued 373system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.55% # Type of FU issued 374system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.55% # Type of FU issued 375system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.55% # Type of FU issued 376system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.55% # Type of FU issued 377system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.55% # Type of FU issued 378system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.55% # Type of FU issued 379system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.55% # Type of FU issued 380system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.55% # Type of FU issued 381system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.55% # Type of FU issued 382system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.55% # Type of FU issued 383system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.55% # Type of FU issued 384system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.55% # Type of FU issued 385system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.55% # Type of FU issued 386system.cpu.iq.FU_type_0::MemRead 1796 20.17% 81.73% # Type of FU issued 387system.cpu.iq.FU_type_0::MemWrite 1627 18.27% 100.00% # Type of FU issued 388system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 389system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 390system.cpu.iq.FU_type_0::total 8903 # Type of FU issued 391system.cpu.iq.rate 0.241012 # Inst issue rate 392system.cpu.iq.fu_busy_cnt 171 # FU busy when requested 393system.cpu.iq.fu_busy_rate 0.019207 # FU busy rate (busy events/executed inst) 394system.cpu.iq.int_inst_queue_reads 29964 # Number of integer instruction queue reads 395system.cpu.iq.int_inst_queue_writes 14583 # Number of integer instruction queue writes 396system.cpu.iq.int_inst_queue_wakeup_accesses 8130 # Number of integer instruction queue wakeup accesses 397system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads 398system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes 399system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses 400system.cpu.iq.int_alu_accesses 9040 # Number of integer alu accesses 401system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses 402system.cpu.iew.lsq.thread0.forwLoads 66 # Number of loads that had data forwarded from stores 403system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 404system.cpu.iew.lsq.thread0.squashedLoads 1062 # Number of loads squashed 405system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed 406system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations 407system.cpu.iew.lsq.thread0.squashedStores 785 # Number of stores squashed 408system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 409system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 410system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 411system.cpu.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked 412system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 413system.cpu.iew.iewSquashCycles 709 # Number of cycles IEW is squashing 414system.cpu.iew.iewBlockCycles 457 # Number of cycles IEW is blocking 415system.cpu.iew.iewUnblockCycles 22 # Number of cycles IEW is unblocking 416system.cpu.iew.iewDispatchedInsts 10362 # Number of instructions dispatched to IQ 417system.cpu.iew.iewDispSquashedInsts 55 # Number of squashed instructions skipped by dispatch 418system.cpu.iew.iewDispLoadInsts 2023 # Number of dispatched load instructions 419system.cpu.iew.iewDispStoreInsts 1831 # Number of dispatched store instructions 420system.cpu.iew.iewDispNonSpecInsts 48 # Number of dispatched non-speculative instructions 421system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall 422system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall 423system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations 424system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly 425system.cpu.iew.predictedNotTakenIncorrect 262 # Number of branches that were predicted not taken incorrectly 426system.cpu.iew.branchMispredicts 328 # Number of branch mispredicts detected at execute 427system.cpu.iew.iewExecutedInsts 8502 # Number of executed instructions 428system.cpu.iew.iewExecLoadInsts 1678 # Number of load instructions executed 429system.cpu.iew.iewExecSquashedInsts 401 # Number of squashed instructions skipped in execute 430system.cpu.iew.exec_swp 0 # number of swp insts executed 431system.cpu.iew.exec_nop 0 # number of nop insts executed 432system.cpu.iew.exec_refs 3201 # number of memory reference insts executed 433system.cpu.iew.exec_branches 1351 # Number of branches executed 434system.cpu.iew.exec_stores 1523 # Number of stores executed 435system.cpu.iew.exec_rate 0.230157 # Inst execution rate 436system.cpu.iew.wb_sent 8272 # cumulative count of insts sent to commit 437system.cpu.iew.wb_count 8157 # cumulative count of insts written-back 438system.cpu.iew.wb_producers 4221 # num instructions producing a value 439system.cpu.iew.wb_consumers 6683 # num instructions consuming a value 440system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 441system.cpu.iew.wb_rate 0.220818 # insts written-back per cycle 442system.cpu.iew.wb_fanout 0.631603 # average fanout of values written-back 443system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 444system.cpu.commit.commitSquashedInsts 4576 # The number of squashed insts skipped by commit 445system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards 446system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted 447system.cpu.commit.committed_per_cycle::samples 11099 # Number of insts commited each cycle 448system.cpu.commit.committed_per_cycle::mean 0.521849 # Number of insts commited each cycle 449system.cpu.commit.committed_per_cycle::stdev 1.323963 # Number of insts commited each cycle 450system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 451system.cpu.commit.committed_per_cycle::0 8724 78.60% 78.60% # Number of insts commited each cycle 452system.cpu.commit.committed_per_cycle::1 1004 9.05% 87.65% # Number of insts commited each cycle 453system.cpu.commit.committed_per_cycle::2 606 5.46% 93.11% # Number of insts commited each cycle 454system.cpu.commit.committed_per_cycle::3 271 2.44% 95.55% # Number of insts commited each cycle 455system.cpu.commit.committed_per_cycle::4 170 1.53% 97.08% # Number of insts commited each cycle 456system.cpu.commit.committed_per_cycle::5 108 0.97% 98.05% # Number of insts commited each cycle 457system.cpu.commit.committed_per_cycle::6 70 0.63% 98.68% # Number of insts commited each cycle 458system.cpu.commit.committed_per_cycle::7 45 0.41% 99.09% # Number of insts commited each cycle 459system.cpu.commit.committed_per_cycle::8 101 0.91% 100.00% # Number of insts commited each cycle 460system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 461system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 462system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 463system.cpu.commit.committed_per_cycle::total 11099 # Number of insts commited each cycle 464system.cpu.commit.committedInsts 5792 # Number of instructions committed 465system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed 466system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 467system.cpu.commit.refs 2007 # Number of memory references committed 468system.cpu.commit.loads 961 # Number of loads committed 469system.cpu.commit.membars 7 # Number of memory barriers committed 470system.cpu.commit.branches 1037 # Number of branches committed 471system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. 472system.cpu.commit.int_insts 5698 # Number of committed integer instructions. 473system.cpu.commit.function_calls 103 # Number of function calls committed. 474system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached 475system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 476system.cpu.rob.rob_reads 21366 # The number of ROB reads 477system.cpu.rob.rob_writes 21446 # The number of ROB writes 478system.cpu.timesIdled 245 # Number of times that the entire CPU went into an idle state and unscheduled itself 479system.cpu.idleCycles 25132 # Total number of cycles that the CPU has spent unscheduled due to idling 480system.cpu.committedInsts 5792 # Number of Instructions Simulated 481system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated 482system.cpu.committedInsts_total 5792 # Number of Instructions Simulated 483system.cpu.cpi 6.377762 # CPI: Cycles Per Instruction 484system.cpu.cpi_total 6.377762 # CPI: Total CPI of All Threads 485system.cpu.ipc 0.156795 # IPC: Instructions Per Cycle 486system.cpu.ipc_total 0.156795 # IPC: Total IPC of All Threads 487system.cpu.int_regfile_reads 13474 # number of integer regfile reads 488system.cpu.int_regfile_writes 7049 # number of integer regfile writes 489system.cpu.fp_regfile_reads 25 # number of floating regfile reads 490system.cpu.fp_regfile_writes 2 # number of floating regfile writes 491system.cpu.toL2Bus.throughput 1569723057 # Throughput (bytes/s) 492system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution 493system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution 494system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution 495system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution 496system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 702 # Packet count per connected master and slave (bytes) 497system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 204 # Packet count per connected master and slave (bytes) 498system.cpu.toL2Bus.pkt_count 906 # Packet count per connected master and slave (bytes) 499system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 22464 # Cumulative packet size per connected master and slave (bytes) 500system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 6528 # Cumulative packet size per connected master and slave (bytes) 501system.cpu.toL2Bus.tot_pkt_size 28992 # Cumulative packet size per connected master and slave (bytes) 502system.cpu.toL2Bus.data_through_bus 28992 # Total data (bytes) 503system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 504system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks) 505system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 506system.cpu.toL2Bus.respLayer0.occupancy 590750 # Layer occupancy (ticks) 507system.cpu.toL2Bus.respLayer0.utilization 3.2 # Layer utilization (%) 508system.cpu.toL2Bus.respLayer1.occupancy 163000 # Layer occupancy (ticks) 509system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) 510system.cpu.icache.tags.replacements 0 # number of replacements 511system.cpu.icache.tags.tagsinuse 167.253035 # Cycle average of tags in use 512system.cpu.icache.tags.total_refs 1372 # Total number of references to valid blocks. 513system.cpu.icache.tags.sampled_refs 351 # Sample count of references to valid blocks. 514system.cpu.icache.tags.avg_refs 3.908832 # Average number of references to valid blocks. 515system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 516system.cpu.icache.tags.occ_blocks::cpu.inst 167.253035 # Average occupied blocks per requestor 517system.cpu.icache.tags.occ_percent::cpu.inst 0.081667 # Average percentage of cache occupancy 518system.cpu.icache.tags.occ_percent::total 0.081667 # Average percentage of cache occupancy 519system.cpu.icache.ReadReq_hits::cpu.inst 1372 # number of ReadReq hits 520system.cpu.icache.ReadReq_hits::total 1372 # number of ReadReq hits 521system.cpu.icache.demand_hits::cpu.inst 1372 # number of demand (read+write) hits 522system.cpu.icache.demand_hits::total 1372 # number of demand (read+write) hits 523system.cpu.icache.overall_hits::cpu.inst 1372 # number of overall hits 524system.cpu.icache.overall_hits::total 1372 # number of overall hits 525system.cpu.icache.ReadReq_misses::cpu.inst 442 # number of ReadReq misses 526system.cpu.icache.ReadReq_misses::total 442 # number of ReadReq misses 527system.cpu.icache.demand_misses::cpu.inst 442 # number of demand (read+write) misses 528system.cpu.icache.demand_misses::total 442 # number of demand (read+write) misses 529system.cpu.icache.overall_misses::cpu.inst 442 # number of overall misses 530system.cpu.icache.overall_misses::total 442 # number of overall misses 531system.cpu.icache.ReadReq_miss_latency::cpu.inst 28917500 # number of ReadReq miss cycles 532system.cpu.icache.ReadReq_miss_latency::total 28917500 # number of ReadReq miss cycles 533system.cpu.icache.demand_miss_latency::cpu.inst 28917500 # number of demand (read+write) miss cycles 534system.cpu.icache.demand_miss_latency::total 28917500 # number of demand (read+write) miss cycles 535system.cpu.icache.overall_miss_latency::cpu.inst 28917500 # number of overall miss cycles 536system.cpu.icache.overall_miss_latency::total 28917500 # number of overall miss cycles 537system.cpu.icache.ReadReq_accesses::cpu.inst 1814 # number of ReadReq accesses(hits+misses) 538system.cpu.icache.ReadReq_accesses::total 1814 # number of ReadReq accesses(hits+misses) 539system.cpu.icache.demand_accesses::cpu.inst 1814 # number of demand (read+write) accesses 540system.cpu.icache.demand_accesses::total 1814 # number of demand (read+write) accesses 541system.cpu.icache.overall_accesses::cpu.inst 1814 # number of overall (read+write) accesses 542system.cpu.icache.overall_accesses::total 1814 # number of overall (read+write) accesses 543system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.243660 # miss rate for ReadReq accesses 544system.cpu.icache.ReadReq_miss_rate::total 0.243660 # miss rate for ReadReq accesses 545system.cpu.icache.demand_miss_rate::cpu.inst 0.243660 # miss rate for demand accesses 546system.cpu.icache.demand_miss_rate::total 0.243660 # miss rate for demand accesses 547system.cpu.icache.overall_miss_rate::cpu.inst 0.243660 # miss rate for overall accesses 548system.cpu.icache.overall_miss_rate::total 0.243660 # miss rate for overall accesses 549system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65424.208145 # average ReadReq miss latency 550system.cpu.icache.ReadReq_avg_miss_latency::total 65424.208145 # average ReadReq miss latency 551system.cpu.icache.demand_avg_miss_latency::cpu.inst 65424.208145 # average overall miss latency 552system.cpu.icache.demand_avg_miss_latency::total 65424.208145 # average overall miss latency 553system.cpu.icache.overall_avg_miss_latency::cpu.inst 65424.208145 # average overall miss latency 554system.cpu.icache.overall_avg_miss_latency::total 65424.208145 # average overall miss latency 555system.cpu.icache.blocked_cycles::no_mshrs 433 # number of cycles access was blocked 556system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 557system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked 558system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 559system.cpu.icache.avg_blocked_cycles::no_mshrs 72.166667 # average number of cycles each access was blocked 560system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 561system.cpu.icache.fast_writes 0 # number of fast writes performed 562system.cpu.icache.cache_copies 0 # number of cache copies performed 563system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91 # number of ReadReq MSHR hits 564system.cpu.icache.ReadReq_mshr_hits::total 91 # number of ReadReq MSHR hits 565system.cpu.icache.demand_mshr_hits::cpu.inst 91 # number of demand (read+write) MSHR hits 566system.cpu.icache.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits 567system.cpu.icache.overall_mshr_hits::cpu.inst 91 # number of overall MSHR hits 568system.cpu.icache.overall_mshr_hits::total 91 # number of overall MSHR hits 569system.cpu.icache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses 570system.cpu.icache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses 571system.cpu.icache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses 572system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses 573system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses 574system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses 575system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23457750 # number of ReadReq MSHR miss cycles 576system.cpu.icache.ReadReq_mshr_miss_latency::total 23457750 # number of ReadReq MSHR miss cycles 577system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23457750 # number of demand (read+write) MSHR miss cycles 578system.cpu.icache.demand_mshr_miss_latency::total 23457750 # number of demand (read+write) MSHR miss cycles 579system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23457750 # number of overall MSHR miss cycles 580system.cpu.icache.overall_mshr_miss_latency::total 23457750 # number of overall MSHR miss cycles 581system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193495 # mshr miss rate for ReadReq accesses 582system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193495 # mshr miss rate for ReadReq accesses 583system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193495 # mshr miss rate for demand accesses 584system.cpu.icache.demand_mshr_miss_rate::total 0.193495 # mshr miss rate for demand accesses 585system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193495 # mshr miss rate for overall accesses 586system.cpu.icache.overall_mshr_miss_rate::total 0.193495 # mshr miss rate for overall accesses 587system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66831.196581 # average ReadReq mshr miss latency 588system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66831.196581 # average ReadReq mshr miss latency 589system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66831.196581 # average overall mshr miss latency 590system.cpu.icache.demand_avg_mshr_miss_latency::total 66831.196581 # average overall mshr miss latency 591system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66831.196581 # average overall mshr miss latency 592system.cpu.icache.overall_avg_mshr_miss_latency::total 66831.196581 # average overall mshr miss latency 593system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 594system.cpu.l2cache.tags.replacements 0 # number of replacements 595system.cpu.l2cache.tags.tagsinuse 197.401673 # Cycle average of tags in use 596system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks. 597system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. 598system.cpu.l2cache.tags.avg_refs 0.017544 # Average number of references to valid blocks. 599system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 600system.cpu.l2cache.tags.occ_blocks::cpu.inst 166.141608 # Average occupied blocks per requestor 601system.cpu.l2cache.tags.occ_blocks::cpu.data 31.260065 # Average occupied blocks per requestor 602system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005070 # Average percentage of cache occupancy 603system.cpu.l2cache.tags.occ_percent::cpu.data 0.000954 # Average percentage of cache occupancy 604system.cpu.l2cache.tags.occ_percent::total 0.006024 # Average percentage of cache occupancy 605system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits 606system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits 607system.cpu.l2cache.ReadReq_hits::total 7 # number of ReadReq hits 608system.cpu.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits 609system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits 610system.cpu.l2cache.demand_hits::total 7 # number of demand (read+write) hits 611system.cpu.l2cache.overall_hits::cpu.inst 6 # number of overall hits 612system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits 613system.cpu.l2cache.overall_hits::total 7 # number of overall hits 614system.cpu.l2cache.ReadReq_misses::cpu.inst 345 # number of ReadReq misses 615system.cpu.l2cache.ReadReq_misses::cpu.data 54 # number of ReadReq misses 616system.cpu.l2cache.ReadReq_misses::total 399 # number of ReadReq misses 617system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses 618system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses 619system.cpu.l2cache.demand_misses::cpu.inst 345 # number of demand (read+write) misses 620system.cpu.l2cache.demand_misses::cpu.data 101 # number of demand (read+write) misses 621system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses 622system.cpu.l2cache.overall_misses::cpu.inst 345 # number of overall misses 623system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses 624system.cpu.l2cache.overall_misses::total 446 # number of overall misses 625system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23046250 # number of ReadReq miss cycles 626system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4132250 # number of ReadReq miss cycles 627system.cpu.l2cache.ReadReq_miss_latency::total 27178500 # number of ReadReq miss cycles 628system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3637250 # number of ReadExReq miss cycles 629system.cpu.l2cache.ReadExReq_miss_latency::total 3637250 # number of ReadExReq miss cycles 630system.cpu.l2cache.demand_miss_latency::cpu.inst 23046250 # number of demand (read+write) miss cycles 631system.cpu.l2cache.demand_miss_latency::cpu.data 7769500 # number of demand (read+write) miss cycles 632system.cpu.l2cache.demand_miss_latency::total 30815750 # number of demand (read+write) miss cycles 633system.cpu.l2cache.overall_miss_latency::cpu.inst 23046250 # number of overall miss cycles 634system.cpu.l2cache.overall_miss_latency::cpu.data 7769500 # number of overall miss cycles 635system.cpu.l2cache.overall_miss_latency::total 30815750 # number of overall miss cycles 636system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses) 637system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) 638system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) 639system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses) 640system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses) 641system.cpu.l2cache.demand_accesses::cpu.inst 351 # number of demand (read+write) accesses 642system.cpu.l2cache.demand_accesses::cpu.data 102 # number of demand (read+write) accesses 643system.cpu.l2cache.demand_accesses::total 453 # number of demand (read+write) accesses 644system.cpu.l2cache.overall_accesses::cpu.inst 351 # number of overall (read+write) accesses 645system.cpu.l2cache.overall_accesses::cpu.data 102 # number of overall (read+write) accesses 646system.cpu.l2cache.overall_accesses::total 453 # number of overall (read+write) accesses 647system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.982906 # miss rate for ReadReq accesses 648system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981818 # miss rate for ReadReq accesses 649system.cpu.l2cache.ReadReq_miss_rate::total 0.982759 # miss rate for ReadReq accesses 650system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 651system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 652system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982906 # miss rate for demand accesses 653system.cpu.l2cache.demand_miss_rate::cpu.data 0.990196 # miss rate for demand accesses 654system.cpu.l2cache.demand_miss_rate::total 0.984547 # miss rate for demand accesses 655system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982906 # miss rate for overall accesses 656system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses 657system.cpu.l2cache.overall_miss_rate::total 0.984547 # miss rate for overall accesses 658system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66800.724638 # average ReadReq miss latency 659system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76523.148148 # average ReadReq miss latency 660system.cpu.l2cache.ReadReq_avg_miss_latency::total 68116.541353 # average ReadReq miss latency 661system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77388.297872 # average ReadExReq miss latency 662system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77388.297872 # average ReadExReq miss latency 663system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66800.724638 # average overall miss latency 664system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76925.742574 # average overall miss latency 665system.cpu.l2cache.demand_avg_miss_latency::total 69093.609865 # average overall miss latency 666system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66800.724638 # average overall miss latency 667system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76925.742574 # average overall miss latency 668system.cpu.l2cache.overall_avg_miss_latency::total 69093.609865 # average overall miss latency 669system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 670system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 671system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 672system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 673system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 674system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 675system.cpu.l2cache.fast_writes 0 # number of fast writes performed 676system.cpu.l2cache.cache_copies 0 # number of cache copies performed 677system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 345 # number of ReadReq MSHR misses 678system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses 679system.cpu.l2cache.ReadReq_mshr_misses::total 399 # number of ReadReq MSHR misses 680system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses 681system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses 682system.cpu.l2cache.demand_mshr_misses::cpu.inst 345 # number of demand (read+write) MSHR misses 683system.cpu.l2cache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses 684system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses 685system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses 686system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses 687system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses 688system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18694250 # number of ReadReq MSHR miss cycles 689system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3465750 # number of ReadReq MSHR miss cycles 690system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22160000 # number of ReadReq MSHR miss cycles 691system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3059750 # number of ReadExReq MSHR miss cycles 692system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3059750 # number of ReadExReq MSHR miss cycles 693system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18694250 # number of demand (read+write) MSHR miss cycles 694system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6525500 # number of demand (read+write) MSHR miss cycles 695system.cpu.l2cache.demand_mshr_miss_latency::total 25219750 # number of demand (read+write) MSHR miss cycles 696system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18694250 # number of overall MSHR miss cycles 697system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6525500 # number of overall MSHR miss cycles 698system.cpu.l2cache.overall_mshr_miss_latency::total 25219750 # number of overall MSHR miss cycles 699system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses 700system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses 701system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses 702system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 703system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 704system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for demand accesses 705system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for demand accesses 706system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547 # mshr miss rate for demand accesses 707system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses 708system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses 709system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses 710system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54186.231884 # average ReadReq mshr miss latency 711system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64180.555556 # average ReadReq mshr miss latency 712system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55538.847118 # average ReadReq mshr miss latency 713system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65101.063830 # average ReadExReq mshr miss latency 714system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65101.063830 # average ReadExReq mshr miss latency 715system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54186.231884 # average overall mshr miss latency 716system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64608.910891 # average overall mshr miss latency 717system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56546.524664 # average overall mshr miss latency 718system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54186.231884 # average overall mshr miss latency 719system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64608.910891 # average overall mshr miss latency 720system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56546.524664 # average overall mshr miss latency 721system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 722system.cpu.dcache.tags.replacements 0 # number of replacements 723system.cpu.dcache.tags.tagsinuse 63.117277 # Cycle average of tags in use 724system.cpu.dcache.tags.total_refs 2192 # Total number of references to valid blocks. 725system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. 726system.cpu.dcache.tags.avg_refs 21.490196 # Average number of references to valid blocks. 727system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 728system.cpu.dcache.tags.occ_blocks::cpu.data 63.117277 # Average occupied blocks per requestor 729system.cpu.dcache.tags.occ_percent::cpu.data 0.015409 # Average percentage of cache occupancy 730system.cpu.dcache.tags.occ_percent::total 0.015409 # Average percentage of cache occupancy 731system.cpu.dcache.ReadReq_hits::cpu.data 1473 # number of ReadReq hits 732system.cpu.dcache.ReadReq_hits::total 1473 # number of ReadReq hits 733system.cpu.dcache.WriteReq_hits::cpu.data 719 # number of WriteReq hits 734system.cpu.dcache.WriteReq_hits::total 719 # number of WriteReq hits 735system.cpu.dcache.demand_hits::cpu.data 2192 # number of demand (read+write) hits 736system.cpu.dcache.demand_hits::total 2192 # number of demand (read+write) hits 737system.cpu.dcache.overall_hits::cpu.data 2192 # number of overall hits 738system.cpu.dcache.overall_hits::total 2192 # number of overall hits 739system.cpu.dcache.ReadReq_misses::cpu.data 104 # number of ReadReq misses 740system.cpu.dcache.ReadReq_misses::total 104 # number of ReadReq misses 741system.cpu.dcache.WriteReq_misses::cpu.data 327 # number of WriteReq misses 742system.cpu.dcache.WriteReq_misses::total 327 # number of WriteReq misses 743system.cpu.dcache.demand_misses::cpu.data 431 # number of demand (read+write) misses 744system.cpu.dcache.demand_misses::total 431 # number of demand (read+write) misses 745system.cpu.dcache.overall_misses::cpu.data 431 # number of overall misses 746system.cpu.dcache.overall_misses::total 431 # number of overall misses 747system.cpu.dcache.ReadReq_miss_latency::cpu.data 7388000 # number of ReadReq miss cycles 748system.cpu.dcache.ReadReq_miss_latency::total 7388000 # number of ReadReq miss cycles 749system.cpu.dcache.WriteReq_miss_latency::cpu.data 19896996 # number of WriteReq miss cycles 750system.cpu.dcache.WriteReq_miss_latency::total 19896996 # number of WriteReq miss cycles 751system.cpu.dcache.demand_miss_latency::cpu.data 27284996 # number of demand (read+write) miss cycles 752system.cpu.dcache.demand_miss_latency::total 27284996 # number of demand (read+write) miss cycles 753system.cpu.dcache.overall_miss_latency::cpu.data 27284996 # number of overall miss cycles 754system.cpu.dcache.overall_miss_latency::total 27284996 # number of overall miss cycles 755system.cpu.dcache.ReadReq_accesses::cpu.data 1577 # number of ReadReq accesses(hits+misses) 756system.cpu.dcache.ReadReq_accesses::total 1577 # number of ReadReq accesses(hits+misses) 757system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) 758system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) 759system.cpu.dcache.demand_accesses::cpu.data 2623 # number of demand (read+write) accesses 760system.cpu.dcache.demand_accesses::total 2623 # number of demand (read+write) accesses 761system.cpu.dcache.overall_accesses::cpu.data 2623 # number of overall (read+write) accesses 762system.cpu.dcache.overall_accesses::total 2623 # number of overall (read+write) accesses 763system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065948 # miss rate for ReadReq accesses 764system.cpu.dcache.ReadReq_miss_rate::total 0.065948 # miss rate for ReadReq accesses 765system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.312620 # miss rate for WriteReq accesses 766system.cpu.dcache.WriteReq_miss_rate::total 0.312620 # miss rate for WriteReq accesses 767system.cpu.dcache.demand_miss_rate::cpu.data 0.164316 # miss rate for demand accesses 768system.cpu.dcache.demand_miss_rate::total 0.164316 # miss rate for demand accesses 769system.cpu.dcache.overall_miss_rate::cpu.data 0.164316 # miss rate for overall accesses 770system.cpu.dcache.overall_miss_rate::total 0.164316 # miss rate for overall accesses 771system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71038.461538 # average ReadReq miss latency 772system.cpu.dcache.ReadReq_avg_miss_latency::total 71038.461538 # average ReadReq miss latency 773system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60847.082569 # average WriteReq miss latency 774system.cpu.dcache.WriteReq_avg_miss_latency::total 60847.082569 # average WriteReq miss latency 775system.cpu.dcache.demand_avg_miss_latency::cpu.data 63306.255220 # average overall miss latency 776system.cpu.dcache.demand_avg_miss_latency::total 63306.255220 # average overall miss latency 777system.cpu.dcache.overall_avg_miss_latency::cpu.data 63306.255220 # average overall miss latency 778system.cpu.dcache.overall_avg_miss_latency::total 63306.255220 # average overall miss latency 779system.cpu.dcache.blocked_cycles::no_mshrs 501 # number of cycles access was blocked 780system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 781system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked 782system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 783system.cpu.dcache.avg_blocked_cycles::no_mshrs 100.200000 # average number of cycles each access was blocked 784system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 785system.cpu.dcache.fast_writes 0 # number of fast writes performed 786system.cpu.dcache.cache_copies 0 # number of cache copies performed 787system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits 788system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits 789system.cpu.dcache.WriteReq_mshr_hits::cpu.data 280 # number of WriteReq MSHR hits 790system.cpu.dcache.WriteReq_mshr_hits::total 280 # number of WriteReq MSHR hits 791system.cpu.dcache.demand_mshr_hits::cpu.data 329 # number of demand (read+write) MSHR hits 792system.cpu.dcache.demand_mshr_hits::total 329 # number of demand (read+write) MSHR hits 793system.cpu.dcache.overall_mshr_hits::cpu.data 329 # number of overall MSHR hits 794system.cpu.dcache.overall_mshr_hits::total 329 # number of overall MSHR hits 795system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses 796system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses 797system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses 798system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses 799system.cpu.dcache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses 800system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses 801system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses 802system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses 803system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4197750 # number of ReadReq MSHR miss cycles 804system.cpu.dcache.ReadReq_mshr_miss_latency::total 4197750 # number of ReadReq MSHR miss cycles 805system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3687248 # number of WriteReq MSHR miss cycles 806system.cpu.dcache.WriteReq_mshr_miss_latency::total 3687248 # number of WriteReq MSHR miss cycles 807system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7884998 # number of demand (read+write) MSHR miss cycles 808system.cpu.dcache.demand_mshr_miss_latency::total 7884998 # number of demand (read+write) MSHR miss cycles 809system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7884998 # number of overall MSHR miss cycles 810system.cpu.dcache.overall_mshr_miss_latency::total 7884998 # number of overall MSHR miss cycles 811system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for ReadReq accesses 812system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034876 # mshr miss rate for ReadReq accesses 813system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses 814system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses 815system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038887 # mshr miss rate for demand accesses 816system.cpu.dcache.demand_mshr_miss_rate::total 0.038887 # mshr miss rate for demand accesses 817system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038887 # mshr miss rate for overall accesses 818system.cpu.dcache.overall_mshr_miss_rate::total 0.038887 # mshr miss rate for overall accesses 819system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76322.727273 # average ReadReq mshr miss latency 820system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76322.727273 # average ReadReq mshr miss latency 821system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78452.085106 # average WriteReq mshr miss latency 822system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78452.085106 # average WriteReq mshr miss latency 823system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77303.901961 # average overall mshr miss latency 824system.cpu.dcache.demand_avg_mshr_miss_latency::total 77303.901961 # average overall mshr miss latency 825system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77303.901961 # average overall mshr miss latency 826system.cpu.dcache.overall_avg_mshr_miss_latency::total 77303.901961 # average overall mshr miss latency 827system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 828 829---------- End Simulation Statistics ---------- 830