stats.txt revision 6692
1 2---------- Begin Simulation Statistics ---------- 3host_inst_rate 103409 # Simulator instruction rate (inst/s) 4host_mem_usage 271924 # Number of bytes of host memory used 5host_seconds 0.06 # Real time elapsed on the host 6host_tick_rate 212174700 # Simulator tick rate (ticks/s) 7sim_freq 1000000000000 # Frequency of simulated ticks 8sim_insts 5800 # Number of instructions simulated 9sim_seconds 0.000012 # Number of seconds simulated 10sim_ticks 11960500 # Number of ticks simulated 11system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 12system.cpu.BPredUnit.BTBHits 734 # Number of BTB hits 13system.cpu.BPredUnit.BTBLookups 1942 # Number of BTB lookups 14system.cpu.BPredUnit.RASInCorrect 31 # Number of incorrect RAS predictions. 15system.cpu.BPredUnit.condIncorrect 389 # Number of conditional branches incorrect 16system.cpu.BPredUnit.condPredicted 1971 # Number of conditional branches predicted 17system.cpu.BPredUnit.lookups 2303 # Number of BP lookups 18system.cpu.BPredUnit.usedRAS 188 # Number of times the RAS was used to get a target. 19system.cpu.commit.COM:branches 1038 # Number of branches committed 20system.cpu.commit.COM:bw_lim_events 51 # number cycles where commit BW limit reached 21system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits 22system.cpu.commit.COM:committed_per_cycle::samples 10831 # Number of insts commited each cycle 23system.cpu.commit.COM:committed_per_cycle::mean 0.535500 # Number of insts commited each cycle 24system.cpu.commit.COM:committed_per_cycle::stdev 1.248160 # Number of insts commited each cycle 25system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 26system.cpu.commit.COM:committed_per_cycle::0-1 8265 76.31% 76.31% # Number of insts commited each cycle 27system.cpu.commit.COM:committed_per_cycle::1-2 1142 10.54% 86.85% # Number of insts commited each cycle 28system.cpu.commit.COM:committed_per_cycle::2-3 659 6.08% 92.94% # Number of insts commited each cycle 29system.cpu.commit.COM:committed_per_cycle::3-4 268 2.47% 95.41% # Number of insts commited each cycle 30system.cpu.commit.COM:committed_per_cycle::4-5 226 2.09% 97.50% # Number of insts commited each cycle 31system.cpu.commit.COM:committed_per_cycle::5-6 118 1.09% 98.59% # Number of insts commited each cycle 32system.cpu.commit.COM:committed_per_cycle::6-7 80 0.74% 99.33% # Number of insts commited each cycle 33system.cpu.commit.COM:committed_per_cycle::7-8 22 0.20% 99.53% # Number of insts commited each cycle 34system.cpu.commit.COM:committed_per_cycle::8 51 0.47% 100.00% # Number of insts commited each cycle 35system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 36system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle 37system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle 38system.cpu.commit.COM:committed_per_cycle::total 10831 # Number of insts commited each cycle 39system.cpu.commit.COM:count 5800 # Number of instructions committed 40system.cpu.commit.COM:loads 962 # Number of loads committed 41system.cpu.commit.COM:membars 7 # Number of memory barriers committed 42system.cpu.commit.COM:refs 2008 # Number of memory references committed 43system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed 44system.cpu.commit.branchMispredicts 243 # The number of times a branch was mispredicted 45system.cpu.commit.commitCommittedInsts 5800 # The number of committed instructions 46system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards 47system.cpu.commit.commitSquashedInsts 3801 # The number of squashed insts skipped by commit 48system.cpu.committedInsts 5800 # Number of Instructions Simulated 49system.cpu.committedInsts_total 5800 # Number of Instructions Simulated 50system.cpu.cpi 4.124483 # CPI: Cycles Per Instruction 51system.cpu.cpi_total 4.124483 # CPI: Total CPI of All Threads 52system.cpu.dcache.ReadReq_accesses 1436 # number of ReadReq accesses(hits+misses) 53system.cpu.dcache.ReadReq_avg_miss_latency 33320.224719 # average ReadReq miss latency 54system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34437.500000 # average ReadReq mshr miss latency 55system.cpu.dcache.ReadReq_hits 1347 # number of ReadReq hits 56system.cpu.dcache.ReadReq_miss_latency 2965500 # number of ReadReq miss cycles 57system.cpu.dcache.ReadReq_miss_rate 0.061978 # miss rate for ReadReq accesses 58system.cpu.dcache.ReadReq_misses 89 # number of ReadReq misses 59system.cpu.dcache.ReadReq_mshr_hits 33 # number of ReadReq MSHR hits 60system.cpu.dcache.ReadReq_mshr_miss_latency 1928500 # number of ReadReq MSHR miss cycles 61system.cpu.dcache.ReadReq_mshr_miss_rate 0.038997 # mshr miss rate for ReadReq accesses 62system.cpu.dcache.ReadReq_mshr_misses 56 # number of ReadReq MSHR misses 63system.cpu.dcache.WriteReq_accesses 1046 # number of WriteReq accesses(hits+misses) 64system.cpu.dcache.WriteReq_avg_miss_latency 33497.150997 # average WriteReq miss latency 65system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35861.538462 # average WriteReq mshr miss latency 66system.cpu.dcache.WriteReq_hits 695 # number of WriteReq hits 67system.cpu.dcache.WriteReq_miss_latency 11757500 # number of WriteReq miss cycles 68system.cpu.dcache.WriteReq_miss_rate 0.335564 # miss rate for WriteReq accesses 69system.cpu.dcache.WriteReq_misses 351 # number of WriteReq misses 70system.cpu.dcache.WriteReq_mshr_hits 286 # number of WriteReq MSHR hits 71system.cpu.dcache.WriteReq_mshr_miss_latency 2331000 # number of WriteReq MSHR miss cycles 72system.cpu.dcache.WriteReq_mshr_miss_rate 0.062141 # mshr miss rate for WriteReq accesses 73system.cpu.dcache.WriteReq_mshr_misses 65 # number of WriteReq MSHR misses 74system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 75system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 76system.cpu.dcache.avg_refs 20.048077 # Average number of references to valid blocks. 77system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 78system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 79system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 80system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 81system.cpu.dcache.cache_copies 0 # number of cache copies performed 82system.cpu.dcache.demand_accesses 2482 # number of demand (read+write) accesses 83system.cpu.dcache.demand_avg_miss_latency 33461.363636 # average overall miss latency 84system.cpu.dcache.demand_avg_mshr_miss_latency 35202.479339 # average overall mshr miss latency 85system.cpu.dcache.demand_hits 2042 # number of demand (read+write) hits 86system.cpu.dcache.demand_miss_latency 14723000 # number of demand (read+write) miss cycles 87system.cpu.dcache.demand_miss_rate 0.177276 # miss rate for demand accesses 88system.cpu.dcache.demand_misses 440 # number of demand (read+write) misses 89system.cpu.dcache.demand_mshr_hits 319 # number of demand (read+write) MSHR hits 90system.cpu.dcache.demand_mshr_miss_latency 4259500 # number of demand (read+write) MSHR miss cycles 91system.cpu.dcache.demand_mshr_miss_rate 0.048751 # mshr miss rate for demand accesses 92system.cpu.dcache.demand_mshr_misses 121 # number of demand (read+write) MSHR misses 93system.cpu.dcache.fast_writes 0 # number of fast writes performed 94system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 95system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 96system.cpu.dcache.overall_accesses 2482 # number of overall (read+write) accesses 97system.cpu.dcache.overall_avg_miss_latency 33461.363636 # average overall miss latency 98system.cpu.dcache.overall_avg_mshr_miss_latency 35202.479339 # average overall mshr miss latency 99system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 100system.cpu.dcache.overall_hits 2042 # number of overall hits 101system.cpu.dcache.overall_miss_latency 14723000 # number of overall miss cycles 102system.cpu.dcache.overall_miss_rate 0.177276 # miss rate for overall accesses 103system.cpu.dcache.overall_misses 440 # number of overall misses 104system.cpu.dcache.overall_mshr_hits 319 # number of overall MSHR hits 105system.cpu.dcache.overall_mshr_miss_latency 4259500 # number of overall MSHR miss cycles 106system.cpu.dcache.overall_mshr_miss_rate 0.048751 # mshr miss rate for overall accesses 107system.cpu.dcache.overall_mshr_misses 121 # number of overall MSHR misses 108system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 109system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 110system.cpu.dcache.replacements 0 # number of replacements 111system.cpu.dcache.sampled_refs 104 # Sample count of references to valid blocks. 112system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 113system.cpu.dcache.tagsinuse 66.056188 # Cycle average of tags in use 114system.cpu.dcache.total_refs 2085 # Total number of references to valid blocks. 115system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 116system.cpu.dcache.writebacks 0 # number of writebacks 117system.cpu.decode.DECODE:BlockedCycles 1201 # Number of cycles decode is blocked 118system.cpu.decode.DECODE:BranchMispred 148 # Number of times decode detected a branch misprediction 119system.cpu.decode.DECODE:BranchResolved 256 # Number of times decode resolved a branch 120system.cpu.decode.DECODE:DecodedInsts 10901 # Number of instructions handled by decode 121system.cpu.decode.DECODE:IdleCycles 7556 # Number of cycles decode is idle 122system.cpu.decode.DECODE:RunCycles 2000 # Number of cycles decode is running 123system.cpu.decode.DECODE:SquashCycles 615 # Number of cycles decode is squashing 124system.cpu.decode.DECODE:SquashedInsts 416 # Number of squashed instructions handled by decode 125system.cpu.decode.DECODE:UnblockCycles 74 # Number of cycles decode is unblocking 126system.cpu.dtb.accesses 0 # DTB accesses 127system.cpu.dtb.hits 0 # DTB hits 128system.cpu.dtb.misses 0 # DTB misses 129system.cpu.dtb.read_accesses 0 # DTB read accesses 130system.cpu.dtb.read_hits 0 # DTB read hits 131system.cpu.dtb.read_misses 0 # DTB read misses 132system.cpu.dtb.write_accesses 0 # DTB write accesses 133system.cpu.dtb.write_hits 0 # DTB write hits 134system.cpu.dtb.write_misses 0 # DTB write misses 135system.cpu.fetch.Branches 2303 # Number of branches that fetch encountered 136system.cpu.fetch.CacheLines 1463 # Number of cache lines fetched 137system.cpu.fetch.Cycles 3604 # Number of cycles fetch has run and was not squashing or blocked 138system.cpu.fetch.IcacheSquashes 216 # Number of outstanding Icache misses that were squashed 139system.cpu.fetch.Insts 12241 # Number of instructions fetch has processed 140system.cpu.fetch.SquashCycles 411 # Number of cycles fetch has spent squashing 141system.cpu.fetch.branchRate 0.096271 # Number of branch fetches per cycle 142system.cpu.fetch.icacheStallCycles 1463 # Number of cycles fetch is stalled on an Icache miss 143system.cpu.fetch.predictedBranches 922 # Number of branches that fetch has predicted taken 144system.cpu.fetch.rate 0.511705 # Number of inst fetches per cycle 145system.cpu.fetch.rateDist::samples 11446 # Number of instructions fetched each cycle (Total) 146system.cpu.fetch.rateDist::mean 1.069457 # Number of instructions fetched each cycle (Total) 147system.cpu.fetch.rateDist::stdev 2.458316 # Number of instructions fetched each cycle (Total) 148system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 149system.cpu.fetch.rateDist::0-1 9306 81.30% 81.30% # Number of instructions fetched each cycle (Total) 150system.cpu.fetch.rateDist::1-2 148 1.29% 82.60% # Number of instructions fetched each cycle (Total) 151system.cpu.fetch.rateDist::2-3 183 1.60% 84.20% # Number of instructions fetched each cycle (Total) 152system.cpu.fetch.rateDist::3-4 143 1.25% 85.44% # Number of instructions fetched each cycle (Total) 153system.cpu.fetch.rateDist::4-5 197 1.72% 87.17% # Number of instructions fetched each cycle (Total) 154system.cpu.fetch.rateDist::5-6 135 1.18% 88.35% # Number of instructions fetched each cycle (Total) 155system.cpu.fetch.rateDist::6-7 371 3.24% 91.59% # Number of instructions fetched each cycle (Total) 156system.cpu.fetch.rateDist::7-8 95 0.83% 92.42% # Number of instructions fetched each cycle (Total) 157system.cpu.fetch.rateDist::8 868 7.58% 100.00% # Number of instructions fetched each cycle (Total) 158system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 159system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 160system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 161system.cpu.fetch.rateDist::total 11446 # Number of instructions fetched each cycle (Total) 162system.cpu.icache.ReadReq_accesses 1463 # number of ReadReq accesses(hits+misses) 163system.cpu.icache.ReadReq_avg_miss_latency 36616.094987 # average ReadReq miss latency 164system.cpu.icache.ReadReq_avg_mshr_miss_latency 34771.212121 # average ReadReq mshr miss latency 165system.cpu.icache.ReadReq_hits 1084 # number of ReadReq hits 166system.cpu.icache.ReadReq_miss_latency 13877500 # number of ReadReq miss cycles 167system.cpu.icache.ReadReq_miss_rate 0.259057 # miss rate for ReadReq accesses 168system.cpu.icache.ReadReq_misses 379 # number of ReadReq misses 169system.cpu.icache.ReadReq_mshr_hits 49 # number of ReadReq MSHR hits 170system.cpu.icache.ReadReq_mshr_miss_latency 11474500 # number of ReadReq MSHR miss cycles 171system.cpu.icache.ReadReq_mshr_miss_rate 0.225564 # mshr miss rate for ReadReq accesses 172system.cpu.icache.ReadReq_mshr_misses 330 # number of ReadReq MSHR misses 173system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 174system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 175system.cpu.icache.avg_refs 3.284848 # Average number of references to valid blocks. 176system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 177system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 178system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 179system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 180system.cpu.icache.cache_copies 0 # number of cache copies performed 181system.cpu.icache.demand_accesses 1463 # number of demand (read+write) accesses 182system.cpu.icache.demand_avg_miss_latency 36616.094987 # average overall miss latency 183system.cpu.icache.demand_avg_mshr_miss_latency 34771.212121 # average overall mshr miss latency 184system.cpu.icache.demand_hits 1084 # number of demand (read+write) hits 185system.cpu.icache.demand_miss_latency 13877500 # number of demand (read+write) miss cycles 186system.cpu.icache.demand_miss_rate 0.259057 # miss rate for demand accesses 187system.cpu.icache.demand_misses 379 # number of demand (read+write) misses 188system.cpu.icache.demand_mshr_hits 49 # number of demand (read+write) MSHR hits 189system.cpu.icache.demand_mshr_miss_latency 11474500 # number of demand (read+write) MSHR miss cycles 190system.cpu.icache.demand_mshr_miss_rate 0.225564 # mshr miss rate for demand accesses 191system.cpu.icache.demand_mshr_misses 330 # number of demand (read+write) MSHR misses 192system.cpu.icache.fast_writes 0 # number of fast writes performed 193system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 194system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 195system.cpu.icache.overall_accesses 1463 # number of overall (read+write) accesses 196system.cpu.icache.overall_avg_miss_latency 36616.094987 # average overall miss latency 197system.cpu.icache.overall_avg_mshr_miss_latency 34771.212121 # average overall mshr miss latency 198system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 199system.cpu.icache.overall_hits 1084 # number of overall hits 200system.cpu.icache.overall_miss_latency 13877500 # number of overall miss cycles 201system.cpu.icache.overall_miss_rate 0.259057 # miss rate for overall accesses 202system.cpu.icache.overall_misses 379 # number of overall misses 203system.cpu.icache.overall_mshr_hits 49 # number of overall MSHR hits 204system.cpu.icache.overall_mshr_miss_latency 11474500 # number of overall MSHR miss cycles 205system.cpu.icache.overall_mshr_miss_rate 0.225564 # mshr miss rate for overall accesses 206system.cpu.icache.overall_mshr_misses 330 # number of overall MSHR misses 207system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 208system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 209system.cpu.icache.replacements 0 # number of replacements 210system.cpu.icache.sampled_refs 330 # Sample count of references to valid blocks. 211system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 212system.cpu.icache.tagsinuse 159.198376 # Cycle average of tags in use 213system.cpu.icache.total_refs 1084 # Total number of references to valid blocks. 214system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 215system.cpu.icache.writebacks 0 # number of writebacks 216system.cpu.idleCycles 12476 # Total number of cycles that the CPU has spent unscheduled due to idling 217system.cpu.iew.EXEC:branches 1260 # Number of branches executed 218system.cpu.iew.EXEC:nop 0 # number of nop insts executed 219system.cpu.iew.EXEC:rate 0.324680 # Inst execution rate 220system.cpu.iew.EXEC:refs 2768 # number of memory reference insts executed 221system.cpu.iew.EXEC:stores 1280 # Number of stores executed 222system.cpu.iew.EXEC:swp 0 # number of swp insts executed 223system.cpu.iew.WB:consumers 5977 # num instructions consuming a value 224system.cpu.iew.WB:count 7563 # cumulative count of insts written-back 225system.cpu.iew.WB:fanout 0.643801 # average fanout of values written-back 226system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ 227system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 228system.cpu.iew.WB:producers 3848 # num instructions producing a value 229system.cpu.iew.WB:rate 0.316152 # insts written-back per cycle 230system.cpu.iew.WB:sent 7622 # cumulative count of insts sent to commit 231system.cpu.iew.branchMispredicts 279 # Number of branch mispredicts detected at execute 232system.cpu.iew.iewBlockCycles 141 # Number of cycles IEW is blocking 233system.cpu.iew.iewDispLoadInsts 1815 # Number of dispatched load instructions 234system.cpu.iew.iewDispNonSpecInsts 14 # Number of dispatched non-speculative instructions 235system.cpu.iew.iewDispSquashedInsts 102 # Number of squashed instructions skipped by dispatch 236system.cpu.iew.iewDispStoreInsts 1394 # Number of dispatched store instructions 237system.cpu.iew.iewDispatchedInsts 9586 # Number of instructions dispatched to IQ 238system.cpu.iew.iewExecLoadInsts 1488 # Number of load instructions executed 239system.cpu.iew.iewExecSquashedInsts 320 # Number of squashed instructions skipped in execute 240system.cpu.iew.iewExecutedInsts 7767 # Number of executed instructions 241system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall 242system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 243system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 244system.cpu.iew.iewSquashCycles 615 # Number of cycles IEW is squashing 245system.cpu.iew.iewUnblockCycles 20 # Number of cycles IEW is unblocking 246system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 247system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 248system.cpu.iew.lsq.thread.0.forwLoads 28 # Number of loads that had data forwarded from stores 249system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 250system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address 251system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 252system.cpu.iew.lsq.thread.0.memOrderViolation 40 # Number of memory ordering violations 253system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled 254system.cpu.iew.lsq.thread.0.squashedLoads 853 # Number of loads squashed 255system.cpu.iew.lsq.thread.0.squashedStores 348 # Number of stores squashed 256system.cpu.iew.memOrderViolationEvents 40 # Number of memory order violations 257system.cpu.iew.predictedNotTakenIncorrect 215 # Number of branches that were predicted not taken incorrectly 258system.cpu.iew.predictedTakenIncorrect 64 # Number of branches that were predicted taken incorrectly 259system.cpu.ipc 0.242455 # IPC: Instructions Per Cycle 260system.cpu.ipc_total 0.242455 # IPC: Total IPC of All Threads 261system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 262system.cpu.iq.ISSUE:FU_type_0::IntAlu 5153 63.72% 63.72% # Type of FU issued 263system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 63.72% # Type of FU issued 264system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 63.72% # Type of FU issued 265system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 63.74% # Type of FU issued 266system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 63.74% # Type of FU issued 267system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 63.74% # Type of FU issued 268system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 63.74% # Type of FU issued 269system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 63.74% # Type of FU issued 270system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 63.74% # Type of FU issued 271system.cpu.iq.ISSUE:FU_type_0::MemRead 1611 19.92% 83.67% # Type of FU issued 272system.cpu.iq.ISSUE:FU_type_0::MemWrite 1321 16.33% 100.00% # Type of FU issued 273system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 274system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 275system.cpu.iq.ISSUE:FU_type_0::total 8087 # Type of FU issued 276system.cpu.iq.ISSUE:fu_busy_cnt 141 # FU busy when requested 277system.cpu.iq.ISSUE:fu_busy_rate 0.017435 # FU busy rate (busy events/executed inst) 278system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 279system.cpu.iq.ISSUE:fu_full::IntAlu 11 7.80% 7.80% # attempts to use FU when none available 280system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 7.80% # attempts to use FU when none available 281system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 7.80% # attempts to use FU when none available 282system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 7.80% # attempts to use FU when none available 283system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 7.80% # attempts to use FU when none available 284system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 7.80% # attempts to use FU when none available 285system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 7.80% # attempts to use FU when none available 286system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 7.80% # attempts to use FU when none available 287system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 7.80% # attempts to use FU when none available 288system.cpu.iq.ISSUE:fu_full::MemRead 67 47.52% 55.32% # attempts to use FU when none available 289system.cpu.iq.ISSUE:fu_full::MemWrite 63 44.68% 100.00% # attempts to use FU when none available 290system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 291system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 292system.cpu.iq.ISSUE:issued_per_cycle::samples 11446 # Number of insts issued each cycle 293system.cpu.iq.ISSUE:issued_per_cycle::mean 0.706535 # Number of insts issued each cycle 294system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.384911 # Number of insts issued each cycle 295system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 296system.cpu.iq.ISSUE:issued_per_cycle::0-1 8157 71.27% 71.27% # Number of insts issued each cycle 297system.cpu.iq.ISSUE:issued_per_cycle::1-2 1172 10.24% 81.50% # Number of insts issued each cycle 298system.cpu.iq.ISSUE:issued_per_cycle::2-3 822 7.18% 88.69% # Number of insts issued each cycle 299system.cpu.iq.ISSUE:issued_per_cycle::3-4 530 4.63% 93.32% # Number of insts issued each cycle 300system.cpu.iq.ISSUE:issued_per_cycle::4-5 377 3.29% 96.61% # Number of insts issued each cycle 301system.cpu.iq.ISSUE:issued_per_cycle::5-6 216 1.89% 98.50% # Number of insts issued each cycle 302system.cpu.iq.ISSUE:issued_per_cycle::6-7 120 1.05% 99.55% # Number of insts issued each cycle 303system.cpu.iq.ISSUE:issued_per_cycle::7-8 43 0.38% 99.92% # Number of insts issued each cycle 304system.cpu.iq.ISSUE:issued_per_cycle::8 9 0.08% 100.00% # Number of insts issued each cycle 305system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 306system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle 307system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle 308system.cpu.iq.ISSUE:issued_per_cycle::total 11446 # Number of insts issued each cycle 309system.cpu.iq.ISSUE:rate 0.338057 # Inst issue rate 310system.cpu.iq.iqInstsAdded 9564 # Number of instructions added to the IQ (excludes non-spec) 311system.cpu.iq.iqInstsIssued 8087 # Number of instructions issued 312system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ 313system.cpu.iq.iqSquashedInstsExamined 3408 # Number of squashed instructions iterated over during squash; mainly for profiling 314system.cpu.iq.iqSquashedInstsIssued 7 # Number of squashed instructions issued 315system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed 316system.cpu.iq.iqSquashedOperandsExamined 3586 # Number of squashed operands that are examined and possibly removed from graph 317system.cpu.itb.accesses 0 # DTB accesses 318system.cpu.itb.hits 0 # DTB hits 319system.cpu.itb.misses 0 # DTB misses 320system.cpu.itb.read_accesses 0 # DTB read accesses 321system.cpu.itb.read_hits 0 # DTB read hits 322system.cpu.itb.read_misses 0 # DTB read misses 323system.cpu.itb.write_accesses 0 # DTB write accesses 324system.cpu.itb.write_hits 0 # DTB write hits 325system.cpu.itb.write_misses 0 # DTB write misses 326system.cpu.l2cache.ReadExReq_accesses 48 # number of ReadExReq accesses(hits+misses) 327system.cpu.l2cache.ReadExReq_avg_miss_latency 34697.916667 # average ReadExReq miss latency 328system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31500 # average ReadExReq mshr miss latency 329system.cpu.l2cache.ReadExReq_miss_latency 1665500 # number of ReadExReq miss cycles 330system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses 331system.cpu.l2cache.ReadExReq_misses 48 # number of ReadExReq misses 332system.cpu.l2cache.ReadExReq_mshr_miss_latency 1512000 # number of ReadExReq MSHR miss cycles 333system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses 334system.cpu.l2cache.ReadExReq_mshr_misses 48 # number of ReadExReq MSHR misses 335system.cpu.l2cache.ReadReq_accesses 386 # number of ReadReq accesses(hits+misses) 336system.cpu.l2cache.ReadReq_avg_miss_latency 34333.333333 # average ReadReq miss latency 337system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31156.084656 # average ReadReq mshr miss latency 338system.cpu.l2cache.ReadReq_hits 8 # number of ReadReq hits 339system.cpu.l2cache.ReadReq_miss_latency 12978000 # number of ReadReq miss cycles 340system.cpu.l2cache.ReadReq_miss_rate 0.979275 # miss rate for ReadReq accesses 341system.cpu.l2cache.ReadReq_misses 378 # number of ReadReq misses 342system.cpu.l2cache.ReadReq_mshr_miss_latency 11777000 # number of ReadReq MSHR miss cycles 343system.cpu.l2cache.ReadReq_mshr_miss_rate 0.979275 # mshr miss rate for ReadReq accesses 344system.cpu.l2cache.ReadReq_mshr_misses 378 # number of ReadReq MSHR misses 345system.cpu.l2cache.UpgradeReq_accesses 17 # number of UpgradeReq accesses(hits+misses) 346system.cpu.l2cache.UpgradeReq_avg_miss_latency 34235.294118 # average UpgradeReq miss latency 347system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31176.470588 # average UpgradeReq mshr miss latency 348system.cpu.l2cache.UpgradeReq_miss_latency 582000 # number of UpgradeReq miss cycles 349system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses 350system.cpu.l2cache.UpgradeReq_misses 17 # number of UpgradeReq misses 351system.cpu.l2cache.UpgradeReq_mshr_miss_latency 530000 # number of UpgradeReq MSHR miss cycles 352system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses 353system.cpu.l2cache.UpgradeReq_mshr_misses 17 # number of UpgradeReq MSHR misses 354system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 355system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 356system.cpu.l2cache.avg_refs 0.022161 # Average number of references to valid blocks. 357system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 358system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 359system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 360system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 361system.cpu.l2cache.cache_copies 0 # number of cache copies performed 362system.cpu.l2cache.demand_accesses 434 # number of demand (read+write) accesses 363system.cpu.l2cache.demand_avg_miss_latency 34374.413146 # average overall miss latency 364system.cpu.l2cache.demand_avg_mshr_miss_latency 31194.835681 # average overall mshr miss latency 365system.cpu.l2cache.demand_hits 8 # number of demand (read+write) hits 366system.cpu.l2cache.demand_miss_latency 14643500 # number of demand (read+write) miss cycles 367system.cpu.l2cache.demand_miss_rate 0.981567 # miss rate for demand accesses 368system.cpu.l2cache.demand_misses 426 # number of demand (read+write) misses 369system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 370system.cpu.l2cache.demand_mshr_miss_latency 13289000 # number of demand (read+write) MSHR miss cycles 371system.cpu.l2cache.demand_mshr_miss_rate 0.981567 # mshr miss rate for demand accesses 372system.cpu.l2cache.demand_mshr_misses 426 # number of demand (read+write) MSHR misses 373system.cpu.l2cache.fast_writes 0 # number of fast writes performed 374system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 375system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 376system.cpu.l2cache.overall_accesses 434 # number of overall (read+write) accesses 377system.cpu.l2cache.overall_avg_miss_latency 34374.413146 # average overall miss latency 378system.cpu.l2cache.overall_avg_mshr_miss_latency 31194.835681 # average overall mshr miss latency 379system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 380system.cpu.l2cache.overall_hits 8 # number of overall hits 381system.cpu.l2cache.overall_miss_latency 14643500 # number of overall miss cycles 382system.cpu.l2cache.overall_miss_rate 0.981567 # miss rate for overall accesses 383system.cpu.l2cache.overall_misses 426 # number of overall misses 384system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits 385system.cpu.l2cache.overall_mshr_miss_latency 13289000 # number of overall MSHR miss cycles 386system.cpu.l2cache.overall_mshr_miss_rate 0.981567 # mshr miss rate for overall accesses 387system.cpu.l2cache.overall_mshr_misses 426 # number of overall MSHR misses 388system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 389system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 390system.cpu.l2cache.replacements 0 # number of replacements 391system.cpu.l2cache.sampled_refs 361 # Sample count of references to valid blocks. 392system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 393system.cpu.l2cache.tagsinuse 180.652204 # Cycle average of tags in use 394system.cpu.l2cache.total_refs 8 # Total number of references to valid blocks. 395system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 396system.cpu.l2cache.writebacks 0 # number of writebacks 397system.cpu.memDep0.conflictingLoads 67 # Number of conflicting loads. 398system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. 399system.cpu.memDep0.insertedLoads 1815 # Number of loads inserted to the mem dependence unit. 400system.cpu.memDep0.insertedStores 1394 # Number of stores inserted to the mem dependence unit. 401system.cpu.numCycles 23922 # number of cpu cycles simulated 402system.cpu.rename.RENAME:BlockCycles 356 # Number of cycles rename is blocking 403system.cpu.rename.RENAME:CommittedMaps 5007 # Number of HB maps that are committed 404system.cpu.rename.RENAME:IQFullEvents 7 # Number of times rename has blocked due to IQ full 405system.cpu.rename.RENAME:IdleCycles 7745 # Number of cycles rename is idle 406system.cpu.rename.RENAME:LSQFullEvents 222 # Number of times rename has blocked due to LSQ full 407system.cpu.rename.RENAME:RenameLookups 17199 # Number of register rename lookups that rename has made 408system.cpu.rename.RENAME:RenamedInsts 10376 # Number of instructions processed by rename 409system.cpu.rename.RENAME:RenamedOperands 9321 # Number of destination operands rename has renamed 410system.cpu.rename.RENAME:RunCycles 1877 # Number of cycles rename is running 411system.cpu.rename.RENAME:SquashCycles 615 # Number of cycles rename is squashing 412system.cpu.rename.RENAME:UnblockCycles 273 # Number of cycles rename is unblocking 413system.cpu.rename.RENAME:UndoneMaps 4314 # Number of HB maps that are undone due to squashing 414system.cpu.rename.RENAME:serializeStallCycles 580 # count of cycles rename stalled for serializing inst 415system.cpu.rename.RENAME:serializingInsts 22 # count of serializing insts renamed 416system.cpu.rename.RENAME:skidInsts 571 # count of insts added to the skid buffer 417system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed 418system.cpu.timesIdled 231 # Number of times that the entire CPU went into an idle state and unscheduled itself 419system.cpu.workload.PROG:num_syscalls 9 # Number of system calls 420 421---------- End Simulation Statistics ---------- 422