config.ini revision 9620:89aa34e10625
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a 13clock=1000 14init_param=0 15kernel= 16load_addr_mask=1099511627775 17mem_mode=timing 18mem_ranges= 19memories=system.physmem 20num_work_ids=16 21readfile= 22symbolfile= 23work_begin_ckpt_count=0 24work_begin_cpu_id_exit=-1 25work_begin_exit_count=0 26work_cpus_ckpt_count=0 27work_end_ckpt_count=0 28work_end_exit_count=0 29work_item_id=-1 30system_port=system.membus.slave[0] 31 32[system.cpu] 33type=DerivO3CPU 34children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 35LFSTSize=1024 36LQEntries=32 37LSQCheckLoads=true 38LSQDepCheckShift=4 39SQEntries=32 40SSITSize=1024 41UnifiedTLB=true 42activity=0 43backComSize=5 44branchPred=system.cpu.branchPred 45cachePorts=200 46checker=Null 47clock=500 48commitToDecodeDelay=1 49commitToFetchDelay=1 50commitToIEWDelay=1 51commitToRenameDelay=1 52commitWidth=8 53cpu_id=0 54decodeToFetchDelay=1 55decodeToRenameDelay=1 56decodeWidth=8 57dispatchWidth=8 58do_checkpoint_insts=true 59do_quiesce=true 60do_statistics_insts=true 61dtb=system.cpu.dtb 62fetchToDecodeDelay=1 63fetchTrapLatency=1 64fetchWidth=8 65forwardComSize=5 66fuPool=system.cpu.fuPool 67function_trace=false 68function_trace_start=0 69iewToCommitDelay=1 70iewToDecodeDelay=1 71iewToFetchDelay=1 72iewToRenameDelay=1 73interrupts=system.cpu.interrupts 74isa=system.cpu.isa 75issueToExecuteDelay=1 76issueWidth=8 77itb=system.cpu.itb 78max_insts_all_threads=0 79max_insts_any_thread=0 80max_loads_all_threads=0 81max_loads_any_thread=0 82needsTSO=false 83numIQEntries=64 84numPhysFloatRegs=256 85numPhysIntRegs=256 86numROBEntries=192 87numRobs=1 88numThreads=1 89profile=0 90progress_interval=0 91renameToDecodeDelay=1 92renameToFetchDelay=1 93renameToIEWDelay=2 94renameToROBDelay=1 95renameWidth=8 96smtCommitPolicy=RoundRobin 97smtFetchPolicy=SingleThread 98smtIQPolicy=Partitioned 99smtIQThreshold=100 100smtLSQPolicy=Partitioned 101smtLSQThreshold=100 102smtNumFetchingThreads=1 103smtROBPolicy=Partitioned 104smtROBThreshold=100 105squashWidth=8 106store_set_clear_period=250000 107switched_out=false 108system=system 109tracer=system.cpu.tracer 110trapLatency=13 111wbDepth=1 112wbWidth=8 113workload=system.cpu.workload 114dcache_port=system.cpu.dcache.cpu_side 115icache_port=system.cpu.icache.cpu_side 116 117[system.cpu.branchPred] 118type=BranchPredictor 119BTBEntries=4096 120BTBTagSize=16 121RASSize=16 122choiceCtrBits=2 123choicePredictorSize=8192 124globalCtrBits=2 125globalHistoryBits=13 126globalPredictorSize=8192 127instShiftAmt=2 128localCtrBits=2 129localHistoryBits=11 130localHistoryTableSize=2048 131localPredictorSize=2048 132numThreads=1 133predType=tournament 134 135[system.cpu.dcache] 136type=BaseCache 137addr_ranges=0:18446744073709551615 138assoc=2 139block_size=64 140clock=500 141forward_snoops=true 142hit_latency=2 143is_top_level=true 144max_miss_count=0 145mshrs=4 146prefetch_on_access=false 147prefetcher=Null 148response_latency=2 149size=262144 150system=system 151tgts_per_mshr=20 152two_queue=false 153write_buffers=8 154cpu_side=system.cpu.dcache_port 155mem_side=system.cpu.toL2Bus.slave[1] 156 157[system.cpu.dtb] 158type=PowerTLB 159size=64 160 161[system.cpu.fuPool] 162type=FUPool 163children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 164FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 165 166[system.cpu.fuPool.FUList0] 167type=FUDesc 168children=opList 169count=6 170opList=system.cpu.fuPool.FUList0.opList 171 172[system.cpu.fuPool.FUList0.opList] 173type=OpDesc 174issueLat=1 175opClass=IntAlu 176opLat=1 177 178[system.cpu.fuPool.FUList1] 179type=FUDesc 180children=opList0 opList1 181count=2 182opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 183 184[system.cpu.fuPool.FUList1.opList0] 185type=OpDesc 186issueLat=1 187opClass=IntMult 188opLat=3 189 190[system.cpu.fuPool.FUList1.opList1] 191type=OpDesc 192issueLat=19 193opClass=IntDiv 194opLat=20 195 196[system.cpu.fuPool.FUList2] 197type=FUDesc 198children=opList0 opList1 opList2 199count=4 200opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 201 202[system.cpu.fuPool.FUList2.opList0] 203type=OpDesc 204issueLat=1 205opClass=FloatAdd 206opLat=2 207 208[system.cpu.fuPool.FUList2.opList1] 209type=OpDesc 210issueLat=1 211opClass=FloatCmp 212opLat=2 213 214[system.cpu.fuPool.FUList2.opList2] 215type=OpDesc 216issueLat=1 217opClass=FloatCvt 218opLat=2 219 220[system.cpu.fuPool.FUList3] 221type=FUDesc 222children=opList0 opList1 opList2 223count=2 224opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 225 226[system.cpu.fuPool.FUList3.opList0] 227type=OpDesc 228issueLat=1 229opClass=FloatMult 230opLat=4 231 232[system.cpu.fuPool.FUList3.opList1] 233type=OpDesc 234issueLat=12 235opClass=FloatDiv 236opLat=12 237 238[system.cpu.fuPool.FUList3.opList2] 239type=OpDesc 240issueLat=24 241opClass=FloatSqrt 242opLat=24 243 244[system.cpu.fuPool.FUList4] 245type=FUDesc 246children=opList 247count=0 248opList=system.cpu.fuPool.FUList4.opList 249 250[system.cpu.fuPool.FUList4.opList] 251type=OpDesc 252issueLat=1 253opClass=MemRead 254opLat=1 255 256[system.cpu.fuPool.FUList5] 257type=FUDesc 258children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 259count=4 260opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 261 262[system.cpu.fuPool.FUList5.opList00] 263type=OpDesc 264issueLat=1 265opClass=SimdAdd 266opLat=1 267 268[system.cpu.fuPool.FUList5.opList01] 269type=OpDesc 270issueLat=1 271opClass=SimdAddAcc 272opLat=1 273 274[system.cpu.fuPool.FUList5.opList02] 275type=OpDesc 276issueLat=1 277opClass=SimdAlu 278opLat=1 279 280[system.cpu.fuPool.FUList5.opList03] 281type=OpDesc 282issueLat=1 283opClass=SimdCmp 284opLat=1 285 286[system.cpu.fuPool.FUList5.opList04] 287type=OpDesc 288issueLat=1 289opClass=SimdCvt 290opLat=1 291 292[system.cpu.fuPool.FUList5.opList05] 293type=OpDesc 294issueLat=1 295opClass=SimdMisc 296opLat=1 297 298[system.cpu.fuPool.FUList5.opList06] 299type=OpDesc 300issueLat=1 301opClass=SimdMult 302opLat=1 303 304[system.cpu.fuPool.FUList5.opList07] 305type=OpDesc 306issueLat=1 307opClass=SimdMultAcc 308opLat=1 309 310[system.cpu.fuPool.FUList5.opList08] 311type=OpDesc 312issueLat=1 313opClass=SimdShift 314opLat=1 315 316[system.cpu.fuPool.FUList5.opList09] 317type=OpDesc 318issueLat=1 319opClass=SimdShiftAcc 320opLat=1 321 322[system.cpu.fuPool.FUList5.opList10] 323type=OpDesc 324issueLat=1 325opClass=SimdSqrt 326opLat=1 327 328[system.cpu.fuPool.FUList5.opList11] 329type=OpDesc 330issueLat=1 331opClass=SimdFloatAdd 332opLat=1 333 334[system.cpu.fuPool.FUList5.opList12] 335type=OpDesc 336issueLat=1 337opClass=SimdFloatAlu 338opLat=1 339 340[system.cpu.fuPool.FUList5.opList13] 341type=OpDesc 342issueLat=1 343opClass=SimdFloatCmp 344opLat=1 345 346[system.cpu.fuPool.FUList5.opList14] 347type=OpDesc 348issueLat=1 349opClass=SimdFloatCvt 350opLat=1 351 352[system.cpu.fuPool.FUList5.opList15] 353type=OpDesc 354issueLat=1 355opClass=SimdFloatDiv 356opLat=1 357 358[system.cpu.fuPool.FUList5.opList16] 359type=OpDesc 360issueLat=1 361opClass=SimdFloatMisc 362opLat=1 363 364[system.cpu.fuPool.FUList5.opList17] 365type=OpDesc 366issueLat=1 367opClass=SimdFloatMult 368opLat=1 369 370[system.cpu.fuPool.FUList5.opList18] 371type=OpDesc 372issueLat=1 373opClass=SimdFloatMultAcc 374opLat=1 375 376[system.cpu.fuPool.FUList5.opList19] 377type=OpDesc 378issueLat=1 379opClass=SimdFloatSqrt 380opLat=1 381 382[system.cpu.fuPool.FUList6] 383type=FUDesc 384children=opList 385count=0 386opList=system.cpu.fuPool.FUList6.opList 387 388[system.cpu.fuPool.FUList6.opList] 389type=OpDesc 390issueLat=1 391opClass=MemWrite 392opLat=1 393 394[system.cpu.fuPool.FUList7] 395type=FUDesc 396children=opList0 opList1 397count=4 398opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 399 400[system.cpu.fuPool.FUList7.opList0] 401type=OpDesc 402issueLat=1 403opClass=MemRead 404opLat=1 405 406[system.cpu.fuPool.FUList7.opList1] 407type=OpDesc 408issueLat=1 409opClass=MemWrite 410opLat=1 411 412[system.cpu.fuPool.FUList8] 413type=FUDesc 414children=opList 415count=1 416opList=system.cpu.fuPool.FUList8.opList 417 418[system.cpu.fuPool.FUList8.opList] 419type=OpDesc 420issueLat=3 421opClass=IprAccess 422opLat=3 423 424[system.cpu.icache] 425type=BaseCache 426addr_ranges=0:18446744073709551615 427assoc=2 428block_size=64 429clock=500 430forward_snoops=true 431hit_latency=2 432is_top_level=true 433max_miss_count=0 434mshrs=4 435prefetch_on_access=false 436prefetcher=Null 437response_latency=2 438size=131072 439system=system 440tgts_per_mshr=20 441two_queue=false 442write_buffers=8 443cpu_side=system.cpu.icache_port 444mem_side=system.cpu.toL2Bus.slave[0] 445 446[system.cpu.interrupts] 447type=PowerInterrupts 448 449[system.cpu.isa] 450type=PowerISA 451 452[system.cpu.itb] 453type=PowerTLB 454size=64 455 456[system.cpu.l2cache] 457type=BaseCache 458addr_ranges=0:18446744073709551615 459assoc=8 460block_size=64 461clock=500 462forward_snoops=true 463hit_latency=20 464is_top_level=false 465max_miss_count=0 466mshrs=20 467prefetch_on_access=false 468prefetcher=Null 469response_latency=20 470size=2097152 471system=system 472tgts_per_mshr=12 473two_queue=false 474write_buffers=8 475cpu_side=system.cpu.toL2Bus.master[0] 476mem_side=system.membus.slave[1] 477 478[system.cpu.toL2Bus] 479type=CoherentBus 480block_size=64 481clock=500 482header_cycles=1 483system=system 484use_default_range=false 485width=32 486master=system.cpu.l2cache.cpu_side 487slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 488 489[system.cpu.tracer] 490type=ExeTracer 491 492[system.cpu.workload] 493type=LiveProcess 494cmd=hello 495cwd= 496egid=100 497env= 498errout=cerr 499euid=100 500executable=tests/test-progs/hello/bin/power/linux/hello 501gid=100 502input=cin 503max_stack_size=67108864 504output=cout 505pid=100 506ppid=99 507simpoint=0 508system=system 509uid=100 510 511[system.membus] 512type=CoherentBus 513block_size=64 514clock=1000 515header_cycles=1 516system=system 517use_default_range=false 518width=8 519master=system.physmem.port 520slave=system.system_port system.cpu.l2cache.mem_side 521 522[system.physmem] 523type=SimpleDRAM 524activation_limit=4 525addr_mapping=openmap 526banks_per_rank=8 527channels=1 528clock=1000 529conf_table_reported=false 530in_addr_map=true 531lines_per_rowbuffer=32 532mem_sched_policy=frfcfs 533null=false 534page_policy=open 535range=0:134217727 536ranks_per_channel=2 537read_buffer_size=32 538tBURST=5000 539tCL=13750 540tRCD=13750 541tREFI=7800000 542tRFC=300000 543tRP=13750 544tWTR=7500 545tXAW=40000 546write_buffer_size=32 547write_thresh_perc=70 548zero=false 549port=system.membus.master[0] 550 551