config.ini revision 10242:cb4e86c17767
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20load_addr_mask=1099511627775 21load_offset=0 22mem_mode=timing 23mem_ranges= 24memories=system.physmem 25num_work_ids=16 26readfile= 27symbolfile= 28work_begin_ckpt_count=0 29work_begin_cpu_id_exit=-1 30work_begin_exit_count=0 31work_cpus_ckpt_count=0 32work_end_ckpt_count=0 33work_end_exit_count=0 34work_item_id=-1 35system_port=system.membus.slave[0] 36 37[system.clk_domain] 38type=SrcClockDomain 39clock=1000 40eventq_index=0 41voltage_domain=system.voltage_domain 42 43[system.cpu] 44type=DerivO3CPU 45children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 46LFSTSize=1024 47LQEntries=32 48LSQCheckLoads=true 49LSQDepCheckShift=4 50SQEntries=32 51SSITSize=1024 52UnifiedTLB=true 53activity=0 54backComSize=5 55branchPred=system.cpu.branchPred 56cachePorts=200 57checker=Null 58clk_domain=system.cpu_clk_domain 59commitToDecodeDelay=1 60commitToFetchDelay=1 61commitToIEWDelay=1 62commitToRenameDelay=1 63commitWidth=8 64cpu_id=0 65decodeToFetchDelay=1 66decodeToRenameDelay=1 67decodeWidth=8 68dispatchWidth=8 69do_checkpoint_insts=true 70do_quiesce=true 71do_statistics_insts=true 72dtb=system.cpu.dtb 73eventq_index=0 74fetchBufferSize=64 75fetchToDecodeDelay=1 76fetchTrapLatency=1 77fetchWidth=8 78forwardComSize=5 79fuPool=system.cpu.fuPool 80function_trace=false 81function_trace_start=0 82iewToCommitDelay=1 83iewToDecodeDelay=1 84iewToFetchDelay=1 85iewToRenameDelay=1 86interrupts=system.cpu.interrupts 87isa=system.cpu.isa 88issueToExecuteDelay=1 89issueWidth=8 90itb=system.cpu.itb 91max_insts_all_threads=0 92max_insts_any_thread=0 93max_loads_all_threads=0 94max_loads_any_thread=0 95needsTSO=false 96numIQEntries=64 97numPhysCCRegs=0 98numPhysFloatRegs=256 99numPhysIntRegs=256 100numROBEntries=192 101numRobs=1 102numThreads=1 103profile=0 104progress_interval=0 105renameToDecodeDelay=1 106renameToFetchDelay=1 107renameToIEWDelay=2 108renameToROBDelay=1 109renameWidth=8 110simpoint_start_insts= 111smtCommitPolicy=RoundRobin 112smtFetchPolicy=SingleThread 113smtIQPolicy=Partitioned 114smtIQThreshold=100 115smtLSQPolicy=Partitioned 116smtLSQThreshold=100 117smtNumFetchingThreads=1 118smtROBPolicy=Partitioned 119smtROBThreshold=100 120socket_id=0 121squashWidth=8 122store_set_clear_period=250000 123switched_out=false 124system=system 125tracer=system.cpu.tracer 126trapLatency=13 127wbDepth=1 128wbWidth=8 129workload=system.cpu.workload 130dcache_port=system.cpu.dcache.cpu_side 131icache_port=system.cpu.icache.cpu_side 132 133[system.cpu.branchPred] 134type=BranchPredictor 135BTBEntries=4096 136BTBTagSize=16 137RASSize=16 138choiceCtrBits=2 139choicePredictorSize=8192 140eventq_index=0 141globalCtrBits=2 142globalPredictorSize=8192 143instShiftAmt=2 144localCtrBits=2 145localHistoryTableSize=2048 146localPredictorSize=2048 147numThreads=1 148predType=tournament 149 150[system.cpu.dcache] 151type=BaseCache 152children=tags 153addr_ranges=0:18446744073709551615 154assoc=2 155clk_domain=system.cpu_clk_domain 156eventq_index=0 157forward_snoops=true 158hit_latency=2 159is_top_level=true 160max_miss_count=0 161mshrs=4 162prefetch_on_access=false 163prefetcher=Null 164response_latency=2 165sequential_access=false 166size=262144 167system=system 168tags=system.cpu.dcache.tags 169tgts_per_mshr=20 170two_queue=false 171write_buffers=8 172cpu_side=system.cpu.dcache_port 173mem_side=system.cpu.toL2Bus.slave[1] 174 175[system.cpu.dcache.tags] 176type=LRU 177assoc=2 178block_size=64 179clk_domain=system.cpu_clk_domain 180eventq_index=0 181hit_latency=2 182sequential_access=false 183size=262144 184 185[system.cpu.dtb] 186type=PowerTLB 187eventq_index=0 188size=64 189 190[system.cpu.fuPool] 191type=FUPool 192children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 193FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 194eventq_index=0 195 196[system.cpu.fuPool.FUList0] 197type=FUDesc 198children=opList 199count=6 200eventq_index=0 201opList=system.cpu.fuPool.FUList0.opList 202 203[system.cpu.fuPool.FUList0.opList] 204type=OpDesc 205eventq_index=0 206issueLat=1 207opClass=IntAlu 208opLat=1 209 210[system.cpu.fuPool.FUList1] 211type=FUDesc 212children=opList0 opList1 213count=2 214eventq_index=0 215opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 216 217[system.cpu.fuPool.FUList1.opList0] 218type=OpDesc 219eventq_index=0 220issueLat=1 221opClass=IntMult 222opLat=3 223 224[system.cpu.fuPool.FUList1.opList1] 225type=OpDesc 226eventq_index=0 227issueLat=19 228opClass=IntDiv 229opLat=20 230 231[system.cpu.fuPool.FUList2] 232type=FUDesc 233children=opList0 opList1 opList2 234count=4 235eventq_index=0 236opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 237 238[system.cpu.fuPool.FUList2.opList0] 239type=OpDesc 240eventq_index=0 241issueLat=1 242opClass=FloatAdd 243opLat=2 244 245[system.cpu.fuPool.FUList2.opList1] 246type=OpDesc 247eventq_index=0 248issueLat=1 249opClass=FloatCmp 250opLat=2 251 252[system.cpu.fuPool.FUList2.opList2] 253type=OpDesc 254eventq_index=0 255issueLat=1 256opClass=FloatCvt 257opLat=2 258 259[system.cpu.fuPool.FUList3] 260type=FUDesc 261children=opList0 opList1 opList2 262count=2 263eventq_index=0 264opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 265 266[system.cpu.fuPool.FUList3.opList0] 267type=OpDesc 268eventq_index=0 269issueLat=1 270opClass=FloatMult 271opLat=4 272 273[system.cpu.fuPool.FUList3.opList1] 274type=OpDesc 275eventq_index=0 276issueLat=12 277opClass=FloatDiv 278opLat=12 279 280[system.cpu.fuPool.FUList3.opList2] 281type=OpDesc 282eventq_index=0 283issueLat=24 284opClass=FloatSqrt 285opLat=24 286 287[system.cpu.fuPool.FUList4] 288type=FUDesc 289children=opList 290count=0 291eventq_index=0 292opList=system.cpu.fuPool.FUList4.opList 293 294[system.cpu.fuPool.FUList4.opList] 295type=OpDesc 296eventq_index=0 297issueLat=1 298opClass=MemRead 299opLat=1 300 301[system.cpu.fuPool.FUList5] 302type=FUDesc 303children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 304count=4 305eventq_index=0 306opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 307 308[system.cpu.fuPool.FUList5.opList00] 309type=OpDesc 310eventq_index=0 311issueLat=1 312opClass=SimdAdd 313opLat=1 314 315[system.cpu.fuPool.FUList5.opList01] 316type=OpDesc 317eventq_index=0 318issueLat=1 319opClass=SimdAddAcc 320opLat=1 321 322[system.cpu.fuPool.FUList5.opList02] 323type=OpDesc 324eventq_index=0 325issueLat=1 326opClass=SimdAlu 327opLat=1 328 329[system.cpu.fuPool.FUList5.opList03] 330type=OpDesc 331eventq_index=0 332issueLat=1 333opClass=SimdCmp 334opLat=1 335 336[system.cpu.fuPool.FUList5.opList04] 337type=OpDesc 338eventq_index=0 339issueLat=1 340opClass=SimdCvt 341opLat=1 342 343[system.cpu.fuPool.FUList5.opList05] 344type=OpDesc 345eventq_index=0 346issueLat=1 347opClass=SimdMisc 348opLat=1 349 350[system.cpu.fuPool.FUList5.opList06] 351type=OpDesc 352eventq_index=0 353issueLat=1 354opClass=SimdMult 355opLat=1 356 357[system.cpu.fuPool.FUList5.opList07] 358type=OpDesc 359eventq_index=0 360issueLat=1 361opClass=SimdMultAcc 362opLat=1 363 364[system.cpu.fuPool.FUList5.opList08] 365type=OpDesc 366eventq_index=0 367issueLat=1 368opClass=SimdShift 369opLat=1 370 371[system.cpu.fuPool.FUList5.opList09] 372type=OpDesc 373eventq_index=0 374issueLat=1 375opClass=SimdShiftAcc 376opLat=1 377 378[system.cpu.fuPool.FUList5.opList10] 379type=OpDesc 380eventq_index=0 381issueLat=1 382opClass=SimdSqrt 383opLat=1 384 385[system.cpu.fuPool.FUList5.opList11] 386type=OpDesc 387eventq_index=0 388issueLat=1 389opClass=SimdFloatAdd 390opLat=1 391 392[system.cpu.fuPool.FUList5.opList12] 393type=OpDesc 394eventq_index=0 395issueLat=1 396opClass=SimdFloatAlu 397opLat=1 398 399[system.cpu.fuPool.FUList5.opList13] 400type=OpDesc 401eventq_index=0 402issueLat=1 403opClass=SimdFloatCmp 404opLat=1 405 406[system.cpu.fuPool.FUList5.opList14] 407type=OpDesc 408eventq_index=0 409issueLat=1 410opClass=SimdFloatCvt 411opLat=1 412 413[system.cpu.fuPool.FUList5.opList15] 414type=OpDesc 415eventq_index=0 416issueLat=1 417opClass=SimdFloatDiv 418opLat=1 419 420[system.cpu.fuPool.FUList5.opList16] 421type=OpDesc 422eventq_index=0 423issueLat=1 424opClass=SimdFloatMisc 425opLat=1 426 427[system.cpu.fuPool.FUList5.opList17] 428type=OpDesc 429eventq_index=0 430issueLat=1 431opClass=SimdFloatMult 432opLat=1 433 434[system.cpu.fuPool.FUList5.opList18] 435type=OpDesc 436eventq_index=0 437issueLat=1 438opClass=SimdFloatMultAcc 439opLat=1 440 441[system.cpu.fuPool.FUList5.opList19] 442type=OpDesc 443eventq_index=0 444issueLat=1 445opClass=SimdFloatSqrt 446opLat=1 447 448[system.cpu.fuPool.FUList6] 449type=FUDesc 450children=opList 451count=0 452eventq_index=0 453opList=system.cpu.fuPool.FUList6.opList 454 455[system.cpu.fuPool.FUList6.opList] 456type=OpDesc 457eventq_index=0 458issueLat=1 459opClass=MemWrite 460opLat=1 461 462[system.cpu.fuPool.FUList7] 463type=FUDesc 464children=opList0 opList1 465count=4 466eventq_index=0 467opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 468 469[system.cpu.fuPool.FUList7.opList0] 470type=OpDesc 471eventq_index=0 472issueLat=1 473opClass=MemRead 474opLat=1 475 476[system.cpu.fuPool.FUList7.opList1] 477type=OpDesc 478eventq_index=0 479issueLat=1 480opClass=MemWrite 481opLat=1 482 483[system.cpu.fuPool.FUList8] 484type=FUDesc 485children=opList 486count=1 487eventq_index=0 488opList=system.cpu.fuPool.FUList8.opList 489 490[system.cpu.fuPool.FUList8.opList] 491type=OpDesc 492eventq_index=0 493issueLat=3 494opClass=IprAccess 495opLat=3 496 497[system.cpu.icache] 498type=BaseCache 499children=tags 500addr_ranges=0:18446744073709551615 501assoc=2 502clk_domain=system.cpu_clk_domain 503eventq_index=0 504forward_snoops=true 505hit_latency=2 506is_top_level=true 507max_miss_count=0 508mshrs=4 509prefetch_on_access=false 510prefetcher=Null 511response_latency=2 512sequential_access=false 513size=131072 514system=system 515tags=system.cpu.icache.tags 516tgts_per_mshr=20 517two_queue=false 518write_buffers=8 519cpu_side=system.cpu.icache_port 520mem_side=system.cpu.toL2Bus.slave[0] 521 522[system.cpu.icache.tags] 523type=LRU 524assoc=2 525block_size=64 526clk_domain=system.cpu_clk_domain 527eventq_index=0 528hit_latency=2 529sequential_access=false 530size=131072 531 532[system.cpu.interrupts] 533type=PowerInterrupts 534eventq_index=0 535 536[system.cpu.isa] 537type=PowerISA 538eventq_index=0 539 540[system.cpu.itb] 541type=PowerTLB 542eventq_index=0 543size=64 544 545[system.cpu.l2cache] 546type=BaseCache 547children=tags 548addr_ranges=0:18446744073709551615 549assoc=8 550clk_domain=system.cpu_clk_domain 551eventq_index=0 552forward_snoops=true 553hit_latency=20 554is_top_level=false 555max_miss_count=0 556mshrs=20 557prefetch_on_access=false 558prefetcher=Null 559response_latency=20 560sequential_access=false 561size=2097152 562system=system 563tags=system.cpu.l2cache.tags 564tgts_per_mshr=12 565two_queue=false 566write_buffers=8 567cpu_side=system.cpu.toL2Bus.master[0] 568mem_side=system.membus.slave[1] 569 570[system.cpu.l2cache.tags] 571type=LRU 572assoc=8 573block_size=64 574clk_domain=system.cpu_clk_domain 575eventq_index=0 576hit_latency=20 577sequential_access=false 578size=2097152 579 580[system.cpu.toL2Bus] 581type=CoherentBus 582clk_domain=system.cpu_clk_domain 583eventq_index=0 584header_cycles=1 585system=system 586use_default_range=false 587width=32 588master=system.cpu.l2cache.cpu_side 589slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 590 591[system.cpu.tracer] 592type=ExeTracer 593eventq_index=0 594 595[system.cpu.workload] 596type=LiveProcess 597cmd=hello 598cwd= 599egid=100 600env= 601errout=cerr 602euid=100 603eventq_index=0 604executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/power/linux/hello 605gid=100 606input=cin 607max_stack_size=67108864 608output=cout 609pid=100 610ppid=99 611simpoint=0 612system=system 613uid=100 614 615[system.cpu_clk_domain] 616type=SrcClockDomain 617clock=500 618eventq_index=0 619voltage_domain=system.voltage_domain 620 621[system.membus] 622type=CoherentBus 623clk_domain=system.clk_domain 624eventq_index=0 625header_cycles=1 626system=system 627use_default_range=false 628width=8 629master=system.physmem.port 630slave=system.system_port system.cpu.l2cache.mem_side 631 632[system.physmem] 633type=DRAMCtrl 634activation_limit=4 635addr_mapping=RoRaBaChCo 636banks_per_rank=8 637burst_length=8 638channels=1 639clk_domain=system.clk_domain 640conf_table_reported=true 641device_bus_width=8 642device_rowbuffer_size=1024 643devices_per_rank=8 644eventq_index=0 645in_addr_map=true 646max_accesses_per_row=16 647mem_sched_policy=frfcfs 648min_writes_per_switch=16 649null=false 650page_policy=open_adaptive 651range=0:134217727 652ranks_per_channel=2 653read_buffer_size=32 654static_backend_latency=10000 655static_frontend_latency=10000 656tBURST=5000 657tCK=1250 658tCL=13750 659tRAS=35000 660tRCD=13750 661tREFI=7800000 662tRFC=260000 663tRP=13750 664tRRD=6000 665tRTP=7500 666tRTW=2500 667tWR=15000 668tWTR=7500 669tXAW=30000 670write_buffer_size=64 671write_high_thresh_perc=85 672write_low_thresh_perc=50 673port=system.membus.master[0] 674 675[system.voltage_domain] 676type=VoltageDomain 677eventq_index=0 678voltage=1.000000 679 680