stats.txt revision 3041
12141SN/A 21376SN/A---------- Begin Simulation Statistics ---------- 31376SN/Ahost_inst_rate 67697 # Simulator instruction rate (inst/s) 41376SN/Ahost_mem_usage 158936 # Number of bytes of host memory used 51376SN/Ahost_seconds 0.08 # Real time elapsed on the host 61376SN/Ahost_tick_rate 102046 # Simulator tick rate (ticks/s) 71376SN/Asim_freq 1000000000000 # Frequency of simulated ticks 81376SN/Asim_insts 5657 # Number of instructions simulated 91376SN/Asim_seconds 0.000000 # Number of seconds simulated 101376SN/Asim_ticks 8573 # Number of ticks simulated 111376SN/Asystem.cpu.dcache.ReadReq_accesses 1131 # number of ReadReq accesses(hits+misses) 121376SN/Asystem.cpu.dcache.ReadReq_avg_miss_latency 1791574296802328064 # average ReadReq miss latency 131376SN/Asystem.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency 141376SN/Asystem.cpu.dcache.ReadReq_hits 1052 # number of ReadReq hits 151376SN/Asystem.cpu.dcache.ReadReq_miss_latency 141534369447383908352 # number of ReadReq miss cycles 161376SN/Asystem.cpu.dcache.ReadReq_miss_rate 0.069850 # miss rate for ReadReq accesses 171376SN/Asystem.cpu.dcache.ReadReq_misses 79 # number of ReadReq misses 181376SN/Asystem.cpu.dcache.ReadReq_mshr_miss_latency 158 # number of ReadReq MSHR miss cycles 191376SN/Asystem.cpu.dcache.ReadReq_mshr_miss_rate 0.069850 # mshr miss rate for ReadReq accesses 201376SN/Asystem.cpu.dcache.ReadReq_mshr_misses 79 # number of ReadReq MSHR misses 211376SN/Asystem.cpu.dcache.WriteReq_accesses 933 # number of WriteReq accesses(hits+misses) 221376SN/Asystem.cpu.dcache.WriteReq_avg_miss_latency 2766176443076198912 # average WriteReq miss latency 231376SN/Asystem.cpu.dcache.WriteReq_avg_mshr_miss_latency 2 # average WriteReq mshr miss latency 241376SN/Asystem.cpu.dcache.WriteReq_hits 875 # number of WriteReq hits 251376SN/Asystem.cpu.dcache.WriteReq_miss_latency 160438233698419539968 # number of WriteReq miss cycles 261376SN/Asystem.cpu.dcache.WriteReq_miss_rate 0.062165 # miss rate for WriteReq accesses 271376SN/Asystem.cpu.dcache.WriteReq_misses 58 # number of WriteReq misses 281376SN/Asystem.cpu.dcache.WriteReq_mshr_miss_latency 100 # number of WriteReq MSHR miss cycles 2912563Sgabeblack@google.comsystem.cpu.dcache.WriteReq_mshr_miss_rate 0.053591 # mshr miss rate for WriteReq accesses 3012563Sgabeblack@google.comsystem.cpu.dcache.WriteReq_mshr_misses 50 # number of WriteReq MSHR misses 311428SN/Asystem.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 321428SN/Asystem.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 331881SN/Asystem.cpu.dcache.avg_refs 14.065693 # Average number of references to valid blocks. 341881SN/Asystem.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked 351881SN/Asystem.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked 361881SN/Asystem.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 375467Snate@binkert.orgsystem.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked 381881SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 391881SN/Asystem.cpu.dcache.demand_accesses 2064 # number of demand (read+write) accesses 401881SN/Asystem.cpu.dcache.demand_avg_miss_latency 2204179585005864704 # average overall miss latency 4113663Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency 421881SN/Asystem.cpu.dcache.demand_hits 1927 # number of demand (read+write) hits 435618Snate@binkert.orgsystem.cpu.dcache.demand_miss_latency 301972603145803464704 # number of demand (read+write) miss cycles 445618Snate@binkert.orgsystem.cpu.dcache.demand_miss_rate 0.066376 # miss rate for demand accesses 455618Snate@binkert.orgsystem.cpu.dcache.demand_misses 137 # number of demand (read+write) misses 465618Snate@binkert.orgsystem.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 475618Snate@binkert.orgsystem.cpu.dcache.demand_mshr_miss_latency 258 # number of demand (read+write) MSHR miss cycles 485618Snate@binkert.orgsystem.cpu.dcache.demand_mshr_miss_rate 0.062500 # mshr miss rate for demand accesses 495618Snate@binkert.orgsystem.cpu.dcache.demand_mshr_misses 129 # number of demand (read+write) MSHR misses 505618Snate@binkert.orgsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 515618Snate@binkert.orgsystem.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 525618Snate@binkert.orgsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 535618Snate@binkert.orgsystem.cpu.dcache.overall_accesses 2064 # number of overall (read+write) accesses 545618Snate@binkert.orgsystem.cpu.dcache.overall_avg_miss_latency 2204179585005864704 # average overall miss latency 5513663Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency 5613663Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 5713663Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_hits 1927 # number of overall hits 585618Snate@binkert.orgsystem.cpu.dcache.overall_miss_latency 301972603145803464704 # number of overall miss cycles 595618Snate@binkert.orgsystem.cpu.dcache.overall_miss_rate 0.066376 # miss rate for overall accesses 605618Snate@binkert.orgsystem.cpu.dcache.overall_misses 137 # number of overall misses 615618Snate@binkert.orgsystem.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits 6213663Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_miss_latency 258 # number of overall MSHR miss cycles 6313663Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_miss_rate 0.062500 # mshr miss rate for overall accesses 645618Snate@binkert.orgsystem.cpu.dcache.overall_mshr_misses 129 # number of overall MSHR misses 655618Snate@binkert.orgsystem.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 665467Snate@binkert.orgsystem.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 675467Snate@binkert.orgsystem.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 6813663Sandreas.sandberg@arm.comsystem.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 6913663Sandreas.sandberg@arm.comsystem.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 7013663Sandreas.sandberg@arm.comsystem.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 711881SN/Asystem.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 721881SN/Asystem.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 731881SN/Asystem.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 7412563Sgabeblack@google.comsystem.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 751881SN/Asystem.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 7612563Sgabeblack@google.comsystem.cpu.dcache.replacements 0 # number of replacements 775467Snate@binkert.orgsystem.cpu.dcache.sampled_refs 137 # Sample count of references to valid blocks. 785467Snate@binkert.orgsystem.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 7912563Sgabeblack@google.comsystem.cpu.dcache.tagsinuse 91.822487 # Cycle average of tags in use 805467Snate@binkert.orgsystem.cpu.dcache.total_refs 1927 # Total number of references to valid blocks. 815467Snate@binkert.orgsystem.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 821881SN/Asystem.cpu.dcache.writebacks 0 # number of writebacks 831881SN/Asystem.cpu.icache.ReadReq_accesses 5658 # number of ReadReq accesses(hits+misses) 845467Snate@binkert.orgsystem.cpu.icache.ReadReq_avg_miss_latency 1549898021785231104 # average ReadReq miss latency 855467Snate@binkert.orgsystem.cpu.icache.ReadReq_avg_mshr_miss_latency 1.993399 # average ReadReq mshr miss latency 865467Snate@binkert.orgsystem.cpu.icache.ReadReq_hits 5355 # number of ReadReq hits 875467Snate@binkert.orgsystem.cpu.icache.ReadReq_miss_latency 469619100600925028352 # number of ReadReq miss cycles 885467Snate@binkert.orgsystem.cpu.icache.ReadReq_miss_rate 0.053552 # miss rate for ReadReq accesses 8912563Sgabeblack@google.comsystem.cpu.icache.ReadReq_misses 303 # number of ReadReq misses 9012563Sgabeblack@google.comsystem.cpu.icache.ReadReq_mshr_miss_latency 604 # number of ReadReq MSHR miss cycles 915467Snate@binkert.orgsystem.cpu.icache.ReadReq_mshr_miss_rate 0.053552 # mshr miss rate for ReadReq accesses 925467Snate@binkert.orgsystem.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses 935467Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 945467Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 955467Snate@binkert.orgsystem.cpu.icache.avg_refs 17.673267 # Average number of references to valid blocks. 965467Snate@binkert.orgsystem.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked 975467Snate@binkert.orgsystem.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked 985467Snate@binkert.orgsystem.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 9913663Sandreas.sandberg@arm.comsystem.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked 1005467Snate@binkert.orgsystem.cpu.icache.cache_copies 0 # number of cache copies performed 1015467Snate@binkert.orgsystem.cpu.icache.demand_accesses 5658 # number of demand (read+write) accesses 1025467Snate@binkert.orgsystem.cpu.icache.demand_avg_miss_latency 1549898021785231104 # average overall miss latency 1035467Snate@binkert.orgsystem.cpu.icache.demand_avg_mshr_miss_latency 1.993399 # average overall mshr miss latency 1041881SN/Asystem.cpu.icache.demand_hits 5355 # number of demand (read+write) hits 1051881SN/Asystem.cpu.icache.demand_miss_latency 469619100600925028352 # number of demand (read+write) miss cycles 1065467Snate@binkert.orgsystem.cpu.icache.demand_miss_rate 0.053552 # miss rate for demand accesses 1075467Snate@binkert.orgsystem.cpu.icache.demand_misses 303 # number of demand (read+write) misses 1085467Snate@binkert.orgsystem.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 1095467Snate@binkert.orgsystem.cpu.icache.demand_mshr_miss_latency 604 # number of demand (read+write) MSHR miss cycles 1106654Snate@binkert.orgsystem.cpu.icache.demand_mshr_miss_rate 0.053552 # mshr miss rate for demand accesses 1116654Snate@binkert.orgsystem.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses 1125467Snate@binkert.orgsystem.cpu.icache.fast_writes 0 # number of fast writes performed 1135467Snate@binkert.orgsystem.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 1145467Snate@binkert.orgsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1151881SN/Asystem.cpu.icache.overall_accesses 5658 # number of overall (read+write) accesses 1165618Snate@binkert.orgsystem.cpu.icache.overall_avg_miss_latency 1549898021785231104 # average overall miss latency 1175618Snate@binkert.orgsystem.cpu.icache.overall_avg_mshr_miss_latency 1.993399 # average overall mshr miss latency 1185618Snate@binkert.orgsystem.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 1195618Snate@binkert.orgsystem.cpu.icache.overall_hits 5355 # number of overall hits 1205618Snate@binkert.orgsystem.cpu.icache.overall_miss_latency 469619100600925028352 # number of overall miss cycles 1215618Snate@binkert.orgsystem.cpu.icache.overall_miss_rate 0.053552 # miss rate for overall accesses 1225618Snate@binkert.orgsystem.cpu.icache.overall_misses 303 # number of overall misses 1235618Snate@binkert.orgsystem.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits 1241881SN/Asystem.cpu.icache.overall_mshr_miss_latency 604 # number of overall MSHR miss cycles 1251881SN/Asystem.cpu.icache.overall_mshr_miss_rate 0.053552 # mshr miss rate for overall accesses 1261881SN/Asystem.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses 1271881SN/Asystem.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 1281881SN/Asystem.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 1291881SN/Asystem.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 1301881SN/Asystem.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 1315467Snate@binkert.orgsystem.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 1321881SN/Asystem.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 1335467Snate@binkert.orgsystem.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 13413663Sandreas.sandberg@arm.comsystem.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 13513663Sandreas.sandberg@arm.comsystem.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 1361881SN/Asystem.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 1375467Snate@binkert.orgsystem.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 1385467Snate@binkert.orgsystem.cpu.icache.replacements 13 # number of replacements 1395467Snate@binkert.orgsystem.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. 1401881SN/Asystem.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 1415467Snate@binkert.orgsystem.cpu.icache.tagsinuse 138.188010 # Cycle average of tags in use 1425467Snate@binkert.orgsystem.cpu.icache.total_refs 5355 # Total number of references to valid blocks. 1431881SN/Asystem.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1441881SN/Asystem.cpu.icache.writebacks 0 # number of writebacks 1455467Snate@binkert.orgsystem.cpu.idle_fraction 0 # Percentage of idle cycles 1465467Snate@binkert.orgsystem.cpu.l2cache.ReadReq_accesses 440 # number of ReadReq accesses(hits+misses) 1475467Snate@binkert.orgsystem.cpu.l2cache.ReadReq_avg_miss_latency 1.963470 # average ReadReq miss latency 1481881SN/Asystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency 1495467Snate@binkert.orgsystem.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits 1505467Snate@binkert.orgsystem.cpu.l2cache.ReadReq_miss_latency 860 # number of ReadReq miss cycles 1515467Snate@binkert.orgsystem.cpu.l2cache.ReadReq_miss_rate 0.995455 # miss rate for ReadReq accesses 1521881SN/Asystem.cpu.l2cache.ReadReq_misses 438 # number of ReadReq misses 1531881SN/Asystem.cpu.l2cache.ReadReq_mshr_miss_latency 430 # number of ReadReq MSHR miss cycles 1545467Snate@binkert.orgsystem.cpu.l2cache.ReadReq_mshr_miss_rate 0.977273 # mshr miss rate for ReadReq accesses 1555467Snate@binkert.orgsystem.cpu.l2cache.ReadReq_mshr_misses 430 # number of ReadReq MSHR misses 1565467Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 1575467Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 1585467Snate@binkert.orgsystem.cpu.l2cache.avg_refs 0.004566 # Average number of references to valid blocks. 1595467Snate@binkert.orgsystem.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked 1605467Snate@binkert.orgsystem.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked 1615467Snate@binkert.orgsystem.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 1625467Snate@binkert.orgsystem.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked 1635467Snate@binkert.orgsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 1645467Snate@binkert.orgsystem.cpu.l2cache.demand_accesses 440 # number of demand (read+write) accesses 1655467Snate@binkert.orgsystem.cpu.l2cache.demand_avg_miss_latency 1.963470 # average overall miss latency 1665467Snate@binkert.orgsystem.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency 1675467Snate@binkert.orgsystem.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits 1685467Snate@binkert.orgsystem.cpu.l2cache.demand_miss_latency 860 # number of demand (read+write) miss cycles 1695467Snate@binkert.orgsystem.cpu.l2cache.demand_miss_rate 0.995455 # miss rate for demand accesses 1705467Snate@binkert.orgsystem.cpu.l2cache.demand_misses 438 # number of demand (read+write) misses 1715467Snate@binkert.orgsystem.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 1725467Snate@binkert.orgsystem.cpu.l2cache.demand_mshr_miss_latency 430 # number of demand (read+write) MSHR miss cycles 1735467Snate@binkert.orgsystem.cpu.l2cache.demand_mshr_miss_rate 0.977273 # mshr miss rate for demand accesses 1745467Snate@binkert.orgsystem.cpu.l2cache.demand_mshr_misses 430 # number of demand (read+write) MSHR misses 1755467Snate@binkert.orgsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 1765467Snate@binkert.orgsystem.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 1775467Snate@binkert.orgsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1785467Snate@binkert.orgsystem.cpu.l2cache.overall_accesses 440 # number of overall (read+write) accesses 1795467Snate@binkert.orgsystem.cpu.l2cache.overall_avg_miss_latency 1.963470 # average overall miss latency 1805467Snate@binkert.orgsystem.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency 1815467Snate@binkert.orgsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 1825467Snate@binkert.orgsystem.cpu.l2cache.overall_hits 2 # number of overall hits 1835467Snate@binkert.orgsystem.cpu.l2cache.overall_miss_latency 860 # number of overall miss cycles 1845467Snate@binkert.orgsystem.cpu.l2cache.overall_miss_rate 0.995455 # miss rate for overall accesses 1855467Snate@binkert.orgsystem.cpu.l2cache.overall_misses 438 # number of overall misses 1865467Snate@binkert.orgsystem.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits 1871881SN/Asystem.cpu.l2cache.overall_mshr_miss_latency 430 # number of overall MSHR miss cycles 1881881SN/Asystem.cpu.l2cache.overall_mshr_miss_rate 0.977273 # mshr miss rate for overall accesses 1891881SN/Asystem.cpu.l2cache.overall_mshr_misses 430 # number of overall MSHR misses 1905467Snate@binkert.orgsystem.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 19112563Sgabeblack@google.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 19212563Sgabeblack@google.comsystem.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 19312563Sgabeblack@google.comsystem.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 19412563Sgabeblack@google.comsystem.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 1951881SN/Asystem.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 1961881SN/Asystem.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 1971881SN/Asystem.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 1981881SN/Asystem.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 1991881SN/Asystem.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 2005467Snate@binkert.orgsystem.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 2011881SN/Asystem.cpu.l2cache.replacements 0 # number of replacements 2021881SN/Asystem.cpu.l2cache.sampled_refs 438 # Sample count of references to valid blocks. 2031881SN/Asystem.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 2041881SN/Asystem.cpu.l2cache.tagsinuse 231.300093 # Cycle average of tags in use 2051881SN/Asystem.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. 2061881SN/Asystem.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2075467Snate@binkert.orgsystem.cpu.l2cache.writebacks 0 # number of writebacks 2081881SN/Asystem.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 2091881SN/Asystem.cpu.numCycles 0 # number of cpu cycles simulated 2101881SN/Asystem.cpu.num_insts 5657 # Number of instructions executed 2111881SN/Asystem.cpu.num_refs 2055 # Number of memory references 2121881SN/Asystem.cpu.workload.PROG:num_syscalls 13 # Number of system calls 2131881SN/A 2141881SN/A---------- End Simulation Statistics ---------- 2151881SN/A