stats.txt revision 10892:bd37e25fb3b7
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000031 # Number of seconds simulated 4sim_ticks 30902500 # Number of ticks simulated 5final_tick 30902500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 339265 # Simulator instruction rate (inst/s) 8host_op_rate 338999 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1861147916 # Simulator tick rate (ticks/s) 10host_mem_usage 289452 # Number of bytes of host memory used 11host_seconds 0.02 # Real time elapsed on the host 12sim_insts 5624 # Number of instructions simulated 13sim_ops 5624 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 18752 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8768 # Number of bytes read from this memory 18system.physmem.bytes_read::total 27520 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 18752 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 18752 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 293 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 137 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 430 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 606811747 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 283731090 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 890542836 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 606811747 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 606811747 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 606811747 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 283731090 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 890542836 # Total bandwidth to/from this memory (bytes/s) 32system.cpu_clk_domain.clock 500 # Clock period in ticks 33system.cpu.dtb.read_hits 0 # DTB read hits 34system.cpu.dtb.read_misses 0 # DTB read misses 35system.cpu.dtb.read_accesses 0 # DTB read accesses 36system.cpu.dtb.write_hits 0 # DTB write hits 37system.cpu.dtb.write_misses 0 # DTB write misses 38system.cpu.dtb.write_accesses 0 # DTB write accesses 39system.cpu.dtb.hits 0 # DTB hits 40system.cpu.dtb.misses 0 # DTB misses 41system.cpu.dtb.accesses 0 # DTB accesses 42system.cpu.itb.read_hits 0 # DTB read hits 43system.cpu.itb.read_misses 0 # DTB read misses 44system.cpu.itb.read_accesses 0 # DTB read accesses 45system.cpu.itb.write_hits 0 # DTB write hits 46system.cpu.itb.write_misses 0 # DTB write misses 47system.cpu.itb.write_accesses 0 # DTB write accesses 48system.cpu.itb.hits 0 # DTB hits 49system.cpu.itb.misses 0 # DTB misses 50system.cpu.itb.accesses 0 # DTB accesses 51system.cpu.workload.num_syscalls 7 # Number of system calls 52system.cpu.numCycles 61805 # number of cpu cycles simulated 53system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 54system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 55system.cpu.committedInsts 5624 # Number of instructions committed 56system.cpu.committedOps 5624 # Number of ops (including micro ops) committed 57system.cpu.num_int_alu_accesses 4944 # Number of integer alu accesses 58system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses 59system.cpu.num_func_calls 190 # number of times a function call or return occured 60system.cpu.num_conditional_control_insts 649 # number of instructions that are conditional controls 61system.cpu.num_int_insts 4944 # number of integer instructions 62system.cpu.num_fp_insts 2 # number of float instructions 63system.cpu.num_int_register_reads 7054 # number of times the integer registers were read 64system.cpu.num_int_register_writes 3281 # number of times the integer registers were written 65system.cpu.num_fp_register_reads 3 # number of times the floating registers were read 66system.cpu.num_fp_register_writes 1 # number of times the floating registers were written 67system.cpu.num_mem_refs 2034 # number of memory refs 68system.cpu.num_load_insts 1132 # Number of load instructions 69system.cpu.num_store_insts 902 # Number of store instructions 70system.cpu.num_idle_cycles 0 # Number of idle cycles 71system.cpu.num_busy_cycles 61805 # Number of busy cycles 72system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 73system.cpu.idle_fraction 0 # Percentage of idle cycles 74system.cpu.Branches 883 # Number of branches fetched 75system.cpu.op_class::No_OpClass 637 11.32% 11.32% # Class of executed instruction 76system.cpu.op_class::IntAlu 2950 52.44% 63.77% # Class of executed instruction 77system.cpu.op_class::IntMult 2 0.04% 63.80% # Class of executed instruction 78system.cpu.op_class::IntDiv 0 0.00% 63.80% # Class of executed instruction 79system.cpu.op_class::FloatAdd 2 0.04% 63.84% # Class of executed instruction 80system.cpu.op_class::FloatCmp 0 0.00% 63.84% # Class of executed instruction 81system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction 82system.cpu.op_class::FloatMult 0 0.00% 63.84% # Class of executed instruction 83system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction 84system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction 85system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction 86system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction 87system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction 88system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction 89system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction 90system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction 91system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction 92system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction 93system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction 94system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction 95system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction 96system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction 97system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction 98system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction 99system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction 100system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction 101system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction 102system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction 103system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction 104system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction 105system.cpu.op_class::MemRead 1132 20.12% 83.96% # Class of executed instruction 106system.cpu.op_class::MemWrite 902 16.04% 100.00% # Class of executed instruction 107system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 108system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 109system.cpu.op_class::total 5625 # Class of executed instruction 110system.cpu.dcache.tags.replacements 0 # number of replacements 111system.cpu.dcache.tags.tagsinuse 86.152837 # Cycle average of tags in use 112system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks. 113system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. 114system.cpu.dcache.tags.avg_refs 13.839416 # Average number of references to valid blocks. 115system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 116system.cpu.dcache.tags.occ_blocks::cpu.data 86.152837 # Average occupied blocks per requestor 117system.cpu.dcache.tags.occ_percent::cpu.data 0.021033 # Average percentage of cache occupancy 118system.cpu.dcache.tags.occ_percent::total 0.021033 # Average percentage of cache occupancy 119system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id 120system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id 121system.cpu.dcache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id 122system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id 123system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses 124system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses 125system.cpu.dcache.ReadReq_hits::cpu.data 1045 # number of ReadReq hits 126system.cpu.dcache.ReadReq_hits::total 1045 # number of ReadReq hits 127system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits 128system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits 129system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits 130system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits 131system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits 132system.cpu.dcache.overall_hits::total 1896 # number of overall hits 133system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses 134system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses 135system.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses 136system.cpu.dcache.WriteReq_misses::total 50 # number of WriteReq misses 137system.cpu.dcache.demand_misses::cpu.data 137 # number of demand (read+write) misses 138system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses 139system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses 140system.cpu.dcache.overall_misses::total 137 # number of overall misses 141system.cpu.dcache.ReadReq_miss_latency::cpu.data 4785000 # number of ReadReq miss cycles 142system.cpu.dcache.ReadReq_miss_latency::total 4785000 # number of ReadReq miss cycles 143system.cpu.dcache.WriteReq_miss_latency::cpu.data 2750000 # number of WriteReq miss cycles 144system.cpu.dcache.WriteReq_miss_latency::total 2750000 # number of WriteReq miss cycles 145system.cpu.dcache.demand_miss_latency::cpu.data 7535000 # number of demand (read+write) miss cycles 146system.cpu.dcache.demand_miss_latency::total 7535000 # number of demand (read+write) miss cycles 147system.cpu.dcache.overall_miss_latency::cpu.data 7535000 # number of overall miss cycles 148system.cpu.dcache.overall_miss_latency::total 7535000 # number of overall miss cycles 149system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses) 150system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses) 151system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) 152system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) 153system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses 154system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses 155system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses 156system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses 157system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076855 # miss rate for ReadReq accesses 158system.cpu.dcache.ReadReq_miss_rate::total 0.076855 # miss rate for ReadReq accesses 159system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses 160system.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses 161system.cpu.dcache.demand_miss_rate::cpu.data 0.067388 # miss rate for demand accesses 162system.cpu.dcache.demand_miss_rate::total 0.067388 # miss rate for demand accesses 163system.cpu.dcache.overall_miss_rate::cpu.data 0.067388 # miss rate for overall accesses 164system.cpu.dcache.overall_miss_rate::total 0.067388 # miss rate for overall accesses 165system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency 166system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency 167system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency 168system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency 169system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency 170system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency 171system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency 172system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency 173system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 174system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 175system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 176system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 177system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 178system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 179system.cpu.dcache.fast_writes 0 # number of fast writes performed 180system.cpu.dcache.cache_copies 0 # number of cache copies performed 181system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses 182system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses 183system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses 184system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses 185system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses 186system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses 187system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses 188system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses 189system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4698000 # number of ReadReq MSHR miss cycles 190system.cpu.dcache.ReadReq_mshr_miss_latency::total 4698000 # number of ReadReq MSHR miss cycles 191system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2700000 # number of WriteReq MSHR miss cycles 192system.cpu.dcache.WriteReq_mshr_miss_latency::total 2700000 # number of WriteReq MSHR miss cycles 193system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7398000 # number of demand (read+write) MSHR miss cycles 194system.cpu.dcache.demand_mshr_miss_latency::total 7398000 # number of demand (read+write) MSHR miss cycles 195system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7398000 # number of overall MSHR miss cycles 196system.cpu.dcache.overall_mshr_miss_latency::total 7398000 # number of overall MSHR miss cycles 197system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses 198system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses 199system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses 200system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses 201system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses 202system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses 203system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses 204system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses 205system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency 206system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency 207system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency 208system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency 209system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency 210system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency 211system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency 212system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency 213system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 214system.cpu.icache.tags.replacements 13 # number of replacements 215system.cpu.icache.tags.tagsinuse 129.096971 # Cycle average of tags in use 216system.cpu.icache.tags.total_refs 5331 # Total number of references to valid blocks. 217system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. 218system.cpu.icache.tags.avg_refs 18.071186 # Average number of references to valid blocks. 219system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 220system.cpu.icache.tags.occ_blocks::cpu.inst 129.096971 # Average occupied blocks per requestor 221system.cpu.icache.tags.occ_percent::cpu.inst 0.063036 # Average percentage of cache occupancy 222system.cpu.icache.tags.occ_percent::total 0.063036 # Average percentage of cache occupancy 223system.cpu.icache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id 224system.cpu.icache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id 225system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id 226system.cpu.icache.tags.occ_task_id_percent::1024 0.137695 # Percentage of cache occupancy per task id 227system.cpu.icache.tags.tag_accesses 11547 # Number of tag accesses 228system.cpu.icache.tags.data_accesses 11547 # Number of data accesses 229system.cpu.icache.ReadReq_hits::cpu.inst 5331 # number of ReadReq hits 230system.cpu.icache.ReadReq_hits::total 5331 # number of ReadReq hits 231system.cpu.icache.demand_hits::cpu.inst 5331 # number of demand (read+write) hits 232system.cpu.icache.demand_hits::total 5331 # number of demand (read+write) hits 233system.cpu.icache.overall_hits::cpu.inst 5331 # number of overall hits 234system.cpu.icache.overall_hits::total 5331 # number of overall hits 235system.cpu.icache.ReadReq_misses::cpu.inst 295 # number of ReadReq misses 236system.cpu.icache.ReadReq_misses::total 295 # number of ReadReq misses 237system.cpu.icache.demand_misses::cpu.inst 295 # number of demand (read+write) misses 238system.cpu.icache.demand_misses::total 295 # number of demand (read+write) misses 239system.cpu.icache.overall_misses::cpu.inst 295 # number of overall misses 240system.cpu.icache.overall_misses::total 295 # number of overall misses 241system.cpu.icache.ReadReq_miss_latency::cpu.inst 16141500 # number of ReadReq miss cycles 242system.cpu.icache.ReadReq_miss_latency::total 16141500 # number of ReadReq miss cycles 243system.cpu.icache.demand_miss_latency::cpu.inst 16141500 # number of demand (read+write) miss cycles 244system.cpu.icache.demand_miss_latency::total 16141500 # number of demand (read+write) miss cycles 245system.cpu.icache.overall_miss_latency::cpu.inst 16141500 # number of overall miss cycles 246system.cpu.icache.overall_miss_latency::total 16141500 # number of overall miss cycles 247system.cpu.icache.ReadReq_accesses::cpu.inst 5626 # number of ReadReq accesses(hits+misses) 248system.cpu.icache.ReadReq_accesses::total 5626 # number of ReadReq accesses(hits+misses) 249system.cpu.icache.demand_accesses::cpu.inst 5626 # number of demand (read+write) accesses 250system.cpu.icache.demand_accesses::total 5626 # number of demand (read+write) accesses 251system.cpu.icache.overall_accesses::cpu.inst 5626 # number of overall (read+write) accesses 252system.cpu.icache.overall_accesses::total 5626 # number of overall (read+write) accesses 253system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052435 # miss rate for ReadReq accesses 254system.cpu.icache.ReadReq_miss_rate::total 0.052435 # miss rate for ReadReq accesses 255system.cpu.icache.demand_miss_rate::cpu.inst 0.052435 # miss rate for demand accesses 256system.cpu.icache.demand_miss_rate::total 0.052435 # miss rate for demand accesses 257system.cpu.icache.overall_miss_rate::cpu.inst 0.052435 # miss rate for overall accesses 258system.cpu.icache.overall_miss_rate::total 0.052435 # miss rate for overall accesses 259system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54716.949153 # average ReadReq miss latency 260system.cpu.icache.ReadReq_avg_miss_latency::total 54716.949153 # average ReadReq miss latency 261system.cpu.icache.demand_avg_miss_latency::cpu.inst 54716.949153 # average overall miss latency 262system.cpu.icache.demand_avg_miss_latency::total 54716.949153 # average overall miss latency 263system.cpu.icache.overall_avg_miss_latency::cpu.inst 54716.949153 # average overall miss latency 264system.cpu.icache.overall_avg_miss_latency::total 54716.949153 # average overall miss latency 265system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 266system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 267system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 268system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 269system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 270system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 271system.cpu.icache.fast_writes 0 # number of fast writes performed 272system.cpu.icache.cache_copies 0 # number of cache copies performed 273system.cpu.icache.ReadReq_mshr_misses::cpu.inst 295 # number of ReadReq MSHR misses 274system.cpu.icache.ReadReq_mshr_misses::total 295 # number of ReadReq MSHR misses 275system.cpu.icache.demand_mshr_misses::cpu.inst 295 # number of demand (read+write) MSHR misses 276system.cpu.icache.demand_mshr_misses::total 295 # number of demand (read+write) MSHR misses 277system.cpu.icache.overall_mshr_misses::cpu.inst 295 # number of overall MSHR misses 278system.cpu.icache.overall_mshr_misses::total 295 # number of overall MSHR misses 279system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15846500 # number of ReadReq MSHR miss cycles 280system.cpu.icache.ReadReq_mshr_miss_latency::total 15846500 # number of ReadReq MSHR miss cycles 281system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15846500 # number of demand (read+write) MSHR miss cycles 282system.cpu.icache.demand_mshr_miss_latency::total 15846500 # number of demand (read+write) MSHR miss cycles 283system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15846500 # number of overall MSHR miss cycles 284system.cpu.icache.overall_mshr_miss_latency::total 15846500 # number of overall MSHR miss cycles 285system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for ReadReq accesses 286system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052435 # mshr miss rate for ReadReq accesses 287system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for demand accesses 288system.cpu.icache.demand_mshr_miss_rate::total 0.052435 # mshr miss rate for demand accesses 289system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for overall accesses 290system.cpu.icache.overall_mshr_miss_rate::total 0.052435 # mshr miss rate for overall accesses 291system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53716.949153 # average ReadReq mshr miss latency 292system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53716.949153 # average ReadReq mshr miss latency 293system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53716.949153 # average overall mshr miss latency 294system.cpu.icache.demand_avg_mshr_miss_latency::total 53716.949153 # average overall mshr miss latency 295system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53716.949153 # average overall mshr miss latency 296system.cpu.icache.overall_avg_mshr_miss_latency::total 53716.949153 # average overall mshr miss latency 297system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 298system.cpu.l2cache.tags.replacements 0 # number of replacements 299system.cpu.l2cache.tags.tagsinuse 183.690355 # Cycle average of tags in use 300system.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks. 301system.cpu.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks. 302system.cpu.l2cache.tags.avg_refs 0.039474 # Average number of references to valid blocks. 303system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 304system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.238740 # Average occupied blocks per requestor 305system.cpu.l2cache.tags.occ_blocks::cpu.data 53.451615 # Average occupied blocks per requestor 306system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003975 # Average percentage of cache occupancy 307system.cpu.l2cache.tags.occ_percent::cpu.data 0.001631 # Average percentage of cache occupancy 308system.cpu.l2cache.tags.occ_percent::total 0.005606 # Average percentage of cache occupancy 309system.cpu.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id 310system.cpu.l2cache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id 311system.cpu.l2cache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id 312system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011597 # Percentage of cache occupancy per task id 313system.cpu.l2cache.tags.tag_accesses 3990 # Number of tag accesses 314system.cpu.l2cache.tags.data_accesses 3990 # Number of data accesses 315system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits 316system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits 317system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 318system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 319system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 320system.cpu.l2cache.overall_hits::total 2 # number of overall hits 321system.cpu.l2cache.ReadExReq_misses::cpu.data 50 # number of ReadExReq misses 322system.cpu.l2cache.ReadExReq_misses::total 50 # number of ReadExReq misses 323system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 293 # number of ReadCleanReq misses 324system.cpu.l2cache.ReadCleanReq_misses::total 293 # number of ReadCleanReq misses 325system.cpu.l2cache.ReadSharedReq_misses::cpu.data 87 # number of ReadSharedReq misses 326system.cpu.l2cache.ReadSharedReq_misses::total 87 # number of ReadSharedReq misses 327system.cpu.l2cache.demand_misses::cpu.inst 293 # number of demand (read+write) misses 328system.cpu.l2cache.demand_misses::cpu.data 137 # number of demand (read+write) misses 329system.cpu.l2cache.demand_misses::total 430 # number of demand (read+write) misses 330system.cpu.l2cache.overall_misses::cpu.inst 293 # number of overall misses 331system.cpu.l2cache.overall_misses::cpu.data 137 # number of overall misses 332system.cpu.l2cache.overall_misses::total 430 # number of overall misses 333system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2625000 # number of ReadExReq miss cycles 334system.cpu.l2cache.ReadExReq_miss_latency::total 2625000 # number of ReadExReq miss cycles 335system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 15383000 # number of ReadCleanReq miss cycles 336system.cpu.l2cache.ReadCleanReq_miss_latency::total 15383000 # number of ReadCleanReq miss cycles 337system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4567500 # number of ReadSharedReq miss cycles 338system.cpu.l2cache.ReadSharedReq_miss_latency::total 4567500 # number of ReadSharedReq miss cycles 339system.cpu.l2cache.demand_miss_latency::cpu.inst 15383000 # number of demand (read+write) miss cycles 340system.cpu.l2cache.demand_miss_latency::cpu.data 7192500 # number of demand (read+write) miss cycles 341system.cpu.l2cache.demand_miss_latency::total 22575500 # number of demand (read+write) miss cycles 342system.cpu.l2cache.overall_miss_latency::cpu.inst 15383000 # number of overall miss cycles 343system.cpu.l2cache.overall_miss_latency::cpu.data 7192500 # number of overall miss cycles 344system.cpu.l2cache.overall_miss_latency::total 22575500 # number of overall miss cycles 345system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) 346system.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) 347system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 295 # number of ReadCleanReq accesses(hits+misses) 348system.cpu.l2cache.ReadCleanReq_accesses::total 295 # number of ReadCleanReq accesses(hits+misses) 349system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 87 # number of ReadSharedReq accesses(hits+misses) 350system.cpu.l2cache.ReadSharedReq_accesses::total 87 # number of ReadSharedReq accesses(hits+misses) 351system.cpu.l2cache.demand_accesses::cpu.inst 295 # number of demand (read+write) accesses 352system.cpu.l2cache.demand_accesses::cpu.data 137 # number of demand (read+write) accesses 353system.cpu.l2cache.demand_accesses::total 432 # number of demand (read+write) accesses 354system.cpu.l2cache.overall_accesses::cpu.inst 295 # number of overall (read+write) accesses 355system.cpu.l2cache.overall_accesses::cpu.data 137 # number of overall (read+write) accesses 356system.cpu.l2cache.overall_accesses::total 432 # number of overall (read+write) accesses 357system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 358system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 359system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.993220 # miss rate for ReadCleanReq accesses 360system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993220 # miss rate for ReadCleanReq accesses 361system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 362system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 363system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993220 # miss rate for demand accesses 364system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 365system.cpu.l2cache.demand_miss_rate::total 0.995370 # miss rate for demand accesses 366system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993220 # miss rate for overall accesses 367system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 368system.cpu.l2cache.overall_miss_rate::total 0.995370 # miss rate for overall accesses 369system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency 370system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency 371system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52501.706485 # average ReadCleanReq miss latency 372system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52501.706485 # average ReadCleanReq miss latency 373system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency 374system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency 375system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.706485 # average overall miss latency 376system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency 377system.cpu.l2cache.demand_avg_miss_latency::total 52501.162791 # average overall miss latency 378system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.706485 # average overall miss latency 379system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency 380system.cpu.l2cache.overall_avg_miss_latency::total 52501.162791 # average overall miss latency 381system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 382system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 383system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 384system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 385system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 386system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 387system.cpu.l2cache.fast_writes 0 # number of fast writes performed 388system.cpu.l2cache.cache_copies 0 # number of cache copies performed 389system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses 390system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses 391system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 293 # number of ReadCleanReq MSHR misses 392system.cpu.l2cache.ReadCleanReq_mshr_misses::total 293 # number of ReadCleanReq MSHR misses 393system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 87 # number of ReadSharedReq MSHR misses 394system.cpu.l2cache.ReadSharedReq_mshr_misses::total 87 # number of ReadSharedReq MSHR misses 395system.cpu.l2cache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses 396system.cpu.l2cache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses 397system.cpu.l2cache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses 398system.cpu.l2cache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses 399system.cpu.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses 400system.cpu.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses 401system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2125000 # number of ReadExReq MSHR miss cycles 402system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2125000 # number of ReadExReq MSHR miss cycles 403system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12453000 # number of ReadCleanReq MSHR miss cycles 404system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12453000 # number of ReadCleanReq MSHR miss cycles 405system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3697500 # number of ReadSharedReq MSHR miss cycles 406system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3697500 # number of ReadSharedReq MSHR miss cycles 407system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12453000 # number of demand (read+write) MSHR miss cycles 408system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5822500 # number of demand (read+write) MSHR miss cycles 409system.cpu.l2cache.demand_mshr_miss_latency::total 18275500 # number of demand (read+write) MSHR miss cycles 410system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12453000 # number of overall MSHR miss cycles 411system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5822500 # number of overall MSHR miss cycles 412system.cpu.l2cache.overall_mshr_miss_latency::total 18275500 # number of overall MSHR miss cycles 413system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 414system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 415system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for ReadCleanReq accesses 416system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993220 # mshr miss rate for ReadCleanReq accesses 417system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 418system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 419system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for demand accesses 420system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 421system.cpu.l2cache.demand_mshr_miss_rate::total 0.995370 # mshr miss rate for demand accesses 422system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for overall accesses 423system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 424system.cpu.l2cache.overall_mshr_miss_rate::total 0.995370 # mshr miss rate for overall accesses 425system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency 426system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency 427system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42501.706485 # average ReadCleanReq mshr miss latency 428system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42501.706485 # average ReadCleanReq mshr miss latency 429system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency 430system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency 431system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.706485 # average overall mshr miss latency 432system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency 433system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.162791 # average overall mshr miss latency 434system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.706485 # average overall mshr miss latency 435system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency 436system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.162791 # average overall mshr miss latency 437system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 438system.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution 439system.cpu.toL2Bus.trans_dist::CleanEvict 13 # Transaction distribution 440system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution 441system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution 442system.cpu.toL2Bus.trans_dist::ReadCleanReq 295 # Transaction distribution 443system.cpu.toL2Bus.trans_dist::ReadSharedReq 87 # Transaction distribution 444system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 603 # Packet count per connected master and slave (bytes) 445system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes) 446system.cpu.toL2Bus.pkt_count::total 877 # Packet count per connected master and slave (bytes) 447system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18880 # Cumulative packet size per connected master and slave (bytes) 448system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8768 # Cumulative packet size per connected master and slave (bytes) 449system.cpu.toL2Bus.pkt_size::total 27648 # Cumulative packet size per connected master and slave (bytes) 450system.cpu.toL2Bus.snoops 0 # Total snoops (count) 451system.cpu.toL2Bus.snoop_fanout::samples 445 # Request fanout histogram 452system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 453system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 454system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 455system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 456system.cpu.toL2Bus.snoop_fanout::1 445 100.00% 100.00% # Request fanout histogram 457system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 458system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 459system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 460system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 461system.cpu.toL2Bus.snoop_fanout::total 445 # Request fanout histogram 462system.cpu.toL2Bus.reqLayer0.occupancy 222500 # Layer occupancy (ticks) 463system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 464system.cpu.toL2Bus.respLayer0.occupancy 442500 # Layer occupancy (ticks) 465system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) 466system.cpu.toL2Bus.respLayer1.occupancy 205500 # Layer occupancy (ticks) 467system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) 468system.membus.trans_dist::ReadResp 380 # Transaction distribution 469system.membus.trans_dist::ReadExReq 50 # Transaction distribution 470system.membus.trans_dist::ReadExResp 50 # Transaction distribution 471system.membus.trans_dist::ReadSharedReq 380 # Transaction distribution 472system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 860 # Packet count per connected master and slave (bytes) 473system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes) 474system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27520 # Cumulative packet size per connected master and slave (bytes) 475system.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes) 476system.membus.snoops 0 # Total snoops (count) 477system.membus.snoop_fanout::samples 430 # Request fanout histogram 478system.membus.snoop_fanout::mean 0 # Request fanout histogram 479system.membus.snoop_fanout::stdev 0 # Request fanout histogram 480system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 481system.membus.snoop_fanout::0 430 100.00% 100.00% # Request fanout histogram 482system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 483system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 484system.membus.snoop_fanout::min_value 0 # Request fanout histogram 485system.membus.snoop_fanout::max_value 0 # Request fanout histogram 486system.membus.snoop_fanout::total 430 # Request fanout histogram 487system.membus.reqLayer0.occupancy 430500 # Layer occupancy (ticks) 488system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) 489system.membus.respLayer1.occupancy 2150500 # Layer occupancy (ticks) 490system.membus.respLayer1.utilization 7.0 # Layer utilization (%) 491 492---------- End Simulation Statistics ---------- 493