stats.txt revision 9962
13021SN/A 23021SN/A---------- Begin Simulation Statistics ---------- 39285Sandreas.hansson@arm.comsim_seconds 0.000032 # Number of seconds simulated 49285Sandreas.hansson@arm.comsim_ticks 31633000 # Number of ticks simulated 59285Sandreas.hansson@arm.comfinal_tick 31633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68540SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79838Sandreas.hansson@arm.comhost_inst_rate 304637 # Simulator instruction rate (inst/s) 89838Sandreas.hansson@arm.comhost_op_rate 304230 # Simulator op (including micro ops) rate (op/s) 99838Sandreas.hansson@arm.comhost_tick_rate 1653175117 # Simulator tick rate (ticks/s) 109838Sandreas.hansson@arm.comhost_mem_usage 224940 # Number of bytes of host memory used 119838Sandreas.hansson@arm.comhost_seconds 0.02 # Real time elapsed on the host 129150SAli.Saidi@ARM.comsim_insts 5814 # Number of instructions simulated 139150SAli.Saidi@ARM.comsim_ops 5814 # Number of ops (including micro ops) simulated 149055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory 159055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory 169055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::total 28096 # Number of bytes read from this memory 179055Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::cpu.inst 19264 # Number of instructions bytes read from this memory 189055Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::total 19264 # Number of instructions bytes read from this memory 199055Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory 209055Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory 219055Ssaidi@eecs.umich.edusystem.physmem.num_reads::total 439 # Number of read requests responded to by this memory 229285Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 608984289 # Total read bandwidth from this memory (bytes/s) 239285Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 279202099 # Total read bandwidth from this memory (bytes/s) 249285Sandreas.hansson@arm.comsystem.physmem.bw_read::total 888186388 # Total read bandwidth from this memory (bytes/s) 259285Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 608984289 # Instruction read bandwidth from this memory (bytes/s) 269285Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 608984289 # Instruction read bandwidth from this memory (bytes/s) 279285Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 608984289 # Total bandwidth to/from this memory (bytes/s) 289285Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 279202099 # Total bandwidth to/from this memory (bytes/s) 299285Sandreas.hansson@arm.comsystem.physmem.bw_total::total 888186388 # Total bandwidth to/from this memory (bytes/s) 309729Sandreas.hansson@arm.comsystem.membus.throughput 888186388 # Throughput (bytes/s) 319729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 388 # Transaction distribution 329729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 388 # Transaction distribution 339729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 51 # Transaction distribution 349729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 51 # Transaction distribution 359838Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878 # Packet count per connected master and slave (bytes) 369838Sandreas.hansson@arm.comsystem.membus.pkt_count::total 878 # Packet count per connected master and slave (bytes) 379838Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28096 # Cumulative packet size per connected master and slave (bytes) 389838Sandreas.hansson@arm.comsystem.membus.tot_pkt_size::total 28096 # Cumulative packet size per connected master and slave (bytes) 399729Sandreas.hansson@arm.comsystem.membus.data_through_bus 28096 # Total data (bytes) 409729Sandreas.hansson@arm.comsystem.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 419729Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 439000 # Layer occupancy (ticks) 429729Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 1.4 # Layer utilization (%) 439729Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 3951000 # Layer occupancy (ticks) 449729Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 12.5 # Layer utilization (%) 458540SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 468540SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 478540SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 488540SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 498540SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 508540SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 518540SN/Asystem.cpu.dtb.hits 0 # DTB hits 528540SN/Asystem.cpu.dtb.misses 0 # DTB misses 538540SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 548540SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 558540SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 568540SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 578540SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 588540SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 598540SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 608540SN/Asystem.cpu.itb.hits 0 # DTB hits 618540SN/Asystem.cpu.itb.misses 0 # DTB misses 628540SN/Asystem.cpu.itb.accesses 0 # DTB accesses 638540SN/Asystem.cpu.workload.num_syscalls 8 # Number of system calls 649285Sandreas.hansson@arm.comsystem.cpu.numCycles 63266 # number of cpu cycles simulated 658540SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 668540SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 679150SAli.Saidi@ARM.comsystem.cpu.committedInsts 5814 # Number of instructions committed 689150SAli.Saidi@ARM.comsystem.cpu.committedOps 5814 # Number of ops (including micro ops) committed 699150SAli.Saidi@ARM.comsystem.cpu.num_int_alu_accesses 5113 # Number of integer alu accesses 708540SN/Asystem.cpu.num_fp_alu_accesses 2 # Number of float alu accesses 718540SN/Asystem.cpu.num_func_calls 194 # number of times a function call or return occured 729150SAli.Saidi@ARM.comsystem.cpu.num_conditional_control_insts 676 # number of instructions that are conditional controls 739150SAli.Saidi@ARM.comsystem.cpu.num_int_insts 5113 # number of integer instructions 748540SN/Asystem.cpu.num_fp_insts 2 # number of float instructions 759150SAli.Saidi@ARM.comsystem.cpu.num_int_register_reads 7284 # number of times the integer registers were read 769150SAli.Saidi@ARM.comsystem.cpu.num_int_register_writes 3397 # number of times the integer registers were written 778540SN/Asystem.cpu.num_fp_register_reads 3 # number of times the floating registers were read 788540SN/Asystem.cpu.num_fp_register_writes 1 # number of times the floating registers were written 799150SAli.Saidi@ARM.comsystem.cpu.num_mem_refs 2089 # number of memory refs 809150SAli.Saidi@ARM.comsystem.cpu.num_load_insts 1163 # Number of load instructions 818540SN/Asystem.cpu.num_store_insts 926 # Number of store instructions 828540SN/Asystem.cpu.num_idle_cycles 0 # Number of idle cycles 839285Sandreas.hansson@arm.comsystem.cpu.num_busy_cycles 63266 # Number of busy cycles 848540SN/Asystem.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 858540SN/Asystem.cpu.idle_fraction 0 # Percentage of idle cycles 869838Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 13 # number of replacements 879838Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 132.545353 # Cycle average of tags in use 889838Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 5513 # Total number of references to valid blocks. 899838Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 303 # Sample count of references to valid blocks. 909838Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 18.194719 # Average number of references to valid blocks. 919838Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 929838Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 132.545353 # Average occupied blocks per requestor 939838Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.064719 # Average percentage of cache occupancy 949838Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.064719 # Average percentage of cache occupancy 959150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::cpu.inst 5513 # number of ReadReq hits 969150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::total 5513 # number of ReadReq hits 979150SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::cpu.inst 5513 # number of demand (read+write) hits 989150SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::total 5513 # number of demand (read+write) hits 999150SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::cpu.inst 5513 # number of overall hits 1009150SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::total 5513 # number of overall hits 1018835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::cpu.inst 303 # number of ReadReq misses 1028835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::total 303 # number of ReadReq misses 1038835SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::cpu.inst 303 # number of demand (read+write) misses 1048835SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::total 303 # number of demand (read+write) misses 1058835SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::cpu.inst 303 # number of overall misses 1068835SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::total 303 # number of overall misses 1079285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 16581000 # number of ReadReq miss cycles 1089285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 16581000 # number of ReadReq miss cycles 1099285Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 16581000 # number of demand (read+write) miss cycles 1109285Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 16581000 # number of demand (read+write) miss cycles 1119285Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 16581000 # number of overall miss cycles 1129285Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 16581000 # number of overall miss cycles 1139150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 5816 # number of ReadReq accesses(hits+misses) 1149150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::total 5816 # number of ReadReq accesses(hits+misses) 1159150SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::cpu.inst 5816 # number of demand (read+write) accesses 1169150SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::total 5816 # number of demand (read+write) accesses 1179150SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::cpu.inst 5816 # number of overall (read+write) accesses 1189150SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::total 5816 # number of overall (read+write) accesses 1199150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052098 # miss rate for ReadReq accesses 1209150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::total 0.052098 # miss rate for ReadReq accesses 1219150SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.052098 # miss rate for demand accesses 1229150SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::total 0.052098 # miss rate for demand accesses 1239150SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.052098 # miss rate for overall accesses 1249150SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::total 0.052098 # miss rate for overall accesses 1259285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54722.772277 # average ReadReq miss latency 1269285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 54722.772277 # average ReadReq miss latency 1279285Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 54722.772277 # average overall miss latency 1289285Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 54722.772277 # average overall miss latency 1299285Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 54722.772277 # average overall miss latency 1309285Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 54722.772277 # average overall miss latency 1318540SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1328540SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1338540SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1348540SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 1358983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1368983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1378540SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 1388540SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 1398835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 303 # number of ReadReq MSHR misses 1408835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::total 303 # number of ReadReq MSHR misses 1418835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 303 # number of demand (read+write) MSHR misses 1428835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::total 303 # number of demand (read+write) MSHR misses 1438835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 303 # number of overall MSHR misses 1448835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::total 303 # number of overall MSHR misses 1458835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15975000 # number of ReadReq MSHR miss cycles 1468835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 15975000 # number of ReadReq MSHR miss cycles 1478835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 15975000 # number of demand (read+write) MSHR miss cycles 1488835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::total 15975000 # number of demand (read+write) MSHR miss cycles 1498835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 15975000 # number of overall MSHR miss cycles 1508835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::total 15975000 # number of overall MSHR miss cycles 1519150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052098 # mshr miss rate for ReadReq accesses 1529150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.052098 # mshr miss rate for ReadReq accesses 1539150SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052098 # mshr miss rate for demand accesses 1549150SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.052098 # mshr miss rate for demand accesses 1559150SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052098 # mshr miss rate for overall accesses 1569150SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.052098 # mshr miss rate for overall accesses 1578835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52722.772277 # average ReadReq mshr miss latency 1589055Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52722.772277 # average ReadReq mshr miss latency 1598835SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency 1609055Ssaidi@eecs.umich.edusystem.cpu.icache.demand_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency 1618835SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency 1629055Ssaidi@eecs.umich.edusystem.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency 1638540SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1649838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 1659838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 188.114191 # Cycle average of tags in use 1669838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 1679838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 388 # Sample count of references to valid blocks. 1689838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 0.005155 # Average number of references to valid blocks. 1699838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1709838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 133.890657 # Average occupied blocks per requestor 1719838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 54.223533 # Average occupied blocks per requestor 1729797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.004086 # Average percentage of cache occupancy 1739797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.001655 # Average percentage of cache occupancy 1749838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.005741 # Average percentage of cache occupancy 1758835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits 1768835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits 1778835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 1788835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 1798835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 1808835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 2 # number of overall hits 1818835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 301 # number of ReadReq misses 1828835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses 1838835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::total 388 # number of ReadReq misses 1848835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses 1858835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses 1868835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.inst 301 # number of demand (read+write) misses 1878835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses 1888835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::total 439 # number of demand (read+write) misses 1898835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses 1908835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses 1918835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::total 439 # number of overall misses 1928835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15652000 # number of ReadReq miss cycles 1938835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 4524000 # number of ReadReq miss cycles 1948835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::total 20176000 # number of ReadReq miss cycles 1958835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2652000 # number of ReadExReq miss cycles 1968835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 2652000 # number of ReadExReq miss cycles 1978835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 15652000 # number of demand (read+write) miss cycles 1988835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 7176000 # number of demand (read+write) miss cycles 1998835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::total 22828000 # number of demand (read+write) miss cycles 2008835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 15652000 # number of overall miss cycles 2018835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 7176000 # number of overall miss cycles 2028835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::total 22828000 # number of overall miss cycles 2038835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 303 # number of ReadReq accesses(hits+misses) 2048835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) 2058835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::total 390 # number of ReadReq accesses(hits+misses) 2068835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) 2078835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) 2088835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.inst 303 # number of demand (read+write) accesses 2098835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses 2108835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses 2118835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.inst 303 # number of overall (read+write) accesses 2128835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses 2138835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses 2148835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993399 # miss rate for ReadReq accesses 2158835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 2169055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_miss_rate::total 0.994872 # miss rate for ReadReq accesses 2178835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 2189055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 2198835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.993399 # miss rate for demand accesses 2208835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 2219055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_miss_rate::total 0.995465 # miss rate for demand accesses 2228835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.993399 # miss rate for overall accesses 2238835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 2249055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_miss_rate::total 0.995465 # miss rate for overall accesses 2258835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 2268835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 2279055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 2288835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 2299055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 2308835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 2318835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 2329055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 2338835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 2348835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 2359055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency 2368540SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2378540SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2388540SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2398540SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2408983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2418983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2428540SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 2433041SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 2448835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses 2458835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses 2468835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 388 # number of ReadReq MSHR misses 2478835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses 2488835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses 2498835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses 2508835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses 2518835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::total 439 # number of demand (read+write) MSHR misses 2528835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses 2538835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses 2548835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::total 439 # number of overall MSHR misses 2558835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12040000 # number of ReadReq MSHR miss cycles 2568835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3480000 # number of ReadReq MSHR miss cycles 2578835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 15520000 # number of ReadReq MSHR miss cycles 2588835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2040000 # number of ReadExReq MSHR miss cycles 2598835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2040000 # number of ReadExReq MSHR miss cycles 2608835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12040000 # number of demand (read+write) MSHR miss cycles 2618835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5520000 # number of demand (read+write) MSHR miss cycles 2628835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 17560000 # number of demand (read+write) MSHR miss cycles 2638835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12040000 # number of overall MSHR miss cycles 2648835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 # number of overall MSHR miss cycles 2658835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 17560000 # number of overall MSHR miss cycles 2668835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for ReadReq accesses 2678835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 2689055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994872 # mshr miss rate for ReadReq accesses 2698835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 2709055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 2718835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for demand accesses 2728835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 2739055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_mshr_miss_rate::total 0.995465 # mshr miss rate for demand accesses 2748835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for overall accesses 2758835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 2769055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_mshr_miss_rate::total 0.995465 # mshr miss rate for overall accesses 2778835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 2788835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 2799055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 2808835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 2819055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 2828835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 2838835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 2849055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 2858835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 2868835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 2879055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 2888540SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2899838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 2909838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 87.492114 # Cycle average of tags in use 2919838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 1950 # Total number of references to valid blocks. 2929838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. 2939838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 14.130435 # Average number of references to valid blocks. 2949838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2959838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 87.492114 # Average occupied blocks per requestor 2969838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.021360 # Average percentage of cache occupancy 2979838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.021360 # Average percentage of cache occupancy 2989481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_hits::cpu.data 1076 # number of ReadReq hits 2999481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_hits::total 1076 # number of ReadReq hits 3009481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::cpu.data 874 # number of WriteReq hits 3019481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::total 874 # number of WriteReq hits 3029481Snilay@cs.wisc.edusystem.cpu.dcache.demand_hits::cpu.data 1950 # number of demand (read+write) hits 3039481Snilay@cs.wisc.edusystem.cpu.dcache.demand_hits::total 1950 # number of demand (read+write) hits 3049481Snilay@cs.wisc.edusystem.cpu.dcache.overall_hits::cpu.data 1950 # number of overall hits 3059481Snilay@cs.wisc.edusystem.cpu.dcache.overall_hits::total 1950 # number of overall hits 3069481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses 3079481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses 3089481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::cpu.data 51 # number of WriteReq misses 3099481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::total 51 # number of WriteReq misses 3109481Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses 3119481Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses 3129481Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses 3139481Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::total 138 # number of overall misses 3149481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_latency::cpu.data 4785000 # number of ReadReq miss cycles 3159481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_latency::total 4785000 # number of ReadReq miss cycles 3169481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_latency::cpu.data 2805000 # number of WriteReq miss cycles 3179481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_latency::total 2805000 # number of WriteReq miss cycles 3189481Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles 3199481Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles 3209481Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles 3219481Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles 3229481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) 3239481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) 3249481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 3259481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 3269481Snilay@cs.wisc.edusystem.cpu.dcache.demand_accesses::cpu.data 2088 # number of demand (read+write) accesses 3279481Snilay@cs.wisc.edusystem.cpu.dcache.demand_accesses::total 2088 # number of demand (read+write) accesses 3289481Snilay@cs.wisc.edusystem.cpu.dcache.overall_accesses::cpu.data 2088 # number of overall (read+write) accesses 3299481Snilay@cs.wisc.edusystem.cpu.dcache.overall_accesses::total 2088 # number of overall (read+write) accesses 3309481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074807 # miss rate for ReadReq accesses 3319481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_rate::total 0.074807 # miss rate for ReadReq accesses 3329481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055135 # miss rate for WriteReq accesses 3339481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::total 0.055135 # miss rate for WriteReq accesses 3349481Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_rate::cpu.data 0.066092 # miss rate for demand accesses 3359481Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_rate::total 0.066092 # miss rate for demand accesses 3369481Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_rate::cpu.data 0.066092 # miss rate for overall accesses 3379481Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_rate::total 0.066092 # miss rate for overall accesses 3389481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency 3399481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency 3409481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency 3419481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency 3429481Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency 3439481Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency 3449481Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency 3459481Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency 3469481Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3479481Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3489481Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 3499481Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 3509481Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3519481Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3529481Snilay@cs.wisc.edusystem.cpu.dcache.fast_writes 0 # number of fast writes performed 3539481Snilay@cs.wisc.edusystem.cpu.dcache.cache_copies 0 # number of cache copies performed 3549481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses 3559481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses 3569481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses 3579481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses 3589481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses 3599481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses 3609481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses 3619481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses 3629481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4611000 # number of ReadReq MSHR miss cycles 3639481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_latency::total 4611000 # number of ReadReq MSHR miss cycles 3649481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2703000 # number of WriteReq MSHR miss cycles 3659481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_latency::total 2703000 # number of WriteReq MSHR miss cycles 3669481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles 3679481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles 3689481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles 3699481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles 3709481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses 3719481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses 3729481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses 3739481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses 3749481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for demand accesses 3759481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses 3769481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses 3779481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses 3789481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency 3799481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency 3809481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 3819481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 3829481Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 3839481Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 3849481Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 3859481Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 3869481Snilay@cs.wisc.edusystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 3879729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.throughput 892232795 # Throughput (bytes/s) 3889729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 390 # Transaction distribution 3899729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 390 # Transaction distribution 3909729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution 3919729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution 3929838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 606 # Packet count per connected master and slave (bytes) 3939838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) 3949838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 882 # Packet count per connected master and slave (bytes) 3959838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19392 # Cumulative packet size per connected master and slave (bytes) 3969838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) 3979838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size::total 28224 # Cumulative packet size per connected master and slave (bytes) 3989729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.data_through_bus 28224 # Total data (bytes) 3999729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 4009729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) 4019729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 4029729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 454500 # Layer occupancy (ticks) 4039729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) 4049729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) 4059729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) 4063021SN/A 4073021SN/A---------- End Simulation Statistics ---------- 408