stats.txt revision 9150
13021SN/A 23021SN/A---------- Begin Simulation Statistics ---------- 39096Sandreas.hansson@arm.comsim_seconds 0.000033 # Number of seconds simulated 49150SAli.Saidi@ARM.comsim_ticks 33399000 # Number of ticks simulated 59150SAli.Saidi@ARM.comfinal_tick 33399000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68540SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79150SAli.Saidi@ARM.comhost_inst_rate 212162 # Simulator instruction rate (inst/s) 89150SAli.Saidi@ARM.comhost_op_rate 212025 # Simulator op (including micro ops) rate (op/s) 99150SAli.Saidi@ARM.comhost_tick_rate 1217250605 # Simulator tick rate (ticks/s) 109150SAli.Saidi@ARM.comhost_mem_usage 223376 # Number of bytes of host memory used 119096Sandreas.hansson@arm.comhost_seconds 0.03 # Real time elapsed on the host 129150SAli.Saidi@ARM.comsim_insts 5814 # Number of instructions simulated 139150SAli.Saidi@ARM.comsim_ops 5814 # Number of ops (including micro ops) simulated 149055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory 159055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory 169055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::total 28096 # Number of bytes read from this memory 179055Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::cpu.inst 19264 # Number of instructions bytes read from this memory 189055Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::total 19264 # Number of instructions bytes read from this memory 199055Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory 209055Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory 219055Ssaidi@eecs.umich.edusystem.physmem.num_reads::total 439 # Number of read requests responded to by this memory 229150SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.inst 576783736 # Total read bandwidth from this memory (bytes/s) 239150SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.data 264439055 # Total read bandwidth from this memory (bytes/s) 249150SAli.Saidi@ARM.comsystem.physmem.bw_read::total 841222791 # Total read bandwidth from this memory (bytes/s) 259150SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::cpu.inst 576783736 # Instruction read bandwidth from this memory (bytes/s) 269150SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::total 576783736 # Instruction read bandwidth from this memory (bytes/s) 279150SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.inst 576783736 # Total bandwidth to/from this memory (bytes/s) 289150SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.data 264439055 # Total bandwidth to/from this memory (bytes/s) 299150SAli.Saidi@ARM.comsystem.physmem.bw_total::total 841222791 # Total bandwidth to/from this memory (bytes/s) 308540SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 318540SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 328540SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 338540SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 348540SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 358540SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 368540SN/Asystem.cpu.dtb.hits 0 # DTB hits 378540SN/Asystem.cpu.dtb.misses 0 # DTB misses 388540SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 398540SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 408540SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 418540SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 428540SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 438540SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 448540SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 458540SN/Asystem.cpu.itb.hits 0 # DTB hits 468540SN/Asystem.cpu.itb.misses 0 # DTB misses 478540SN/Asystem.cpu.itb.accesses 0 # DTB accesses 488540SN/Asystem.cpu.workload.num_syscalls 8 # Number of system calls 499150SAli.Saidi@ARM.comsystem.cpu.numCycles 66798 # number of cpu cycles simulated 508540SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 518540SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 529150SAli.Saidi@ARM.comsystem.cpu.committedInsts 5814 # Number of instructions committed 539150SAli.Saidi@ARM.comsystem.cpu.committedOps 5814 # Number of ops (including micro ops) committed 549150SAli.Saidi@ARM.comsystem.cpu.num_int_alu_accesses 5113 # Number of integer alu accesses 558540SN/Asystem.cpu.num_fp_alu_accesses 2 # Number of float alu accesses 568540SN/Asystem.cpu.num_func_calls 194 # number of times a function call or return occured 579150SAli.Saidi@ARM.comsystem.cpu.num_conditional_control_insts 676 # number of instructions that are conditional controls 589150SAli.Saidi@ARM.comsystem.cpu.num_int_insts 5113 # number of integer instructions 598540SN/Asystem.cpu.num_fp_insts 2 # number of float instructions 609150SAli.Saidi@ARM.comsystem.cpu.num_int_register_reads 7284 # number of times the integer registers were read 619150SAli.Saidi@ARM.comsystem.cpu.num_int_register_writes 3397 # number of times the integer registers were written 628540SN/Asystem.cpu.num_fp_register_reads 3 # number of times the floating registers were read 638540SN/Asystem.cpu.num_fp_register_writes 1 # number of times the floating registers were written 649150SAli.Saidi@ARM.comsystem.cpu.num_mem_refs 2089 # number of memory refs 659150SAli.Saidi@ARM.comsystem.cpu.num_load_insts 1163 # Number of load instructions 668540SN/Asystem.cpu.num_store_insts 926 # Number of store instructions 678540SN/Asystem.cpu.num_idle_cycles 0 # Number of idle cycles 689150SAli.Saidi@ARM.comsystem.cpu.num_busy_cycles 66798 # Number of busy cycles 698540SN/Asystem.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 708540SN/Asystem.cpu.idle_fraction 0 # Percentage of idle cycles 718540SN/Asystem.cpu.icache.replacements 13 # number of replacements 729150SAli.Saidi@ARM.comsystem.cpu.icache.tagsinuse 133.141027 # Cycle average of tags in use 739150SAli.Saidi@ARM.comsystem.cpu.icache.total_refs 5513 # Total number of references to valid blocks. 748540SN/Asystem.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. 759150SAli.Saidi@ARM.comsystem.cpu.icache.avg_refs 18.194719 # Average number of references to valid blocks. 768540SN/Asystem.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 779150SAli.Saidi@ARM.comsystem.cpu.icache.occ_blocks::cpu.inst 133.141027 # Average occupied blocks per requestor 789150SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::cpu.inst 0.065010 # Average percentage of cache occupancy 799150SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::total 0.065010 # Average percentage of cache occupancy 809150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::cpu.inst 5513 # number of ReadReq hits 819150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::total 5513 # number of ReadReq hits 829150SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::cpu.inst 5513 # number of demand (read+write) hits 839150SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::total 5513 # number of demand (read+write) hits 849150SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::cpu.inst 5513 # number of overall hits 859150SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::total 5513 # number of overall hits 868835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::cpu.inst 303 # number of ReadReq misses 878835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::total 303 # number of ReadReq misses 888835SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::cpu.inst 303 # number of demand (read+write) misses 898835SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::total 303 # number of demand (read+write) misses 908835SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::cpu.inst 303 # number of overall misses 918835SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::total 303 # number of overall misses 928835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 16884000 # number of ReadReq miss cycles 938835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_latency::total 16884000 # number of ReadReq miss cycles 948835SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_latency::cpu.inst 16884000 # number of demand (read+write) miss cycles 958835SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_latency::total 16884000 # number of demand (read+write) miss cycles 968835SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_latency::cpu.inst 16884000 # number of overall miss cycles 978835SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_latency::total 16884000 # number of overall miss cycles 989150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 5816 # number of ReadReq accesses(hits+misses) 999150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::total 5816 # number of ReadReq accesses(hits+misses) 1009150SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::cpu.inst 5816 # number of demand (read+write) accesses 1019150SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::total 5816 # number of demand (read+write) accesses 1029150SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::cpu.inst 5816 # number of overall (read+write) accesses 1039150SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::total 5816 # number of overall (read+write) accesses 1049150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052098 # miss rate for ReadReq accesses 1059150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::total 0.052098 # miss rate for ReadReq accesses 1069150SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.052098 # miss rate for demand accesses 1079150SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::total 0.052098 # miss rate for demand accesses 1089150SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.052098 # miss rate for overall accesses 1099150SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::total 0.052098 # miss rate for overall accesses 1108835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55722.772277 # average ReadReq miss latency 1119055Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_avg_miss_latency::total 55722.772277 # average ReadReq miss latency 1128835SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency 1139055Ssaidi@eecs.umich.edusystem.cpu.icache.demand_avg_miss_latency::total 55722.772277 # average overall miss latency 1148835SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency 1159055Ssaidi@eecs.umich.edusystem.cpu.icache.overall_avg_miss_latency::total 55722.772277 # average overall miss latency 1168540SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1178540SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1188540SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1198540SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 1208983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1218983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1228540SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 1238540SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 1248835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 303 # number of ReadReq MSHR misses 1258835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::total 303 # number of ReadReq MSHR misses 1268835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 303 # number of demand (read+write) MSHR misses 1278835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::total 303 # number of demand (read+write) MSHR misses 1288835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 303 # number of overall MSHR misses 1298835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::total 303 # number of overall MSHR misses 1308835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15975000 # number of ReadReq MSHR miss cycles 1318835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 15975000 # number of ReadReq MSHR miss cycles 1328835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 15975000 # number of demand (read+write) MSHR miss cycles 1338835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::total 15975000 # number of demand (read+write) MSHR miss cycles 1348835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 15975000 # number of overall MSHR miss cycles 1358835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::total 15975000 # number of overall MSHR miss cycles 1369150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052098 # mshr miss rate for ReadReq accesses 1379150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.052098 # mshr miss rate for ReadReq accesses 1389150SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052098 # mshr miss rate for demand accesses 1399150SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.052098 # mshr miss rate for demand accesses 1409150SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052098 # mshr miss rate for overall accesses 1419150SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.052098 # mshr miss rate for overall accesses 1428835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52722.772277 # average ReadReq mshr miss latency 1439055Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52722.772277 # average ReadReq mshr miss latency 1448835SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency 1459055Ssaidi@eecs.umich.edusystem.cpu.icache.demand_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency 1468835SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency 1479055Ssaidi@eecs.umich.edusystem.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency 1488540SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1498540SN/Asystem.cpu.dcache.replacements 0 # number of replacements 1509150SAli.Saidi@ARM.comsystem.cpu.dcache.tagsinuse 87.742269 # Cycle average of tags in use 1519150SAli.Saidi@ARM.comsystem.cpu.dcache.total_refs 1950 # Total number of references to valid blocks. 1528540SN/Asystem.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. 1539150SAli.Saidi@ARM.comsystem.cpu.dcache.avg_refs 14.130435 # Average number of references to valid blocks. 1548540SN/Asystem.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1559150SAli.Saidi@ARM.comsystem.cpu.dcache.occ_blocks::cpu.data 87.742269 # Average occupied blocks per requestor 1569150SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::cpu.data 0.021421 # Average percentage of cache occupancy 1579150SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::total 0.021421 # Average percentage of cache occupancy 1589150SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1076 # number of ReadReq hits 1599150SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_hits::total 1076 # number of ReadReq hits 1608835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::cpu.data 874 # number of WriteReq hits 1618835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::total 874 # number of WriteReq hits 1629150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_hits::cpu.data 1950 # number of demand (read+write) hits 1639150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_hits::total 1950 # number of demand (read+write) hits 1649150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_hits::cpu.data 1950 # number of overall hits 1659150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_hits::total 1950 # number of overall hits 1668835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses 1678835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses 1688835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::cpu.data 51 # number of WriteReq misses 1698835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::total 51 # number of WriteReq misses 1708835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses 1718835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses 1728835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses 1738835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::total 138 # number of overall misses 1748835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 4872000 # number of ReadReq miss cycles 1758835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_latency::total 4872000 # number of ReadReq miss cycles 1768835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 2856000 # number of WriteReq miss cycles 1778835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_latency::total 2856000 # number of WriteReq miss cycles 1788835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_latency::cpu.data 7728000 # number of demand (read+write) miss cycles 1798835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_latency::total 7728000 # number of demand (read+write) miss cycles 1808835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_latency::cpu.data 7728000 # number of overall miss cycles 1818835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_latency::total 7728000 # number of overall miss cycles 1829150SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) 1839150SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) 1848835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 1858835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 1869150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_accesses::cpu.data 2088 # number of demand (read+write) accesses 1879150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_accesses::total 2088 # number of demand (read+write) accesses 1889150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_accesses::cpu.data 2088 # number of overall (read+write) accesses 1899150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_accesses::total 2088 # number of overall (read+write) accesses 1909150SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074807 # miss rate for ReadReq accesses 1919150SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.074807 # miss rate for ReadReq accesses 1928835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055135 # miss rate for WriteReq accesses 1939055Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_miss_rate::total 0.055135 # miss rate for WriteReq accesses 1949150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.066092 # miss rate for demand accesses 1959150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::total 0.066092 # miss rate for demand accesses 1969150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.066092 # miss rate for overall accesses 1979150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_rate::total 0.066092 # miss rate for overall accesses 1988835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency 1999055Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency 2008835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency 2019055Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency 2028835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency 2039055Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency 2048835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency 2059055Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency 2068540SN/Asystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2078540SN/Asystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2088540SN/Asystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2098540SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 2108983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2118983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2128540SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 2133041SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 2148835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses 2158835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses 2168835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses 2178835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses 2188835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses 2198835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses 2208835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses 2218835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses 2228835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4611000 # number of ReadReq MSHR miss cycles 2238835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 4611000 # number of ReadReq MSHR miss cycles 2248835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2703000 # number of WriteReq MSHR miss cycles 2258835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 2703000 # number of WriteReq MSHR miss cycles 2268835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles 2278835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles 2288835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles 2298835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles 2309150SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses 2319150SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses 2328835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses 2339055Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses 2349150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for demand accesses 2359150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses 2369150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses 2379150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses 2388835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency 2399055Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency 2408835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 2419055Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 2428835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 2439055Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 2448835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 2459055Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 2468540SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2478540SN/Asystem.cpu.l2cache.replacements 0 # number of replacements 2489150SAli.Saidi@ARM.comsystem.cpu.l2cache.tagsinuse 188.881290 # Cycle average of tags in use 2498540SN/Asystem.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. 2508540SN/Asystem.cpu.l2cache.sampled_refs 388 # Sample count of references to valid blocks. 2518540SN/Asystem.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks. 2528540SN/Asystem.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2539150SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_blocks::cpu.inst 134.495649 # Average occupied blocks per requestor 2549150SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_blocks::cpu.data 54.385641 # Average occupied blocks per requestor 2559150SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::cpu.inst 0.004104 # Average percentage of cache occupancy 2569150SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::cpu.data 0.001660 # Average percentage of cache occupancy 2579150SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::total 0.005764 # Average percentage of cache occupancy 2588835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits 2598835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits 2608835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 2618835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 2628835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 2638835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 2 # number of overall hits 2648835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 301 # number of ReadReq misses 2658835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses 2668835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::total 388 # number of ReadReq misses 2678835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses 2688835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses 2698835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.inst 301 # number of demand (read+write) misses 2708835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses 2718835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::total 439 # number of demand (read+write) misses 2728835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses 2738835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses 2748835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::total 439 # number of overall misses 2758835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15652000 # number of ReadReq miss cycles 2768835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 4524000 # number of ReadReq miss cycles 2778835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::total 20176000 # number of ReadReq miss cycles 2788835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2652000 # number of ReadExReq miss cycles 2798835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 2652000 # number of ReadExReq miss cycles 2808835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 15652000 # number of demand (read+write) miss cycles 2818835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 7176000 # number of demand (read+write) miss cycles 2828835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::total 22828000 # number of demand (read+write) miss cycles 2838835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 15652000 # number of overall miss cycles 2848835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 7176000 # number of overall miss cycles 2858835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::total 22828000 # number of overall miss cycles 2868835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 303 # number of ReadReq accesses(hits+misses) 2878835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) 2888835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::total 390 # number of ReadReq accesses(hits+misses) 2898835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) 2908835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) 2918835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.inst 303 # number of demand (read+write) accesses 2928835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses 2938835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses 2948835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.inst 303 # number of overall (read+write) accesses 2958835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses 2968835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses 2978835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993399 # miss rate for ReadReq accesses 2988835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 2999055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_miss_rate::total 0.994872 # miss rate for ReadReq accesses 3008835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 3019055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 3028835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.993399 # miss rate for demand accesses 3038835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 3049055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_miss_rate::total 0.995465 # miss rate for demand accesses 3058835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.993399 # miss rate for overall accesses 3068835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 3079055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_miss_rate::total 0.995465 # miss rate for overall accesses 3088835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 3098835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 3109055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 3118835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 3129055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 3138835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 3148835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 3159055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 3168835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 3178835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 3189055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency 3198540SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3208540SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3218540SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 3228540SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 3238983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3248983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3258540SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 3263041SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 3278835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses 3288835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses 3298835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 388 # number of ReadReq MSHR misses 3308835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses 3318835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses 3328835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses 3338835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses 3348835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::total 439 # number of demand (read+write) MSHR misses 3358835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses 3368835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses 3378835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::total 439 # number of overall MSHR misses 3388835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12040000 # number of ReadReq MSHR miss cycles 3398835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3480000 # number of ReadReq MSHR miss cycles 3408835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 15520000 # number of ReadReq MSHR miss cycles 3418835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2040000 # number of ReadExReq MSHR miss cycles 3428835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2040000 # number of ReadExReq MSHR miss cycles 3438835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12040000 # number of demand (read+write) MSHR miss cycles 3448835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5520000 # number of demand (read+write) MSHR miss cycles 3458835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 17560000 # number of demand (read+write) MSHR miss cycles 3468835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12040000 # number of overall MSHR miss cycles 3478835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 # number of overall MSHR miss cycles 3488835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 17560000 # number of overall MSHR miss cycles 3498835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for ReadReq accesses 3508835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 3519055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994872 # mshr miss rate for ReadReq accesses 3528835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 3539055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 3548835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for demand accesses 3558835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 3569055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_mshr_miss_rate::total 0.995465 # mshr miss rate for demand accesses 3578835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for overall accesses 3588835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 3599055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_mshr_miss_rate::total 0.995465 # mshr miss rate for overall accesses 3608835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 3618835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 3629055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 3638835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 3649055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 3658835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 3668835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 3679055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 3688835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 3698835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 3709055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 3718540SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 3723021SN/A 3733021SN/A---------- End Simulation Statistics ---------- 374