stats.txt revision 8540
111507SCurtis.Dunham@arm.com 211507SCurtis.Dunham@arm.com---------- Begin Simulation Statistics ---------- 311680SCurtis.Dunham@arm.comsim_seconds 0.000032 # Number of seconds simulated 411680SCurtis.Dunham@arm.comsim_ticks 32088000 # Number of ticks simulated 511680SCurtis.Dunham@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 611507SCurtis.Dunham@arm.comhost_inst_rate 266984 # Simulator instruction rate (inst/s) 711687Sandreas.hansson@arm.comhost_tick_rate 1467506046 # Simulator tick rate (ticks/s) 811687Sandreas.hansson@arm.comhost_mem_usage 241568 # Number of bytes of host memory used 911687Sandreas.hansson@arm.comhost_seconds 0.02 # Real time elapsed on the host 1011687Sandreas.hansson@arm.comsim_insts 5827 # Number of instructions simulated 1111687Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 0 # DTB read hits 1211507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_misses 0 # DTB read misses 1311507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 1411507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_hits 0 # DTB write hits 1511507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_misses 0 # DTB write misses 1611680SCurtis.Dunham@arm.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 1711570SCurtis.Dunham@arm.comsystem.cpu.dtb.hits 0 # DTB hits 1811507SCurtis.Dunham@arm.comsystem.cpu.dtb.misses 0 # DTB misses 1911570SCurtis.Dunham@arm.comsystem.cpu.dtb.accesses 0 # DTB accesses 2011570SCurtis.Dunham@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 2111570SCurtis.Dunham@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 2211570SCurtis.Dunham@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 2311507SCurtis.Dunham@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 2411570SCurtis.Dunham@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 2511680SCurtis.Dunham@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 2611680SCurtis.Dunham@arm.comsystem.cpu.itb.hits 0 # DTB hits 2711680SCurtis.Dunham@arm.comsystem.cpu.itb.misses 0 # DTB misses 2811680SCurtis.Dunham@arm.comsystem.cpu.itb.accesses 0 # DTB accesses 2911680SCurtis.Dunham@arm.comsystem.cpu.workload.num_syscalls 8 # Number of system calls 3011680SCurtis.Dunham@arm.comsystem.cpu.numCycles 64176 # number of cpu cycles simulated 3111680SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 3211680SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 3311570SCurtis.Dunham@arm.comsystem.cpu.num_insts 5827 # Number of instructions executed 3411507SCurtis.Dunham@arm.comsystem.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses 3511570SCurtis.Dunham@arm.comsystem.cpu.num_fp_alu_accesses 2 # Number of float alu accesses 3611507SCurtis.Dunham@arm.comsystem.cpu.num_func_calls 194 # number of times a function call or return occured 3711570SCurtis.Dunham@arm.comsystem.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls 3811507SCurtis.Dunham@arm.comsystem.cpu.num_int_insts 5126 # number of integer instructions 3911507SCurtis.Dunham@arm.comsystem.cpu.num_fp_insts 2 # number of float instructions 4011570SCurtis.Dunham@arm.comsystem.cpu.num_int_register_reads 7300 # number of times the integer registers were read 4111507SCurtis.Dunham@arm.comsystem.cpu.num_int_register_writes 3409 # number of times the integer registers were written 4211507SCurtis.Dunham@arm.comsystem.cpu.num_fp_register_reads 3 # number of times the floating registers were read 4311507SCurtis.Dunham@arm.comsystem.cpu.num_fp_register_writes 1 # number of times the floating registers were written 4411507SCurtis.Dunham@arm.comsystem.cpu.num_mem_refs 2090 # number of memory refs 4511507SCurtis.Dunham@arm.comsystem.cpu.num_load_insts 1164 # Number of load instructions 4611507SCurtis.Dunham@arm.comsystem.cpu.num_store_insts 926 # Number of store instructions 4711507SCurtis.Dunham@arm.comsystem.cpu.num_idle_cycles 0 # Number of idle cycles 4811507SCurtis.Dunham@arm.comsystem.cpu.num_busy_cycles 64176 # Number of busy cycles 4911507SCurtis.Dunham@arm.comsystem.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 5011507SCurtis.Dunham@arm.comsystem.cpu.idle_fraction 0 # Percentage of idle cycles 5111507SCurtis.Dunham@arm.comsystem.cpu.icache.replacements 13 # number of replacements 5211507SCurtis.Dunham@arm.comsystem.cpu.icache.tagsinuse 132.493866 # Cycle average of tags in use 5311507SCurtis.Dunham@arm.comsystem.cpu.icache.total_refs 5526 # Total number of references to valid blocks. 5411507SCurtis.Dunham@arm.comsystem.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. 5511570SCurtis.Dunham@arm.comsystem.cpu.icache.avg_refs 18.237624 # Average number of references to valid blocks. 5611507SCurtis.Dunham@arm.comsystem.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 5711507SCurtis.Dunham@arm.comsystem.cpu.icache.occ_blocks::0 132.493866 # Average occupied blocks per context 5811507SCurtis.Dunham@arm.comsystem.cpu.icache.occ_percent::0 0.064694 # Average percentage of cache occupancy 5911507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits 5526 # number of ReadReq hits 6011570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits 5526 # number of demand (read+write) hits 6111507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits 5526 # number of overall hits 6211507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses 303 # number of ReadReq misses 6311507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses 303 # number of demand (read+write) misses 6411507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses 303 # number of overall misses 6511507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency 16884000 # number of ReadReq miss cycles 6611507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency 16884000 # number of demand (read+write) miss cycles 6711507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency 16884000 # number of overall miss cycles 6811507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses 5829 # number of ReadReq accesses(hits+misses) 6911507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses 5829 # number of demand (read+write) accesses 7011507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses 5829 # number of overall (read+write) accesses 7111507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate 0.051981 # miss rate for ReadReq accesses 7211507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate 0.051981 # miss rate for demand accesses 7311507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate 0.051981 # miss rate for overall accesses 7411507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency 55722.772277 # average ReadReq miss latency 7511507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency 55722.772277 # average overall miss latency 7611507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency 55722.772277 # average overall miss latency 7711507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 7811507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 7911680SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 8011507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 8111507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 8211507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 8311507SCurtis.Dunham@arm.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 8411507SCurtis.Dunham@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 8511507SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks 0 # number of writebacks 8611570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 8711507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits 8811507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses 8911507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses 9011507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses 9111507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 9211507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency 15975000 # number of ReadReq MSHR miss cycles 9311507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency 15975000 # number of demand (read+write) MSHR miss cycles 9411680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency 15975000 # number of overall MSHR miss cycles 9511680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 9611680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate 0.051981 # mshr miss rate for ReadReq accesses 9711507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate 0.051981 # mshr miss rate for demand accesses 9811507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate 0.051981 # mshr miss rate for overall accesses 9911507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency 52722.772277 # average ReadReq mshr miss latency 10011507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency 10111507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency 10211507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 10311507SCurtis.Dunham@arm.comsystem.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 10411507SCurtis.Dunham@arm.comsystem.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 10511507SCurtis.Dunham@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 10611507SCurtis.Dunham@arm.comsystem.cpu.dcache.replacements 0 # number of replacements 10711507SCurtis.Dunham@arm.comsystem.cpu.dcache.tagsinuse 87.458397 # Cycle average of tags in use 10811507SCurtis.Dunham@arm.comsystem.cpu.dcache.total_refs 1951 # Total number of references to valid blocks. 10911507SCurtis.Dunham@arm.comsystem.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. 11011507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks. 11111507SCurtis.Dunham@arm.comsystem.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 11211507SCurtis.Dunham@arm.comsystem.cpu.dcache.occ_blocks::0 87.458397 # Average occupied blocks per context 11311507SCurtis.Dunham@arm.comsystem.cpu.dcache.occ_percent::0 0.021352 # Average percentage of cache occupancy 11411507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits 1077 # number of ReadReq hits 11511507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits 874 # number of WriteReq hits 11611507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits 1951 # number of demand (read+write) hits 11711507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits 1951 # number of overall hits 11811507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses 87 # number of ReadReq misses 11911507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses 51 # number of WriteReq misses 12011507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses 138 # number of demand (read+write) misses 12111507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses 138 # number of overall misses 12211507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency 4872000 # number of ReadReq miss cycles 12311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency 2856000 # number of WriteReq miss cycles 12411507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency 7728000 # number of demand (read+write) miss cycles 12511507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency 7728000 # number of overall miss cycles 12611507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses) 12711507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) 12811507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses 12911507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses 13011507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate 0.074742 # miss rate for ReadReq accesses 13111507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate 0.055135 # miss rate for WriteReq accesses 13211507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate 0.066060 # miss rate for demand accesses 13311507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate 0.066060 # miss rate for overall accesses 13411507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency 13511507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency 13611507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency 13711507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency 13811507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 13911507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 14011507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 14111507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 14211507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 14311507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 14411507SCurtis.Dunham@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 14511507SCurtis.Dunham@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 14611507SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks 0 # number of writebacks 14711507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 14811507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits 14911507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses 15011507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses 15111507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses 15211507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses 15311507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 15411507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency 4611000 # number of ReadReq MSHR miss cycles 15511507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency 2703000 # number of WriteReq MSHR miss cycles 15611507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency 7314000 # number of demand (read+write) MSHR miss cycles 15711507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency 7314000 # number of overall MSHR miss cycles 15811507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 15911507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate 0.074742 # mshr miss rate for ReadReq accesses 16011507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses 16111507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate 0.066060 # mshr miss rate for demand accesses 16211507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate 0.066060 # mshr miss rate for overall accesses 16311507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency 16411507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency 16511507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency 16611507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency 16711507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 16811507SCurtis.Dunham@arm.comsystem.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 16911507SCurtis.Dunham@arm.comsystem.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 17011507SCurtis.Dunham@arm.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 17111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.replacements 0 # number of replacements 17211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tagsinuse 188.045319 # Cycle average of tags in use 17311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. 17411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.sampled_refs 388 # Sample count of references to valid blocks. 17511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks. 17611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 17711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.occ_blocks::0 188.045319 # Average occupied blocks per context 17811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.occ_percent::0 0.005739 # Average percentage of cache occupancy 17911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits 18011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits 18111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits 2 # number of overall hits 18211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_misses 388 # number of ReadReq misses 18311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses 18411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses 439 # number of demand (read+write) misses 18511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses 439 # number of overall misses 18611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_miss_latency 20176000 # number of ReadReq miss cycles 18711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency 2652000 # number of ReadExReq miss cycles 18811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency 22828000 # number of demand (read+write) miss cycles 18911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency 22828000 # number of overall miss cycles 19011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_accesses 390 # number of ReadReq accesses(hits+misses) 19111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses) 19211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses 19311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses 19411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_miss_rate 0.994872 # miss rate for ReadReq accesses 19511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses 19611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate 0.995465 # miss rate for demand accesses 19711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate 0.995465 # miss rate for overall accesses 19811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency 19911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency 20011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency 20111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency 20211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 20311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 20411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 20511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 20611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 20711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 20811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 20911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 21011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.writebacks 0 # number of writebacks 21111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 21211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits 21311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses 388 # number of ReadReq MSHR misses 21411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses 21511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses 439 # number of demand (read+write) MSHR misses 21611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses 439 # number of overall MSHR misses 21711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 21811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency 15520000 # number of ReadReq MSHR miss cycles 21911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency 2040000 # number of ReadExReq MSHR miss cycles 22011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency 17560000 # number of demand (read+write) MSHR miss cycles 22111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency 17560000 # number of overall MSHR miss cycles 22211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 22311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate 0.994872 # mshr miss rate for ReadReq accesses 22411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses 22511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate 0.995465 # mshr miss rate for demand accesses 22611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate 0.995465 # mshr miss rate for overall accesses 22711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency 22811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency 22911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency 23011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency 23111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 23211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 23311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 23411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 23511680SCurtis.Dunham@arm.com 23611680SCurtis.Dunham@arm.com---------- End Simulation Statistics ---------- 23711680SCurtis.Dunham@arm.com