stats.txt revision 7927
1 2---------- Begin Simulation Statistics ---------- 3host_inst_rate 499743 # Simulator instruction rate (inst/s) 4host_mem_usage 205480 # Number of bytes of host memory used 5host_seconds 0.01 # Real time elapsed on the host 6host_tick_rate 2679135009 # Simulator tick rate (ticks/s) 7sim_freq 1000000000000 # Frequency of simulated ticks 8sim_insts 5827 # Number of instructions simulated 9sim_seconds 0.000032 # Number of seconds simulated 10sim_ticks 32088000 # Number of ticks simulated 11system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses) 12system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency 13system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency 14system.cpu.dcache.ReadReq_hits 1077 # number of ReadReq hits 15system.cpu.dcache.ReadReq_miss_latency 4872000 # number of ReadReq miss cycles 16system.cpu.dcache.ReadReq_miss_rate 0.074742 # miss rate for ReadReq accesses 17system.cpu.dcache.ReadReq_misses 87 # number of ReadReq misses 18system.cpu.dcache.ReadReq_mshr_miss_latency 4611000 # number of ReadReq MSHR miss cycles 19system.cpu.dcache.ReadReq_mshr_miss_rate 0.074742 # mshr miss rate for ReadReq accesses 20system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses 21system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) 22system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency 23system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency 24system.cpu.dcache.WriteReq_hits 874 # number of WriteReq hits 25system.cpu.dcache.WriteReq_miss_latency 2856000 # number of WriteReq miss cycles 26system.cpu.dcache.WriteReq_miss_rate 0.055135 # miss rate for WriteReq accesses 27system.cpu.dcache.WriteReq_misses 51 # number of WriteReq misses 28system.cpu.dcache.WriteReq_mshr_miss_latency 2703000 # number of WriteReq MSHR miss cycles 29system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses 30system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses 31system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 32system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 33system.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks. 34system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 35system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 36system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 37system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 38system.cpu.dcache.cache_copies 0 # number of cache copies performed 39system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses 40system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency 41system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency 42system.cpu.dcache.demand_hits 1951 # number of demand (read+write) hits 43system.cpu.dcache.demand_miss_latency 7728000 # number of demand (read+write) miss cycles 44system.cpu.dcache.demand_miss_rate 0.066060 # miss rate for demand accesses 45system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses 46system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 47system.cpu.dcache.demand_mshr_miss_latency 7314000 # number of demand (read+write) MSHR miss cycles 48system.cpu.dcache.demand_mshr_miss_rate 0.066060 # mshr miss rate for demand accesses 49system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses 50system.cpu.dcache.fast_writes 0 # number of fast writes performed 51system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 52system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 53system.cpu.dcache.occ_%::0 0.021352 # Average percentage of cache occupancy 54system.cpu.dcache.occ_blocks::0 87.458397 # Average occupied blocks per context 55system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses 56system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency 57system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency 58system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 59system.cpu.dcache.overall_hits 1951 # number of overall hits 60system.cpu.dcache.overall_miss_latency 7728000 # number of overall miss cycles 61system.cpu.dcache.overall_miss_rate 0.066060 # miss rate for overall accesses 62system.cpu.dcache.overall_misses 138 # number of overall misses 63system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits 64system.cpu.dcache.overall_mshr_miss_latency 7314000 # number of overall MSHR miss cycles 65system.cpu.dcache.overall_mshr_miss_rate 0.066060 # mshr miss rate for overall accesses 66system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses 67system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 68system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 69system.cpu.dcache.replacements 0 # number of replacements 70system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. 71system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 72system.cpu.dcache.tagsinuse 87.458397 # Cycle average of tags in use 73system.cpu.dcache.total_refs 1951 # Total number of references to valid blocks. 74system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 75system.cpu.dcache.writebacks 0 # number of writebacks 76system.cpu.dtb.accesses 0 # DTB accesses 77system.cpu.dtb.hits 0 # DTB hits 78system.cpu.dtb.misses 0 # DTB misses 79system.cpu.dtb.read_accesses 0 # DTB read accesses 80system.cpu.dtb.read_hits 0 # DTB read hits 81system.cpu.dtb.read_misses 0 # DTB read misses 82system.cpu.dtb.write_accesses 0 # DTB write accesses 83system.cpu.dtb.write_hits 0 # DTB write hits 84system.cpu.dtb.write_misses 0 # DTB write misses 85system.cpu.icache.ReadReq_accesses 5829 # number of ReadReq accesses(hits+misses) 86system.cpu.icache.ReadReq_avg_miss_latency 55722.772277 # average ReadReq miss latency 87system.cpu.icache.ReadReq_avg_mshr_miss_latency 52722.772277 # average ReadReq mshr miss latency 88system.cpu.icache.ReadReq_hits 5526 # number of ReadReq hits 89system.cpu.icache.ReadReq_miss_latency 16884000 # number of ReadReq miss cycles 90system.cpu.icache.ReadReq_miss_rate 0.051981 # miss rate for ReadReq accesses 91system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses 92system.cpu.icache.ReadReq_mshr_miss_latency 15975000 # number of ReadReq MSHR miss cycles 93system.cpu.icache.ReadReq_mshr_miss_rate 0.051981 # mshr miss rate for ReadReq accesses 94system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses 95system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 96system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 97system.cpu.icache.avg_refs 18.237624 # Average number of references to valid blocks. 98system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 99system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 100system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 101system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 102system.cpu.icache.cache_copies 0 # number of cache copies performed 103system.cpu.icache.demand_accesses 5829 # number of demand (read+write) accesses 104system.cpu.icache.demand_avg_miss_latency 55722.772277 # average overall miss latency 105system.cpu.icache.demand_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency 106system.cpu.icache.demand_hits 5526 # number of demand (read+write) hits 107system.cpu.icache.demand_miss_latency 16884000 # number of demand (read+write) miss cycles 108system.cpu.icache.demand_miss_rate 0.051981 # miss rate for demand accesses 109system.cpu.icache.demand_misses 303 # number of demand (read+write) misses 110system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 111system.cpu.icache.demand_mshr_miss_latency 15975000 # number of demand (read+write) MSHR miss cycles 112system.cpu.icache.demand_mshr_miss_rate 0.051981 # mshr miss rate for demand accesses 113system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses 114system.cpu.icache.fast_writes 0 # number of fast writes performed 115system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 116system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 117system.cpu.icache.occ_%::0 0.064694 # Average percentage of cache occupancy 118system.cpu.icache.occ_blocks::0 132.493866 # Average occupied blocks per context 119system.cpu.icache.overall_accesses 5829 # number of overall (read+write) accesses 120system.cpu.icache.overall_avg_miss_latency 55722.772277 # average overall miss latency 121system.cpu.icache.overall_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency 122system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 123system.cpu.icache.overall_hits 5526 # number of overall hits 124system.cpu.icache.overall_miss_latency 16884000 # number of overall miss cycles 125system.cpu.icache.overall_miss_rate 0.051981 # miss rate for overall accesses 126system.cpu.icache.overall_misses 303 # number of overall misses 127system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits 128system.cpu.icache.overall_mshr_miss_latency 15975000 # number of overall MSHR miss cycles 129system.cpu.icache.overall_mshr_miss_rate 0.051981 # mshr miss rate for overall accesses 130system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses 131system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 132system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 133system.cpu.icache.replacements 13 # number of replacements 134system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. 135system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 136system.cpu.icache.tagsinuse 132.493866 # Cycle average of tags in use 137system.cpu.icache.total_refs 5526 # Total number of references to valid blocks. 138system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 139system.cpu.icache.writebacks 0 # number of writebacks 140system.cpu.idle_fraction 0 # Percentage of idle cycles 141system.cpu.itb.accesses 0 # DTB accesses 142system.cpu.itb.hits 0 # DTB hits 143system.cpu.itb.misses 0 # DTB misses 144system.cpu.itb.read_accesses 0 # DTB read accesses 145system.cpu.itb.read_hits 0 # DTB read hits 146system.cpu.itb.read_misses 0 # DTB read misses 147system.cpu.itb.write_accesses 0 # DTB write accesses 148system.cpu.itb.write_hits 0 # DTB write hits 149system.cpu.itb.write_misses 0 # DTB write misses 150system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses) 151system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency 152system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency 153system.cpu.l2cache.ReadExReq_miss_latency 2652000 # number of ReadExReq miss cycles 154system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses 155system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses 156system.cpu.l2cache.ReadExReq_mshr_miss_latency 2040000 # number of ReadExReq MSHR miss cycles 157system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses 158system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses 159system.cpu.l2cache.ReadReq_accesses 390 # number of ReadReq accesses(hits+misses) 160system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency 161system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency 162system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits 163system.cpu.l2cache.ReadReq_miss_latency 20176000 # number of ReadReq miss cycles 164system.cpu.l2cache.ReadReq_miss_rate 0.994872 # miss rate for ReadReq accesses 165system.cpu.l2cache.ReadReq_misses 388 # number of ReadReq misses 166system.cpu.l2cache.ReadReq_mshr_miss_latency 15520000 # number of ReadReq MSHR miss cycles 167system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994872 # mshr miss rate for ReadReq accesses 168system.cpu.l2cache.ReadReq_mshr_misses 388 # number of ReadReq MSHR misses 169system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 170system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 171system.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks. 172system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 173system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 174system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 175system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 176system.cpu.l2cache.cache_copies 0 # number of cache copies performed 177system.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses 178system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency 179system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency 180system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits 181system.cpu.l2cache.demand_miss_latency 22828000 # number of demand (read+write) miss cycles 182system.cpu.l2cache.demand_miss_rate 0.995465 # miss rate for demand accesses 183system.cpu.l2cache.demand_misses 439 # number of demand (read+write) misses 184system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 185system.cpu.l2cache.demand_mshr_miss_latency 17560000 # number of demand (read+write) MSHR miss cycles 186system.cpu.l2cache.demand_mshr_miss_rate 0.995465 # mshr miss rate for demand accesses 187system.cpu.l2cache.demand_mshr_misses 439 # number of demand (read+write) MSHR misses 188system.cpu.l2cache.fast_writes 0 # number of fast writes performed 189system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 190system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 191system.cpu.l2cache.occ_%::0 0.005739 # Average percentage of cache occupancy 192system.cpu.l2cache.occ_blocks::0 188.045319 # Average occupied blocks per context 193system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses 194system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency 195system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency 196system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 197system.cpu.l2cache.overall_hits 2 # number of overall hits 198system.cpu.l2cache.overall_miss_latency 22828000 # number of overall miss cycles 199system.cpu.l2cache.overall_miss_rate 0.995465 # miss rate for overall accesses 200system.cpu.l2cache.overall_misses 439 # number of overall misses 201system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits 202system.cpu.l2cache.overall_mshr_miss_latency 17560000 # number of overall MSHR miss cycles 203system.cpu.l2cache.overall_mshr_miss_rate 0.995465 # mshr miss rate for overall accesses 204system.cpu.l2cache.overall_mshr_misses 439 # number of overall MSHR misses 205system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 206system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 207system.cpu.l2cache.replacements 0 # number of replacements 208system.cpu.l2cache.sampled_refs 388 # Sample count of references to valid blocks. 209system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 210system.cpu.l2cache.tagsinuse 188.045319 # Cycle average of tags in use 211system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. 212system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 213system.cpu.l2cache.writebacks 0 # number of writebacks 214system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 215system.cpu.numCycles 64176 # number of cpu cycles simulated 216system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 217system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 218system.cpu.num_busy_cycles 64176 # Number of busy cycles 219system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls 220system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses 221system.cpu.num_fp_insts 2 # number of float instructions 222system.cpu.num_fp_register_reads 3 # number of times the floating registers were read 223system.cpu.num_fp_register_writes 1 # number of times the floating registers were written 224system.cpu.num_func_calls 194 # number of times a function call or return occured 225system.cpu.num_idle_cycles 0 # Number of idle cycles 226system.cpu.num_insts 5827 # Number of instructions executed 227system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses 228system.cpu.num_int_insts 5126 # number of integer instructions 229system.cpu.num_int_register_reads 7301 # number of times the integer registers were read 230system.cpu.num_int_register_writes 3409 # number of times the integer registers were written 231system.cpu.num_load_insts 1164 # Number of load instructions 232system.cpu.num_mem_refs 2090 # number of memory refs 233system.cpu.num_store_insts 926 # Number of store instructions 234system.cpu.workload.PROG:num_syscalls 8 # Number of system calls 235 236---------- End Simulation Statistics ---------- 237