stats.txt revision 11680
13021SN/A 23021SN/A---------- Begin Simulation Statistics ---------- 311201Sandreas.hansson@arm.comsim_seconds 0.000034 # Number of seconds simulated 411606Sandreas.sandberg@arm.comsim_ticks 34362500 # Number of ticks simulated 511606Sandreas.sandberg@arm.comfinal_tick 34362500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68540SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711606Sandreas.sandberg@arm.comhost_inst_rate 251821 # Simulator instruction rate (inst/s) 811606Sandreas.sandberg@arm.comhost_op_rate 251667 # Simulator op (including micro ops) rate (op/s) 911606Sandreas.sandberg@arm.comhost_tick_rate 1532173253 # Simulator tick rate (ticks/s) 1011606Sandreas.sandberg@arm.comhost_mem_usage 250252 # Number of bytes of host memory used 1111606Sandreas.sandberg@arm.comhost_seconds 0.02 # Real time elapsed on the host 1211390Ssteve.reinhardt@amd.comsim_insts 5641 # Number of instructions simulated 1311390Ssteve.reinhardt@amd.comsim_ops 5641 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611606Sandreas.sandberg@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states 1710488Snilay@cs.wisc.edusystem.physmem.bytes_read::cpu.inst 18752 # Number of bytes read from this memory 1810488Snilay@cs.wisc.edusystem.physmem.bytes_read::cpu.data 8768 # Number of bytes read from this memory 1910488Snilay@cs.wisc.edusystem.physmem.bytes_read::total 27520 # Number of bytes read from this memory 2010488Snilay@cs.wisc.edusystem.physmem.bytes_inst_read::cpu.inst 18752 # Number of instructions bytes read from this memory 2110488Snilay@cs.wisc.edusystem.physmem.bytes_inst_read::total 18752 # Number of instructions bytes read from this memory 2210488Snilay@cs.wisc.edusystem.physmem.num_reads::cpu.inst 293 # Number of read requests responded to by this memory 2310488Snilay@cs.wisc.edusystem.physmem.num_reads::cpu.data 137 # Number of read requests responded to by this memory 2410488Snilay@cs.wisc.edusystem.physmem.num_reads::total 430 # Number of read requests responded to by this memory 2511606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu.inst 545711168 # Total read bandwidth from this memory (bytes/s) 2611606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu.data 255161877 # Total read bandwidth from this memory (bytes/s) 2711606Sandreas.sandberg@arm.comsystem.physmem.bw_read::total 800873045 # Total read bandwidth from this memory (bytes/s) 2811606Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::cpu.inst 545711168 # Instruction read bandwidth from this memory (bytes/s) 2911606Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::total 545711168 # Instruction read bandwidth from this memory (bytes/s) 3011606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu.inst 545711168 # Total bandwidth to/from this memory (bytes/s) 3111606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu.data 255161877 # Total bandwidth to/from this memory (bytes/s) 3211606Sandreas.sandberg@arm.comsystem.physmem.bw_total::total 800873045 # Total bandwidth to/from this memory (bytes/s) 3311606Sandreas.sandberg@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states 3410036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 358540SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 368540SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 378540SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 388540SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 398540SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 408540SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 418540SN/Asystem.cpu.dtb.hits 0 # DTB hits 428540SN/Asystem.cpu.dtb.misses 0 # DTB misses 438540SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 448540SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 458540SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 468540SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 478540SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 488540SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 498540SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 508540SN/Asystem.cpu.itb.hits 0 # DTB hits 518540SN/Asystem.cpu.itb.misses 0 # DTB misses 528540SN/Asystem.cpu.itb.accesses 0 # DTB accesses 5310488Snilay@cs.wisc.edusystem.cpu.workload.num_syscalls 7 # Number of system calls 5411606Sandreas.sandberg@arm.comsystem.cpu.pwrStateResidencyTicks::ON 34362500 # Cumulative time (in ticks) in various power states 5511606Sandreas.sandberg@arm.comsystem.cpu.numCycles 68725 # number of cpu cycles simulated 568540SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 578540SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 5811390Ssteve.reinhardt@amd.comsystem.cpu.committedInsts 5641 # Number of instructions committed 5911390Ssteve.reinhardt@amd.comsystem.cpu.committedOps 5641 # Number of ops (including micro ops) committed 6011390Ssteve.reinhardt@amd.comsystem.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses 618540SN/Asystem.cpu.num_fp_alu_accesses 2 # Number of float alu accesses 6211390Ssteve.reinhardt@amd.comsystem.cpu.num_func_calls 191 # number of times a function call or return occured 6311390Ssteve.reinhardt@amd.comsystem.cpu.num_conditional_control_insts 651 # number of instructions that are conditional controls 6411390Ssteve.reinhardt@amd.comsystem.cpu.num_int_insts 4957 # number of integer instructions 658540SN/Asystem.cpu.num_fp_insts 2 # number of float instructions 6611390Ssteve.reinhardt@amd.comsystem.cpu.num_int_register_reads 7072 # number of times the integer registers were read 6711390Ssteve.reinhardt@amd.comsystem.cpu.num_int_register_writes 3291 # number of times the integer registers were written 688540SN/Asystem.cpu.num_fp_register_reads 3 # number of times the floating registers were read 698540SN/Asystem.cpu.num_fp_register_writes 1 # number of times the floating registers were written 7011390Ssteve.reinhardt@amd.comsystem.cpu.num_mem_refs 2037 # number of memory refs 7111390Ssteve.reinhardt@amd.comsystem.cpu.num_load_insts 1135 # Number of load instructions 7210488Snilay@cs.wisc.edusystem.cpu.num_store_insts 902 # Number of store instructions 738540SN/Asystem.cpu.num_idle_cycles 0 # Number of idle cycles 7411606Sandreas.sandberg@arm.comsystem.cpu.num_busy_cycles 68725 # Number of busy cycles 758540SN/Asystem.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 768540SN/Asystem.cpu.idle_fraction 0 # Percentage of idle cycles 7711390Ssteve.reinhardt@amd.comsystem.cpu.Branches 886 # Number of branches fetched 7811390Ssteve.reinhardt@amd.comsystem.cpu.op_class::No_OpClass 641 11.36% 11.36% # Class of executed instruction 7911390Ssteve.reinhardt@amd.comsystem.cpu.op_class::IntAlu 2960 52.46% 63.82% # Class of executed instruction 8011390Ssteve.reinhardt@amd.comsystem.cpu.op_class::IntMult 2 0.04% 63.86% # Class of executed instruction 8111390Ssteve.reinhardt@amd.comsystem.cpu.op_class::IntDiv 0 0.00% 63.86% # Class of executed instruction 8211390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatAdd 2 0.04% 63.90% # Class of executed instruction 8311390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction 8411390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction 8511390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction 8611390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction 8711390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction 8811390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction 8911390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction 9011390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdAlu 0 0.00% 63.90% # Class of executed instruction 9111390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdCmp 0 0.00% 63.90% # Class of executed instruction 9211390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdCvt 0 0.00% 63.90% # Class of executed instruction 9311390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdMisc 0 0.00% 63.90% # Class of executed instruction 9411390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdMult 0 0.00% 63.90% # Class of executed instruction 9511390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdMultAcc 0 0.00% 63.90% # Class of executed instruction 9611390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdShift 0 0.00% 63.90% # Class of executed instruction 9711390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdShiftAcc 0 0.00% 63.90% # Class of executed instruction 9811390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdSqrt 0 0.00% 63.90% # Class of executed instruction 9911390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatAdd 0 0.00% 63.90% # Class of executed instruction 10011390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatAlu 0 0.00% 63.90% # Class of executed instruction 10111390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatCmp 0 0.00% 63.90% # Class of executed instruction 10211390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatCvt 0 0.00% 63.90% # Class of executed instruction 10311390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatDiv 0 0.00% 63.90% # Class of executed instruction 10411390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatMisc 0 0.00% 63.90% # Class of executed instruction 10511390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction 10611390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction 10711390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction 10811390Ssteve.reinhardt@amd.comsystem.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction 10911390Ssteve.reinhardt@amd.comsystem.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction 11010220Sandreas.hansson@arm.comsystem.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 11110220Sandreas.hansson@arm.comsystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 11211390Ssteve.reinhardt@amd.comsystem.cpu.op_class::total 5642 # Class of executed instruction 11311606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states 1149838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 11511606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.tagsinuse 86.019878 # Cycle average of tags in use 11611390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.total_refs 1899 # Total number of references to valid blocks. 11710488Snilay@cs.wisc.edusystem.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. 11811390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.avg_refs 13.861314 # Average number of references to valid blocks. 1199838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 12011606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 86.019878 # Average occupied blocks per requestor 12111606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.021001 # Average percentage of cache occupancy 12211606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.021001 # Average percentage of cache occupancy 12310488Snilay@cs.wisc.edusystem.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id 12411201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id 12511201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 115 # Occupied blocks per task id 12610488Snilay@cs.wisc.edusystem.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id 12711390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.tag_accesses 4209 # Number of tag accesses 12811390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.data_accesses 4209 # Number of data accesses 12911606Sandreas.sandberg@arm.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states 13011390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits 13111390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits 13210488Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits 13310488Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits 13411390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_hits::cpu.data 1899 # number of demand (read+write) hits 13511390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_hits::total 1899 # number of demand (read+write) hits 13611390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_hits::cpu.data 1899 # number of overall hits 13711390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_hits::total 1899 # number of overall hits 1389481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses 1399481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses 14010488Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses 14110488Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::total 50 # number of WriteReq misses 14210488Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::cpu.data 137 # number of demand (read+write) misses 14310488Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses 14410488Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses 14510488Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::total 137 # number of overall misses 14611606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 5481000 # number of ReadReq miss cycles 14711606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 5481000 # number of ReadReq miss cycles 14811606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 3150000 # number of WriteReq miss cycles 14911606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 3150000 # number of WriteReq miss cycles 15011606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 8631000 # number of demand (read+write) miss cycles 15111606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_miss_latency::total 8631000 # number of demand (read+write) miss cycles 15211606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 8631000 # number of overall miss cycles 15311606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_miss_latency::total 8631000 # number of overall miss cycles 15411390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1135 # number of ReadReq accesses(hits+misses) 15511390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_accesses::total 1135 # number of ReadReq accesses(hits+misses) 15610488Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) 15710488Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) 15811390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_accesses::cpu.data 2036 # number of demand (read+write) accesses 15911390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_accesses::total 2036 # number of demand (read+write) accesses 16011390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_accesses::cpu.data 2036 # number of overall (read+write) accesses 16111390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_accesses::total 2036 # number of overall (read+write) accesses 16211390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076652 # miss rate for ReadReq accesses 16311390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.076652 # miss rate for ReadReq accesses 16410488Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses 16510488Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses 16611390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.067289 # miss rate for demand accesses 16711390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_miss_rate::total 0.067289 # miss rate for demand accesses 16811390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.067289 # miss rate for overall accesses 16911390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_miss_rate::total 0.067289 # miss rate for overall accesses 17011606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency 17111606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency 17211606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency 17311606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency 17411606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency 17511606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency 17611606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency 17711606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency 1789481Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1799481Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1809481Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1819481Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1829481Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1839481Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1849481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses 1859481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses 18610488Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses 18710488Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses 18810488Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses 18910488Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses 19010488Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses 19110488Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses 19211606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5394000 # number of ReadReq MSHR miss cycles 19311606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 5394000 # number of ReadReq MSHR miss cycles 19411606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3100000 # number of WriteReq MSHR miss cycles 19511606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 3100000 # number of WriteReq MSHR miss cycles 19611606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 8494000 # number of demand (read+write) MSHR miss cycles 19711606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 8494000 # number of demand (read+write) MSHR miss cycles 19811606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 8494000 # number of overall MSHR miss cycles 19911606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 8494000 # number of overall MSHR miss cycles 20011390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076652 # mshr miss rate for ReadReq accesses 20111390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076652 # mshr miss rate for ReadReq accesses 20210488Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses 20310488Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses 20411390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for demand accesses 20511390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.067289 # mshr miss rate for demand accesses 20611390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for overall accesses 20711390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.067289 # mshr miss rate for overall accesses 20811606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency 20911606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency 21011606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency 21111606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency 21211606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency 21311606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency 21411606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency 21511606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency 21611606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states 21710726Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 13 # number of replacements 21811606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.tagsinuse 128.944610 # Cycle average of tags in use 21911390Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.total_refs 5348 # Total number of references to valid blocks. 22010726Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. 22111390Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.avg_refs 18.128814 # Average number of references to valid blocks. 22210726Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 22311606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 128.944610 # Average occupied blocks per requestor 22411606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.062961 # Average percentage of cache occupancy 22511606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.occ_percent::total 0.062961 # Average percentage of cache occupancy 22610726Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id 22711201Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id 22811201Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id 22910726Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.137695 # Percentage of cache occupancy per task id 23011390Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.tag_accesses 11581 # Number of tag accesses 23111390Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.data_accesses 11581 # Number of data accesses 23211606Sandreas.sandberg@arm.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states 23311390Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_hits::cpu.inst 5348 # number of ReadReq hits 23411390Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_hits::total 5348 # number of ReadReq hits 23511390Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_hits::cpu.inst 5348 # number of demand (read+write) hits 23611390Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_hits::total 5348 # number of demand (read+write) hits 23711390Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_hits::cpu.inst 5348 # number of overall hits 23811390Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_hits::total 5348 # number of overall hits 23910726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 295 # number of ReadReq misses 24010726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 295 # number of ReadReq misses 24110726Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 295 # number of demand (read+write) misses 24210726Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 295 # number of demand (read+write) misses 24310726Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 295 # number of overall misses 24410726Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 295 # number of overall misses 24511606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 18485500 # number of ReadReq miss cycles 24611606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 18485500 # number of ReadReq miss cycles 24711606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 18485500 # number of demand (read+write) miss cycles 24811606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_miss_latency::total 18485500 # number of demand (read+write) miss cycles 24911606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 18485500 # number of overall miss cycles 25011606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_miss_latency::total 18485500 # number of overall miss cycles 25111390Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 5643 # number of ReadReq accesses(hits+misses) 25211390Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_accesses::total 5643 # number of ReadReq accesses(hits+misses) 25311390Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_accesses::cpu.inst 5643 # number of demand (read+write) accesses 25411390Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_accesses::total 5643 # number of demand (read+write) accesses 25511390Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_accesses::cpu.inst 5643 # number of overall (read+write) accesses 25611390Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_accesses::total 5643 # number of overall (read+write) accesses 25711390Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052277 # miss rate for ReadReq accesses 25811390Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_miss_rate::total 0.052277 # miss rate for ReadReq accesses 25911390Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.052277 # miss rate for demand accesses 26011390Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_miss_rate::total 0.052277 # miss rate for demand accesses 26111390Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.052277 # miss rate for overall accesses 26211390Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_miss_rate::total 0.052277 # miss rate for overall accesses 26311606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62662.711864 # average ReadReq miss latency 26411606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 62662.711864 # average ReadReq miss latency 26511606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 62662.711864 # average overall miss latency 26611606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 62662.711864 # average overall miss latency 26711606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 62662.711864 # average overall miss latency 26811606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 62662.711864 # average overall miss latency 26910726Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 27010726Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 27110726Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 27210726Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 27310726Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 27410726Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 27511201Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::writebacks 13 # number of writebacks 27611201Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::total 13 # number of writebacks 27710726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 295 # number of ReadReq MSHR misses 27810726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 295 # number of ReadReq MSHR misses 27910726Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 295 # number of demand (read+write) MSHR misses 28010726Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 295 # number of demand (read+write) MSHR misses 28110726Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 295 # number of overall MSHR misses 28210726Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 295 # number of overall MSHR misses 28311606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18190500 # number of ReadReq MSHR miss cycles 28411606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 18190500 # number of ReadReq MSHR miss cycles 28511606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 18190500 # number of demand (read+write) MSHR miss cycles 28611606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 18190500 # number of demand (read+write) MSHR miss cycles 28711606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 18190500 # number of overall MSHR miss cycles 28811606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 18190500 # number of overall MSHR miss cycles 28911390Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for ReadReq accesses 29011390Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.052277 # mshr miss rate for ReadReq accesses 29111390Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for demand accesses 29211390Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.052277 # mshr miss rate for demand accesses 29311390Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for overall accesses 29411390Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.052277 # mshr miss rate for overall accesses 29511606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61662.711864 # average ReadReq mshr miss latency 29611606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61662.711864 # average ReadReq mshr miss latency 29711606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61662.711864 # average overall mshr miss latency 29811606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 61662.711864 # average overall mshr miss latency 29911606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61662.711864 # average overall mshr miss latency 30011606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 61662.711864 # average overall mshr miss latency 30111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states 30210726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 30311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.tagsinuse 216.139082 # Cycle average of tags in use 30410892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks. 30511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.sampled_refs 430 # Sample count of references to valid blocks. 30611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.avg_refs 0.034884 # Average number of references to valid blocks. 30710726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 30811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 130.077342 # Average occupied blocks per requestor 30911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 86.061740 # Average occupied blocks per requestor 31011390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.003970 # Average percentage of cache occupancy 31111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.002626 # Average percentage of cache occupancy 31211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.006596 # Average percentage of cache occupancy 31311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 430 # Occupied blocks per task id 31411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id 31511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id 31611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.013123 # Percentage of cache occupancy per task id 31710892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 3990 # Number of tag accesses 31810892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 3990 # Number of data accesses 31911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states 32011201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 13 # number of WritebackClean hits 32111201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 13 # number of WritebackClean hits 32210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits 32310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits 32410726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 32510726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 32610726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 32710726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 2 # number of overall hits 32810726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 50 # number of ReadExReq misses 32910726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 50 # number of ReadExReq misses 33010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 293 # number of ReadCleanReq misses 33110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 293 # number of ReadCleanReq misses 33210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 87 # number of ReadSharedReq misses 33310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 87 # number of ReadSharedReq misses 33410726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 293 # number of demand (read+write) misses 33510726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 137 # number of demand (read+write) misses 33610726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 430 # number of demand (read+write) misses 33710726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 293 # number of overall misses 33810726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 137 # number of overall misses 33910726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 430 # number of overall misses 34011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3025000 # number of ReadExReq miss cycles 34111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 3025000 # number of ReadExReq miss cycles 34211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 17727000 # number of ReadCleanReq miss cycles 34311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 17727000 # number of ReadCleanReq miss cycles 34411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5263500 # number of ReadSharedReq miss cycles 34511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 5263500 # number of ReadSharedReq miss cycles 34611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 17727000 # number of demand (read+write) miss cycles 34711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 8288500 # number of demand (read+write) miss cycles 34811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_latency::total 26015500 # number of demand (read+write) miss cycles 34911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 17727000 # number of overall miss cycles 35011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 8288500 # number of overall miss cycles 35111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_latency::total 26015500 # number of overall miss cycles 35211201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 13 # number of WritebackClean accesses(hits+misses) 35311201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 13 # number of WritebackClean accesses(hits+misses) 35410726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) 35510726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) 35610892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 295 # number of ReadCleanReq accesses(hits+misses) 35710892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 295 # number of ReadCleanReq accesses(hits+misses) 35810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 87 # number of ReadSharedReq accesses(hits+misses) 35910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 87 # number of ReadSharedReq accesses(hits+misses) 36010726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 295 # number of demand (read+write) accesses 36110726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 137 # number of demand (read+write) accesses 36210726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 432 # number of demand (read+write) accesses 36310726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 295 # number of overall (read+write) accesses 36410726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 137 # number of overall (read+write) accesses 36510726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 432 # number of overall (read+write) accesses 36610726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 36710726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 36810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.993220 # miss rate for ReadCleanReq accesses 36910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993220 # miss rate for ReadCleanReq accesses 37010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 37110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 37210726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.993220 # miss rate for demand accesses 37310726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 37410726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.995370 # miss rate for demand accesses 37510726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.993220 # miss rate for overall accesses 37610726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 37710726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.995370 # miss rate for overall accesses 37811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency 37911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency 38011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.706485 # average ReadCleanReq miss latency 38111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.706485 # average ReadCleanReq miss latency 38211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency 38311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency 38411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.706485 # average overall miss latency 38511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency 38611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 60501.162791 # average overall miss latency 38711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.706485 # average overall miss latency 38811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency 38911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 60501.162791 # average overall miss latency 39010726Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 39110726Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 39210726Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 39310726Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 39410726Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 39510726Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 39610726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses 39710726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses 39810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 293 # number of ReadCleanReq MSHR misses 39910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 293 # number of ReadCleanReq MSHR misses 40010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 87 # number of ReadSharedReq MSHR misses 40110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 87 # number of ReadSharedReq MSHR misses 40210726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses 40310726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses 40410726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses 40510726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses 40610726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses 40710726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses 40811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2525000 # number of ReadExReq MSHR miss cycles 40911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2525000 # number of ReadExReq MSHR miss cycles 41011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14797000 # number of ReadCleanReq MSHR miss cycles 41111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14797000 # number of ReadCleanReq MSHR miss cycles 41211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4393500 # number of ReadSharedReq MSHR miss cycles 41311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4393500 # number of ReadSharedReq MSHR miss cycles 41411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14797000 # number of demand (read+write) MSHR miss cycles 41511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6918500 # number of demand (read+write) MSHR miss cycles 41611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 21715500 # number of demand (read+write) MSHR miss cycles 41711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14797000 # number of overall MSHR miss cycles 41811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6918500 # number of overall MSHR miss cycles 41911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 21715500 # number of overall MSHR miss cycles 42010726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 42110726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 42210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for ReadCleanReq accesses 42310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993220 # mshr miss rate for ReadCleanReq accesses 42410892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 42510892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 42610726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for demand accesses 42710726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 42810726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.995370 # mshr miss rate for demand accesses 42910726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for overall accesses 43010726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 43110726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.995370 # mshr miss rate for overall accesses 43211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency 43311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency 43411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.706485 # average ReadCleanReq mshr miss latency 43511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.706485 # average ReadCleanReq mshr miss latency 43611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency 43711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency 43811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.706485 # average overall mshr miss latency 43911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency 44011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.162791 # average overall mshr miss latency 44111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.706485 # average overall mshr miss latency 44211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency 44311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.162791 # average overall mshr miss latency 44411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter. 44511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 13 # Number of requests hitting in the snoop filter with a single holder of the requested data. 44611138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 44711138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 44811138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 44911138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 45011606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states 45110488Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution 45211201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 13 # Transaction distribution 45310488Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution 45410488Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution 45510892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 295 # Transaction distribution 45610892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 87 # Transaction distribution 45710892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 603 # Packet count per connected master and slave (bytes) 45810488Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes) 45910892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 877 # Packet count per connected master and slave (bytes) 46011201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19712 # Cumulative packet size per connected master and slave (bytes) 46110488Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8768 # Cumulative packet size per connected master and slave (bytes) 46211201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 28480 # Cumulative packet size per connected master and slave (bytes) 46310409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 0 # Total snoops (count) 46411570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) 46511201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 432 # Request fanout histogram 46611138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram 46710409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 46810409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 46911201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 432 100.00% 100.00% # Request fanout histogram 47011138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 47110409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 47210409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 47311138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 47411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram 47511201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 432 # Request fanout histogram 47611201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 235500 # Layer occupancy (ticks) 4779729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 47810488Snilay@cs.wisc.edusystem.cpu.toL2Bus.respLayer0.occupancy 442500 # Layer occupancy (ticks) 47911201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) 48010488Snilay@cs.wisc.edusystem.cpu.toL2Bus.respLayer1.occupancy 205500 # Layer occupancy (ticks) 48111201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) 48211606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_requests 430 # Total number of requests made to the snoop filter. 48311606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 48411606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 48511606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 48611606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 48711606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 48811606Sandreas.sandberg@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states 48910726Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 380 # Transaction distribution 49010726Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 50 # Transaction distribution 49110726Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 50 # Transaction distribution 49210892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 380 # Transaction distribution 49310726Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 860 # Packet count per connected master and slave (bytes) 49410726Sandreas.hansson@arm.comsystem.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes) 49510726Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27520 # Cumulative packet size per connected master and slave (bytes) 49610726Sandreas.hansson@arm.comsystem.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes) 49710726Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 49811570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 49910726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 430 # Request fanout histogram 50010726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 50110726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 50210726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 50310726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 430 100.00% 100.00% # Request fanout histogram 50410726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 50510726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 50610726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 50710726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 50810726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 430 # Request fanout histogram 50910726Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 430500 # Layer occupancy (ticks) 51011201Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 1.3 # Layer utilization (%) 51111201Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 2150000 # Layer occupancy (ticks) 51211201Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 6.3 # Layer utilization (%) 5133021SN/A 5143021SN/A---------- End Simulation Statistics ---------- 515