stats.txt revision 11507
13021SN/A 23021SN/A---------- Begin Simulation Statistics ---------- 311201Sandreas.hansson@arm.comsim_seconds 0.000034 # Number of seconds simulated 411390Ssteve.reinhardt@amd.comsim_ticks 33932500 # Number of ticks simulated 511390Ssteve.reinhardt@amd.comfinal_tick 33932500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68540SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711502SCurtis.Dunham@arm.comhost_inst_rate 431758 # Simulator instruction rate (inst/s) 811502SCurtis.Dunham@arm.comhost_op_rate 430982 # Simulator op (including micro ops) rate (op/s) 911502SCurtis.Dunham@arm.comhost_tick_rate 2588300068 # Simulator tick rate (ticks/s) 1011502SCurtis.Dunham@arm.comhost_mem_usage 244424 # Number of bytes of host memory used 1111456Sandreas.hansson@arm.comhost_seconds 0.01 # Real time elapsed on the host 1211390Ssteve.reinhardt@amd.comsim_insts 5641 # Number of instructions simulated 1311390Ssteve.reinhardt@amd.comsim_ops 5641 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610488Snilay@cs.wisc.edusystem.physmem.bytes_read::cpu.inst 18752 # Number of bytes read from this memory 1710488Snilay@cs.wisc.edusystem.physmem.bytes_read::cpu.data 8768 # Number of bytes read from this memory 1810488Snilay@cs.wisc.edusystem.physmem.bytes_read::total 27520 # Number of bytes read from this memory 1910488Snilay@cs.wisc.edusystem.physmem.bytes_inst_read::cpu.inst 18752 # Number of instructions bytes read from this memory 2010488Snilay@cs.wisc.edusystem.physmem.bytes_inst_read::total 18752 # Number of instructions bytes read from this memory 2110488Snilay@cs.wisc.edusystem.physmem.num_reads::cpu.inst 293 # Number of read requests responded to by this memory 2210488Snilay@cs.wisc.edusystem.physmem.num_reads::cpu.data 137 # Number of read requests responded to by this memory 2310488Snilay@cs.wisc.edusystem.physmem.num_reads::total 430 # Number of read requests responded to by this memory 2411390Ssteve.reinhardt@amd.comsystem.physmem.bw_read::cpu.inst 552626538 # Total read bandwidth from this memory (bytes/s) 2511390Ssteve.reinhardt@amd.comsystem.physmem.bw_read::cpu.data 258395344 # Total read bandwidth from this memory (bytes/s) 2611390Ssteve.reinhardt@amd.comsystem.physmem.bw_read::total 811021882 # Total read bandwidth from this memory (bytes/s) 2711390Ssteve.reinhardt@amd.comsystem.physmem.bw_inst_read::cpu.inst 552626538 # Instruction read bandwidth from this memory (bytes/s) 2811390Ssteve.reinhardt@amd.comsystem.physmem.bw_inst_read::total 552626538 # Instruction read bandwidth from this memory (bytes/s) 2911390Ssteve.reinhardt@amd.comsystem.physmem.bw_total::cpu.inst 552626538 # Total bandwidth to/from this memory (bytes/s) 3011390Ssteve.reinhardt@amd.comsystem.physmem.bw_total::cpu.data 258395344 # Total bandwidth to/from this memory (bytes/s) 3111390Ssteve.reinhardt@amd.comsystem.physmem.bw_total::total 811021882 # Total bandwidth to/from this memory (bytes/s) 3210036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 338540SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 348540SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 358540SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 368540SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 378540SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 388540SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 398540SN/Asystem.cpu.dtb.hits 0 # DTB hits 408540SN/Asystem.cpu.dtb.misses 0 # DTB misses 418540SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 428540SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 438540SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 448540SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 458540SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 468540SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 478540SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 488540SN/Asystem.cpu.itb.hits 0 # DTB hits 498540SN/Asystem.cpu.itb.misses 0 # DTB misses 508540SN/Asystem.cpu.itb.accesses 0 # DTB accesses 5110488Snilay@cs.wisc.edusystem.cpu.workload.num_syscalls 7 # Number of system calls 5211390Ssteve.reinhardt@amd.comsystem.cpu.numCycles 67865 # number of cpu cycles simulated 538540SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 548540SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 5511390Ssteve.reinhardt@amd.comsystem.cpu.committedInsts 5641 # Number of instructions committed 5611390Ssteve.reinhardt@amd.comsystem.cpu.committedOps 5641 # Number of ops (including micro ops) committed 5711390Ssteve.reinhardt@amd.comsystem.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses 588540SN/Asystem.cpu.num_fp_alu_accesses 2 # Number of float alu accesses 5911390Ssteve.reinhardt@amd.comsystem.cpu.num_func_calls 191 # number of times a function call or return occured 6011390Ssteve.reinhardt@amd.comsystem.cpu.num_conditional_control_insts 651 # number of instructions that are conditional controls 6111390Ssteve.reinhardt@amd.comsystem.cpu.num_int_insts 4957 # number of integer instructions 628540SN/Asystem.cpu.num_fp_insts 2 # number of float instructions 6311390Ssteve.reinhardt@amd.comsystem.cpu.num_int_register_reads 7072 # number of times the integer registers were read 6411390Ssteve.reinhardt@amd.comsystem.cpu.num_int_register_writes 3291 # number of times the integer registers were written 658540SN/Asystem.cpu.num_fp_register_reads 3 # number of times the floating registers were read 668540SN/Asystem.cpu.num_fp_register_writes 1 # number of times the floating registers were written 6711390Ssteve.reinhardt@amd.comsystem.cpu.num_mem_refs 2037 # number of memory refs 6811390Ssteve.reinhardt@amd.comsystem.cpu.num_load_insts 1135 # Number of load instructions 6910488Snilay@cs.wisc.edusystem.cpu.num_store_insts 902 # Number of store instructions 708540SN/Asystem.cpu.num_idle_cycles 0 # Number of idle cycles 7111390Ssteve.reinhardt@amd.comsystem.cpu.num_busy_cycles 67865 # Number of busy cycles 728540SN/Asystem.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 738540SN/Asystem.cpu.idle_fraction 0 # Percentage of idle cycles 7411390Ssteve.reinhardt@amd.comsystem.cpu.Branches 886 # Number of branches fetched 7511390Ssteve.reinhardt@amd.comsystem.cpu.op_class::No_OpClass 641 11.36% 11.36% # Class of executed instruction 7611390Ssteve.reinhardt@amd.comsystem.cpu.op_class::IntAlu 2960 52.46% 63.82% # Class of executed instruction 7711390Ssteve.reinhardt@amd.comsystem.cpu.op_class::IntMult 2 0.04% 63.86% # Class of executed instruction 7811390Ssteve.reinhardt@amd.comsystem.cpu.op_class::IntDiv 0 0.00% 63.86% # Class of executed instruction 7911390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatAdd 2 0.04% 63.90% # Class of executed instruction 8011390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction 8111390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction 8211390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction 8311390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction 8411390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction 8511390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction 8611390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction 8711390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdAlu 0 0.00% 63.90% # Class of executed instruction 8811390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdCmp 0 0.00% 63.90% # Class of executed instruction 8911390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdCvt 0 0.00% 63.90% # Class of executed instruction 9011390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdMisc 0 0.00% 63.90% # Class of executed instruction 9111390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdMult 0 0.00% 63.90% # Class of executed instruction 9211390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdMultAcc 0 0.00% 63.90% # Class of executed instruction 9311390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdShift 0 0.00% 63.90% # Class of executed instruction 9411390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdShiftAcc 0 0.00% 63.90% # Class of executed instruction 9511390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdSqrt 0 0.00% 63.90% # Class of executed instruction 9611390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatAdd 0 0.00% 63.90% # Class of executed instruction 9711390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatAlu 0 0.00% 63.90% # Class of executed instruction 9811390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatCmp 0 0.00% 63.90% # Class of executed instruction 9911390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatCvt 0 0.00% 63.90% # Class of executed instruction 10011390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatDiv 0 0.00% 63.90% # Class of executed instruction 10111390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatMisc 0 0.00% 63.90% # Class of executed instruction 10211390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction 10311390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction 10411390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction 10511390Ssteve.reinhardt@amd.comsystem.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction 10611390Ssteve.reinhardt@amd.comsystem.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction 10710220Sandreas.hansson@arm.comsystem.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 10810220Sandreas.hansson@arm.comsystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 10911390Ssteve.reinhardt@amd.comsystem.cpu.op_class::total 5642 # Class of executed instruction 1109838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 11111390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.tagsinuse 86.030444 # Cycle average of tags in use 11211390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.total_refs 1899 # Total number of references to valid blocks. 11310488Snilay@cs.wisc.edusystem.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. 11411390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.avg_refs 13.861314 # Average number of references to valid blocks. 1159838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 11611390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 86.030444 # Average occupied blocks per requestor 11711390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.021004 # Average percentage of cache occupancy 11811390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.occ_percent::total 0.021004 # Average percentage of cache occupancy 11910488Snilay@cs.wisc.edusystem.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id 12011201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id 12111201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 115 # Occupied blocks per task id 12210488Snilay@cs.wisc.edusystem.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id 12311390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.tag_accesses 4209 # Number of tag accesses 12411390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.data_accesses 4209 # Number of data accesses 12511390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits 12611390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits 12710488Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits 12810488Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits 12911390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_hits::cpu.data 1899 # number of demand (read+write) hits 13011390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_hits::total 1899 # number of demand (read+write) hits 13111390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_hits::cpu.data 1899 # number of overall hits 13211390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_hits::total 1899 # number of overall hits 1339481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses 1349481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses 13510488Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses 13610488Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::total 50 # number of WriteReq misses 13710488Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::cpu.data 137 # number of demand (read+write) misses 13810488Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses 13910488Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses 14010488Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::total 137 # number of overall misses 14111201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 5394000 # number of ReadReq miss cycles 14211201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 5394000 # number of ReadReq miss cycles 14311201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 3100000 # number of WriteReq miss cycles 14411201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 3100000 # number of WriteReq miss cycles 14511201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 8494000 # number of demand (read+write) miss cycles 14611201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 8494000 # number of demand (read+write) miss cycles 14711201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 8494000 # number of overall miss cycles 14811201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 8494000 # number of overall miss cycles 14911390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1135 # number of ReadReq accesses(hits+misses) 15011390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_accesses::total 1135 # number of ReadReq accesses(hits+misses) 15110488Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) 15210488Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) 15311390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_accesses::cpu.data 2036 # number of demand (read+write) accesses 15411390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_accesses::total 2036 # number of demand (read+write) accesses 15511390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_accesses::cpu.data 2036 # number of overall (read+write) accesses 15611390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_accesses::total 2036 # number of overall (read+write) accesses 15711390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076652 # miss rate for ReadReq accesses 15811390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.076652 # miss rate for ReadReq accesses 15910488Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses 16010488Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses 16111390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.067289 # miss rate for demand accesses 16211390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_miss_rate::total 0.067289 # miss rate for demand accesses 16311390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.067289 # miss rate for overall accesses 16411390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_miss_rate::total 0.067289 # miss rate for overall accesses 16511201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency 16611201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency 16711201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency 16811201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency 16911201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency 17011201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency 17111201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency 17211201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency 1739481Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1749481Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1759481Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1769481Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1779481Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1789481Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1799481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses 1809481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses 18110488Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses 18210488Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses 18310488Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses 18410488Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses 18510488Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses 18610488Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses 18711201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5307000 # number of ReadReq MSHR miss cycles 18811201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 5307000 # number of ReadReq MSHR miss cycles 18911201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3050000 # number of WriteReq MSHR miss cycles 19011201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 3050000 # number of WriteReq MSHR miss cycles 19111201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 8357000 # number of demand (read+write) MSHR miss cycles 19211201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 8357000 # number of demand (read+write) MSHR miss cycles 19311201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 8357000 # number of overall MSHR miss cycles 19411201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 8357000 # number of overall MSHR miss cycles 19511390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076652 # mshr miss rate for ReadReq accesses 19611390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076652 # mshr miss rate for ReadReq accesses 19710488Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses 19810488Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses 19911390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for demand accesses 20011390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.067289 # mshr miss rate for demand accesses 20111390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for overall accesses 20211390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.067289 # mshr miss rate for overall accesses 20311201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency 20411201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency 20511201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency 20611201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency 20711201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 20811201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency 20911201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 21011201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency 21110726Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 13 # number of replacements 21211390Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.tagsinuse 128.953338 # Cycle average of tags in use 21311390Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.total_refs 5348 # Total number of references to valid blocks. 21410726Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. 21511390Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.avg_refs 18.128814 # Average number of references to valid blocks. 21610726Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 21711390Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 128.953338 # Average occupied blocks per requestor 21811390Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.062965 # Average percentage of cache occupancy 21911390Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.occ_percent::total 0.062965 # Average percentage of cache occupancy 22010726Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id 22111201Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id 22211201Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id 22310726Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.137695 # Percentage of cache occupancy per task id 22411390Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.tag_accesses 11581 # Number of tag accesses 22511390Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.data_accesses 11581 # Number of data accesses 22611390Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_hits::cpu.inst 5348 # number of ReadReq hits 22711390Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_hits::total 5348 # number of ReadReq hits 22811390Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_hits::cpu.inst 5348 # number of demand (read+write) hits 22911390Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_hits::total 5348 # number of demand (read+write) hits 23011390Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_hits::cpu.inst 5348 # number of overall hits 23111390Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_hits::total 5348 # number of overall hits 23210726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 295 # number of ReadReq misses 23310726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 295 # number of ReadReq misses 23410726Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 295 # number of demand (read+write) misses 23510726Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 295 # number of demand (read+write) misses 23610726Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 295 # number of overall misses 23710726Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 295 # number of overall misses 23811201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 18192500 # number of ReadReq miss cycles 23911201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 18192500 # number of ReadReq miss cycles 24011201Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 18192500 # number of demand (read+write) miss cycles 24111201Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 18192500 # number of demand (read+write) miss cycles 24211201Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 18192500 # number of overall miss cycles 24311201Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 18192500 # number of overall miss cycles 24411390Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 5643 # number of ReadReq accesses(hits+misses) 24511390Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_accesses::total 5643 # number of ReadReq accesses(hits+misses) 24611390Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_accesses::cpu.inst 5643 # number of demand (read+write) accesses 24711390Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_accesses::total 5643 # number of demand (read+write) accesses 24811390Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_accesses::cpu.inst 5643 # number of overall (read+write) accesses 24911390Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_accesses::total 5643 # number of overall (read+write) accesses 25011390Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052277 # miss rate for ReadReq accesses 25111390Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_miss_rate::total 0.052277 # miss rate for ReadReq accesses 25211390Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.052277 # miss rate for demand accesses 25311390Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_miss_rate::total 0.052277 # miss rate for demand accesses 25411390Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.052277 # miss rate for overall accesses 25511390Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_miss_rate::total 0.052277 # miss rate for overall accesses 25611201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61669.491525 # average ReadReq miss latency 25711201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 61669.491525 # average ReadReq miss latency 25811201Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 61669.491525 # average overall miss latency 25911201Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 61669.491525 # average overall miss latency 26011201Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 61669.491525 # average overall miss latency 26111201Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 61669.491525 # average overall miss latency 26210726Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 26310726Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 26410726Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 26510726Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 26610726Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 26710726Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 26811201Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::writebacks 13 # number of writebacks 26911201Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::total 13 # number of writebacks 27010726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 295 # number of ReadReq MSHR misses 27110726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 295 # number of ReadReq MSHR misses 27210726Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 295 # number of demand (read+write) MSHR misses 27310726Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 295 # number of demand (read+write) MSHR misses 27410726Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 295 # number of overall MSHR misses 27510726Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 295 # number of overall MSHR misses 27611201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17897500 # number of ReadReq MSHR miss cycles 27711201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 17897500 # number of ReadReq MSHR miss cycles 27811201Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 17897500 # number of demand (read+write) MSHR miss cycles 27911201Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 17897500 # number of demand (read+write) MSHR miss cycles 28011201Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 17897500 # number of overall MSHR miss cycles 28111201Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 17897500 # number of overall MSHR miss cycles 28211390Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for ReadReq accesses 28311390Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.052277 # mshr miss rate for ReadReq accesses 28411390Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for demand accesses 28511390Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.052277 # mshr miss rate for demand accesses 28611390Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for overall accesses 28711390Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.052277 # mshr miss rate for overall accesses 28811201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60669.491525 # average ReadReq mshr miss latency 28911201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60669.491525 # average ReadReq mshr miss latency 29011201Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency 29111201Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency 29211201Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency 29311201Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency 29410726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 29511390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.tagsinuse 183.490494 # Cycle average of tags in use 29610892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks. 29710726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks. 29810892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 0.039474 # Average number of references to valid blocks. 29910726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 30011390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 130.087016 # Average occupied blocks per requestor 30111390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 53.403478 # Average occupied blocks per requestor 30211390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.003970 # Average percentage of cache occupancy 30311201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.001630 # Average percentage of cache occupancy 30411390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.occ_percent::total 0.005600 # Average percentage of cache occupancy 30510726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id 30611201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id 30711201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id 30810726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.011597 # Percentage of cache occupancy per task id 30910892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 3990 # Number of tag accesses 31010892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 3990 # Number of data accesses 31111201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 13 # number of WritebackClean hits 31211201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 13 # number of WritebackClean hits 31310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits 31410892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits 31510726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 31610726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 31710726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 31810726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 2 # number of overall hits 31910726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 50 # number of ReadExReq misses 32010726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 50 # number of ReadExReq misses 32110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 293 # number of ReadCleanReq misses 32210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 293 # number of ReadCleanReq misses 32310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 87 # number of ReadSharedReq misses 32410892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 87 # number of ReadSharedReq misses 32510726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 293 # number of demand (read+write) misses 32610726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 137 # number of demand (read+write) misses 32710726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 430 # number of demand (read+write) misses 32810726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 293 # number of overall misses 32910726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 137 # number of overall misses 33010726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 430 # number of overall misses 33111201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2975000 # number of ReadExReq miss cycles 33211201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 2975000 # number of ReadExReq miss cycles 33311201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 17434000 # number of ReadCleanReq miss cycles 33411201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 17434000 # number of ReadCleanReq miss cycles 33511201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5176500 # number of ReadSharedReq miss cycles 33611201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 5176500 # number of ReadSharedReq miss cycles 33711201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 17434000 # number of demand (read+write) miss cycles 33811201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 8151500 # number of demand (read+write) miss cycles 33911201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 25585500 # number of demand (read+write) miss cycles 34011201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 17434000 # number of overall miss cycles 34111201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 8151500 # number of overall miss cycles 34211201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 25585500 # number of overall miss cycles 34311201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 13 # number of WritebackClean accesses(hits+misses) 34411201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 13 # number of WritebackClean accesses(hits+misses) 34510726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) 34610726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) 34710892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 295 # number of ReadCleanReq accesses(hits+misses) 34810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 295 # number of ReadCleanReq accesses(hits+misses) 34910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 87 # number of ReadSharedReq accesses(hits+misses) 35010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 87 # number of ReadSharedReq accesses(hits+misses) 35110726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 295 # number of demand (read+write) accesses 35210726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 137 # number of demand (read+write) accesses 35310726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 432 # number of demand (read+write) accesses 35410726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 295 # number of overall (read+write) accesses 35510726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 137 # number of overall (read+write) accesses 35610726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 432 # number of overall (read+write) accesses 35710726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 35810726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 35910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.993220 # miss rate for ReadCleanReq accesses 36010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993220 # miss rate for ReadCleanReq accesses 36110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 36210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 36310726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.993220 # miss rate for demand accesses 36410726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 36510726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.995370 # miss rate for demand accesses 36610726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.993220 # miss rate for overall accesses 36710726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 36810726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.995370 # miss rate for overall accesses 36911201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency 37011201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency 37111201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.706485 # average ReadCleanReq miss latency 37211201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.706485 # average ReadCleanReq miss latency 37311201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency 37411201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency 37511201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.706485 # average overall miss latency 37611201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency 37711201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 59501.162791 # average overall miss latency 37811201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.706485 # average overall miss latency 37911201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency 38011201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 59501.162791 # average overall miss latency 38110726Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 38210726Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 38310726Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 38410726Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 38510726Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 38610726Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 38710726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses 38810726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses 38910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 293 # number of ReadCleanReq MSHR misses 39010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 293 # number of ReadCleanReq MSHR misses 39110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 87 # number of ReadSharedReq MSHR misses 39210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 87 # number of ReadSharedReq MSHR misses 39310726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses 39410726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses 39510726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses 39610726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses 39710726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses 39810726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses 39911201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2475000 # number of ReadExReq MSHR miss cycles 40011201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2475000 # number of ReadExReq MSHR miss cycles 40111201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14504000 # number of ReadCleanReq MSHR miss cycles 40211201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14504000 # number of ReadCleanReq MSHR miss cycles 40311201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4306500 # number of ReadSharedReq MSHR miss cycles 40411201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4306500 # number of ReadSharedReq MSHR miss cycles 40511201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14504000 # number of demand (read+write) MSHR miss cycles 40611201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6781500 # number of demand (read+write) MSHR miss cycles 40711201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 21285500 # number of demand (read+write) MSHR miss cycles 40811201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14504000 # number of overall MSHR miss cycles 40911201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6781500 # number of overall MSHR miss cycles 41011201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 21285500 # number of overall MSHR miss cycles 41110726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 41210726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 41310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for ReadCleanReq accesses 41410892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993220 # mshr miss rate for ReadCleanReq accesses 41510892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 41610892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 41710726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for demand accesses 41810726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 41910726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.995370 # mshr miss rate for demand accesses 42010726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for overall accesses 42110726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 42210726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.995370 # mshr miss rate for overall accesses 42311201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency 42411201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency 42511201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.706485 # average ReadCleanReq mshr miss latency 42611201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.706485 # average ReadCleanReq mshr miss latency 42711201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency 42811201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency 42911201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.706485 # average overall mshr miss latency 43011201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 43111201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.162791 # average overall mshr miss latency 43211201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.706485 # average overall mshr miss latency 43311201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 43411201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.162791 # average overall mshr miss latency 43511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter. 43611138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 13 # Number of requests hitting in the snoop filter with a single holder of the requested data. 43711138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 43811138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 43911138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 44011138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 44110488Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution 44211201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 13 # Transaction distribution 44310488Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution 44410488Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution 44510892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 295 # Transaction distribution 44610892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 87 # Transaction distribution 44710892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 603 # Packet count per connected master and slave (bytes) 44810488Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes) 44910892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 877 # Packet count per connected master and slave (bytes) 45011201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19712 # Cumulative packet size per connected master and slave (bytes) 45110488Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8768 # Cumulative packet size per connected master and slave (bytes) 45211201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 28480 # Cumulative packet size per connected master and slave (bytes) 45310409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 0 # Total snoops (count) 45411201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 432 # Request fanout histogram 45511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram 45610409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 45710409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 45811201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 432 100.00% 100.00% # Request fanout histogram 45911138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 46010409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 46110409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 46211138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 46311138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram 46411201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 432 # Request fanout histogram 46511201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 235500 # Layer occupancy (ticks) 4669729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 46710488Snilay@cs.wisc.edusystem.cpu.toL2Bus.respLayer0.occupancy 442500 # Layer occupancy (ticks) 46811201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) 46910488Snilay@cs.wisc.edusystem.cpu.toL2Bus.respLayer1.occupancy 205500 # Layer occupancy (ticks) 47011201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) 47110726Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 380 # Transaction distribution 47210726Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 50 # Transaction distribution 47310726Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 50 # Transaction distribution 47410892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 380 # Transaction distribution 47510726Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 860 # Packet count per connected master and slave (bytes) 47610726Sandreas.hansson@arm.comsystem.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes) 47710726Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27520 # Cumulative packet size per connected master and slave (bytes) 47810726Sandreas.hansson@arm.comsystem.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes) 47910726Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 48010726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 430 # Request fanout histogram 48110726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 48210726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 48310726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 48410726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 430 100.00% 100.00% # Request fanout histogram 48510726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 48610726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 48710726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 48810726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 48910726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 430 # Request fanout histogram 49010726Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 430500 # Layer occupancy (ticks) 49111201Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 1.3 # Layer utilization (%) 49211201Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 2150000 # Layer occupancy (ticks) 49311201Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 6.3 # Layer utilization (%) 4943021SN/A 4953021SN/A---------- End Simulation Statistics ---------- 496