stats.txt revision 10036
13021SN/A 23021SN/A---------- Begin Simulation Statistics ---------- 39285Sandreas.hansson@arm.comsim_seconds 0.000032 # Number of seconds simulated 49285Sandreas.hansson@arm.comsim_ticks 31633000 # Number of ticks simulated 59285Sandreas.hansson@arm.comfinal_tick 31633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68540SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710036SAli.Saidi@ARM.comhost_inst_rate 65946 # Simulator instruction rate (inst/s) 810036SAli.Saidi@ARM.comhost_op_rate 65935 # Simulator op (including micro ops) rate (op/s) 910036SAli.Saidi@ARM.comhost_tick_rate 358688094 # Simulator tick rate (ticks/s) 1010036SAli.Saidi@ARM.comhost_mem_usage 230484 # Number of bytes of host memory used 1110036SAli.Saidi@ARM.comhost_seconds 0.09 # Real time elapsed on the host 129150SAli.Saidi@ARM.comsim_insts 5814 # Number of instructions simulated 139150SAli.Saidi@ARM.comsim_ops 5814 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 169055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory 179055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory 189055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::total 28096 # Number of bytes read from this memory 199055Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::cpu.inst 19264 # Number of instructions bytes read from this memory 209055Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::total 19264 # Number of instructions bytes read from this memory 219055Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory 229055Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory 239055Ssaidi@eecs.umich.edusystem.physmem.num_reads::total 439 # Number of read requests responded to by this memory 249285Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 608984289 # Total read bandwidth from this memory (bytes/s) 259285Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 279202099 # Total read bandwidth from this memory (bytes/s) 269285Sandreas.hansson@arm.comsystem.physmem.bw_read::total 888186388 # Total read bandwidth from this memory (bytes/s) 279285Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 608984289 # Instruction read bandwidth from this memory (bytes/s) 289285Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 608984289 # Instruction read bandwidth from this memory (bytes/s) 299285Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 608984289 # Total bandwidth to/from this memory (bytes/s) 309285Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 279202099 # Total bandwidth to/from this memory (bytes/s) 319285Sandreas.hansson@arm.comsystem.physmem.bw_total::total 888186388 # Total bandwidth to/from this memory (bytes/s) 329729Sandreas.hansson@arm.comsystem.membus.throughput 888186388 # Throughput (bytes/s) 339729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 388 # Transaction distribution 349729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 388 # Transaction distribution 359729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 51 # Transaction distribution 369729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 51 # Transaction distribution 379838Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878 # Packet count per connected master and slave (bytes) 389838Sandreas.hansson@arm.comsystem.membus.pkt_count::total 878 # Packet count per connected master and slave (bytes) 399838Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28096 # Cumulative packet size per connected master and slave (bytes) 409838Sandreas.hansson@arm.comsystem.membus.tot_pkt_size::total 28096 # Cumulative packet size per connected master and slave (bytes) 419729Sandreas.hansson@arm.comsystem.membus.data_through_bus 28096 # Total data (bytes) 429729Sandreas.hansson@arm.comsystem.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 439729Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 439000 # Layer occupancy (ticks) 449729Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 1.4 # Layer utilization (%) 459729Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 3951000 # Layer occupancy (ticks) 469729Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 12.5 # Layer utilization (%) 4710036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 488540SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 498540SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 508540SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 518540SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 528540SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 538540SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 548540SN/Asystem.cpu.dtb.hits 0 # DTB hits 558540SN/Asystem.cpu.dtb.misses 0 # DTB misses 568540SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 578540SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 588540SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 598540SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 608540SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 618540SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 628540SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 638540SN/Asystem.cpu.itb.hits 0 # DTB hits 648540SN/Asystem.cpu.itb.misses 0 # DTB misses 658540SN/Asystem.cpu.itb.accesses 0 # DTB accesses 668540SN/Asystem.cpu.workload.num_syscalls 8 # Number of system calls 679285Sandreas.hansson@arm.comsystem.cpu.numCycles 63266 # number of cpu cycles simulated 688540SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 698540SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 709150SAli.Saidi@ARM.comsystem.cpu.committedInsts 5814 # Number of instructions committed 719150SAli.Saidi@ARM.comsystem.cpu.committedOps 5814 # Number of ops (including micro ops) committed 729150SAli.Saidi@ARM.comsystem.cpu.num_int_alu_accesses 5113 # Number of integer alu accesses 738540SN/Asystem.cpu.num_fp_alu_accesses 2 # Number of float alu accesses 748540SN/Asystem.cpu.num_func_calls 194 # number of times a function call or return occured 759150SAli.Saidi@ARM.comsystem.cpu.num_conditional_control_insts 676 # number of instructions that are conditional controls 769150SAli.Saidi@ARM.comsystem.cpu.num_int_insts 5113 # number of integer instructions 778540SN/Asystem.cpu.num_fp_insts 2 # number of float instructions 789150SAli.Saidi@ARM.comsystem.cpu.num_int_register_reads 7284 # number of times the integer registers were read 799150SAli.Saidi@ARM.comsystem.cpu.num_int_register_writes 3397 # number of times the integer registers were written 808540SN/Asystem.cpu.num_fp_register_reads 3 # number of times the floating registers were read 818540SN/Asystem.cpu.num_fp_register_writes 1 # number of times the floating registers were written 829150SAli.Saidi@ARM.comsystem.cpu.num_mem_refs 2089 # number of memory refs 839150SAli.Saidi@ARM.comsystem.cpu.num_load_insts 1163 # Number of load instructions 848540SN/Asystem.cpu.num_store_insts 926 # Number of store instructions 858540SN/Asystem.cpu.num_idle_cycles 0 # Number of idle cycles 869285Sandreas.hansson@arm.comsystem.cpu.num_busy_cycles 63266 # Number of busy cycles 878540SN/Asystem.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 888540SN/Asystem.cpu.idle_fraction 0 # Percentage of idle cycles 899838Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 13 # number of replacements 909838Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 132.545353 # Cycle average of tags in use 919838Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 5513 # Total number of references to valid blocks. 929838Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 303 # Sample count of references to valid blocks. 939838Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 18.194719 # Average number of references to valid blocks. 949838Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 959838Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 132.545353 # Average occupied blocks per requestor 969838Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.064719 # Average percentage of cache occupancy 979838Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.064719 # Average percentage of cache occupancy 9810036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 290 # Occupied blocks per task id 9910036SAli.Saidi@ARM.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id 10010036SAli.Saidi@ARM.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id 10110036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.141602 # Percentage of cache occupancy per task id 10210036SAli.Saidi@ARM.comsystem.cpu.icache.tags.tag_accesses 11935 # Number of tag accesses 10310036SAli.Saidi@ARM.comsystem.cpu.icache.tags.data_accesses 11935 # Number of data accesses 1049150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::cpu.inst 5513 # number of ReadReq hits 1059150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::total 5513 # number of ReadReq hits 1069150SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::cpu.inst 5513 # number of demand (read+write) hits 1079150SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::total 5513 # number of demand (read+write) hits 1089150SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::cpu.inst 5513 # number of overall hits 1099150SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::total 5513 # number of overall hits 1108835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::cpu.inst 303 # number of ReadReq misses 1118835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::total 303 # number of ReadReq misses 1128835SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::cpu.inst 303 # number of demand (read+write) misses 1138835SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::total 303 # number of demand (read+write) misses 1148835SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::cpu.inst 303 # number of overall misses 1158835SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::total 303 # number of overall misses 1169285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 16581000 # number of ReadReq miss cycles 1179285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 16581000 # number of ReadReq miss cycles 1189285Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 16581000 # number of demand (read+write) miss cycles 1199285Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 16581000 # number of demand (read+write) miss cycles 1209285Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 16581000 # number of overall miss cycles 1219285Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 16581000 # number of overall miss cycles 1229150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 5816 # number of ReadReq accesses(hits+misses) 1239150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::total 5816 # number of ReadReq accesses(hits+misses) 1249150SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::cpu.inst 5816 # number of demand (read+write) accesses 1259150SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::total 5816 # number of demand (read+write) accesses 1269150SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::cpu.inst 5816 # number of overall (read+write) accesses 1279150SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::total 5816 # number of overall (read+write) accesses 1289150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052098 # miss rate for ReadReq accesses 1299150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::total 0.052098 # miss rate for ReadReq accesses 1309150SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.052098 # miss rate for demand accesses 1319150SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::total 0.052098 # miss rate for demand accesses 1329150SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.052098 # miss rate for overall accesses 1339150SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::total 0.052098 # miss rate for overall accesses 1349285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54722.772277 # average ReadReq miss latency 1359285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 54722.772277 # average ReadReq miss latency 1369285Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 54722.772277 # average overall miss latency 1379285Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 54722.772277 # average overall miss latency 1389285Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 54722.772277 # average overall miss latency 1399285Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 54722.772277 # average overall miss latency 1408540SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1418540SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1428540SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1438540SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 1448983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1458983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1468540SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 1478540SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 1488835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 303 # number of ReadReq MSHR misses 1498835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::total 303 # number of ReadReq MSHR misses 1508835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 303 # number of demand (read+write) MSHR misses 1518835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::total 303 # number of demand (read+write) MSHR misses 1528835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 303 # number of overall MSHR misses 1538835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::total 303 # number of overall MSHR misses 1548835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15975000 # number of ReadReq MSHR miss cycles 1558835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 15975000 # number of ReadReq MSHR miss cycles 1568835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 15975000 # number of demand (read+write) MSHR miss cycles 1578835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::total 15975000 # number of demand (read+write) MSHR miss cycles 1588835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 15975000 # number of overall MSHR miss cycles 1598835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::total 15975000 # number of overall MSHR miss cycles 1609150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052098 # mshr miss rate for ReadReq accesses 1619150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.052098 # mshr miss rate for ReadReq accesses 1629150SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052098 # mshr miss rate for demand accesses 1639150SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.052098 # mshr miss rate for demand accesses 1649150SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052098 # mshr miss rate for overall accesses 1659150SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.052098 # mshr miss rate for overall accesses 1668835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52722.772277 # average ReadReq mshr miss latency 1679055Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52722.772277 # average ReadReq mshr miss latency 1688835SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency 1699055Ssaidi@eecs.umich.edusystem.cpu.icache.demand_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency 1708835SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency 1719055Ssaidi@eecs.umich.edusystem.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency 1728540SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1739838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 1749838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 188.114191 # Cycle average of tags in use 1759838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 1769838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 388 # Sample count of references to valid blocks. 1779838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 0.005155 # Average number of references to valid blocks. 1789838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1799838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 133.890657 # Average occupied blocks per requestor 1809838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 54.223533 # Average occupied blocks per requestor 1819797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.004086 # Average percentage of cache occupancy 1829797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.001655 # Average percentage of cache occupancy 1839838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.005741 # Average percentage of cache occupancy 18410036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 388 # Occupied blocks per task id 18510036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id 18610036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id 18710036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.011841 # Percentage of cache occupancy per task id 18810036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.tag_accesses 3967 # Number of tag accesses 18910036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.data_accesses 3967 # Number of data accesses 1908835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits 1918835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits 1928835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 1938835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 1948835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 1958835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 2 # number of overall hits 1968835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 301 # number of ReadReq misses 1978835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses 1988835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::total 388 # number of ReadReq misses 1998835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses 2008835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses 2018835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.inst 301 # number of demand (read+write) misses 2028835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses 2038835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::total 439 # number of demand (read+write) misses 2048835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses 2058835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses 2068835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::total 439 # number of overall misses 2078835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15652000 # number of ReadReq miss cycles 2088835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 4524000 # number of ReadReq miss cycles 2098835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::total 20176000 # number of ReadReq miss cycles 2108835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2652000 # number of ReadExReq miss cycles 2118835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 2652000 # number of ReadExReq miss cycles 2128835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 15652000 # number of demand (read+write) miss cycles 2138835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 7176000 # number of demand (read+write) miss cycles 2148835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::total 22828000 # number of demand (read+write) miss cycles 2158835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 15652000 # number of overall miss cycles 2168835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 7176000 # number of overall miss cycles 2178835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::total 22828000 # number of overall miss cycles 2188835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 303 # number of ReadReq accesses(hits+misses) 2198835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) 2208835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::total 390 # number of ReadReq accesses(hits+misses) 2218835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) 2228835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) 2238835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.inst 303 # number of demand (read+write) accesses 2248835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses 2258835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses 2268835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.inst 303 # number of overall (read+write) accesses 2278835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses 2288835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses 2298835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993399 # miss rate for ReadReq accesses 2308835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 2319055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_miss_rate::total 0.994872 # miss rate for ReadReq accesses 2328835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 2339055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 2348835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.993399 # miss rate for demand accesses 2358835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 2369055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_miss_rate::total 0.995465 # miss rate for demand accesses 2378835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.993399 # miss rate for overall accesses 2388835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 2399055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_miss_rate::total 0.995465 # miss rate for overall accesses 2408835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 2418835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 2429055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 2438835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 2449055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 2458835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 2468835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 2479055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 2488835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 2498835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 2509055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency 2518540SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2528540SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2538540SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2548540SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2558983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2568983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2578540SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 2583041SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 2598835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses 2608835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses 2618835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 388 # number of ReadReq MSHR misses 2628835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses 2638835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses 2648835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses 2658835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses 2668835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::total 439 # number of demand (read+write) MSHR misses 2678835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses 2688835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses 2698835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::total 439 # number of overall MSHR misses 2708835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12040000 # number of ReadReq MSHR miss cycles 2718835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3480000 # number of ReadReq MSHR miss cycles 2728835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 15520000 # number of ReadReq MSHR miss cycles 2738835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2040000 # number of ReadExReq MSHR miss cycles 2748835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2040000 # number of ReadExReq MSHR miss cycles 2758835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12040000 # number of demand (read+write) MSHR miss cycles 2768835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5520000 # number of demand (read+write) MSHR miss cycles 2778835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 17560000 # number of demand (read+write) MSHR miss cycles 2788835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12040000 # number of overall MSHR miss cycles 2798835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 # number of overall MSHR miss cycles 2808835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 17560000 # number of overall MSHR miss cycles 2818835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for ReadReq accesses 2828835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 2839055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994872 # mshr miss rate for ReadReq accesses 2848835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 2859055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 2868835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for demand accesses 2878835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 2889055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_mshr_miss_rate::total 0.995465 # mshr miss rate for demand accesses 2898835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for overall accesses 2908835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 2919055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_mshr_miss_rate::total 0.995465 # mshr miss rate for overall accesses 2928835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 2938835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 2949055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 2958835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 2969055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 2978835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 2988835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 2999055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 3008835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 3018835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 3029055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 3038540SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 3049838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 3059838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 87.492114 # Cycle average of tags in use 3069838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 1950 # Total number of references to valid blocks. 3079838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. 3089838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 14.130435 # Average number of references to valid blocks. 3099838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 3109838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 87.492114 # Average occupied blocks per requestor 3119838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.021360 # Average percentage of cache occupancy 3129838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.021360 # Average percentage of cache occupancy 31310036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id 31410036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id 31510036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 114 # Occupied blocks per task id 31610036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id 31710036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.tag_accesses 4314 # Number of tag accesses 31810036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.data_accesses 4314 # Number of data accesses 3199481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_hits::cpu.data 1076 # number of ReadReq hits 3209481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_hits::total 1076 # number of ReadReq hits 3219481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::cpu.data 874 # number of WriteReq hits 3229481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::total 874 # number of WriteReq hits 3239481Snilay@cs.wisc.edusystem.cpu.dcache.demand_hits::cpu.data 1950 # number of demand (read+write) hits 3249481Snilay@cs.wisc.edusystem.cpu.dcache.demand_hits::total 1950 # number of demand (read+write) hits 3259481Snilay@cs.wisc.edusystem.cpu.dcache.overall_hits::cpu.data 1950 # number of overall hits 3269481Snilay@cs.wisc.edusystem.cpu.dcache.overall_hits::total 1950 # number of overall hits 3279481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses 3289481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses 3299481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::cpu.data 51 # number of WriteReq misses 3309481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::total 51 # number of WriteReq misses 3319481Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses 3329481Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses 3339481Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses 3349481Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::total 138 # number of overall misses 3359481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_latency::cpu.data 4785000 # number of ReadReq miss cycles 3369481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_latency::total 4785000 # number of ReadReq miss cycles 3379481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_latency::cpu.data 2805000 # number of WriteReq miss cycles 3389481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_latency::total 2805000 # number of WriteReq miss cycles 3399481Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles 3409481Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles 3419481Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles 3429481Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles 3439481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) 3449481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) 3459481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 3469481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 3479481Snilay@cs.wisc.edusystem.cpu.dcache.demand_accesses::cpu.data 2088 # number of demand (read+write) accesses 3489481Snilay@cs.wisc.edusystem.cpu.dcache.demand_accesses::total 2088 # number of demand (read+write) accesses 3499481Snilay@cs.wisc.edusystem.cpu.dcache.overall_accesses::cpu.data 2088 # number of overall (read+write) accesses 3509481Snilay@cs.wisc.edusystem.cpu.dcache.overall_accesses::total 2088 # number of overall (read+write) accesses 3519481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074807 # miss rate for ReadReq accesses 3529481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_rate::total 0.074807 # miss rate for ReadReq accesses 3539481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055135 # miss rate for WriteReq accesses 3549481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::total 0.055135 # miss rate for WriteReq accesses 3559481Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_rate::cpu.data 0.066092 # miss rate for demand accesses 3569481Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_rate::total 0.066092 # miss rate for demand accesses 3579481Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_rate::cpu.data 0.066092 # miss rate for overall accesses 3589481Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_rate::total 0.066092 # miss rate for overall accesses 3599481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency 3609481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency 3619481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency 3629481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency 3639481Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency 3649481Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency 3659481Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency 3669481Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency 3679481Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3689481Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3699481Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 3709481Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 3719481Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3729481Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3739481Snilay@cs.wisc.edusystem.cpu.dcache.fast_writes 0 # number of fast writes performed 3749481Snilay@cs.wisc.edusystem.cpu.dcache.cache_copies 0 # number of cache copies performed 3759481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses 3769481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses 3779481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses 3789481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses 3799481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses 3809481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses 3819481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses 3829481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses 3839481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4611000 # number of ReadReq MSHR miss cycles 3849481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_latency::total 4611000 # number of ReadReq MSHR miss cycles 3859481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2703000 # number of WriteReq MSHR miss cycles 3869481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_latency::total 2703000 # number of WriteReq MSHR miss cycles 3879481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles 3889481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles 3899481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles 3909481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles 3919481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses 3929481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses 3939481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses 3949481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses 3959481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for demand accesses 3969481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses 3979481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses 3989481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses 3999481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency 4009481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency 4019481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 4029481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 4039481Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 4049481Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 4059481Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 4069481Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 4079481Snilay@cs.wisc.edusystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 4089729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.throughput 892232795 # Throughput (bytes/s) 4099729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 390 # Transaction distribution 4109729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 390 # Transaction distribution 4119729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution 4129729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution 4139838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 606 # Packet count per connected master and slave (bytes) 4149838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) 4159838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 882 # Packet count per connected master and slave (bytes) 4169838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19392 # Cumulative packet size per connected master and slave (bytes) 4179838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) 4189838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size::total 28224 # Cumulative packet size per connected master and slave (bytes) 4199729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.data_through_bus 28224 # Total data (bytes) 4209729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 4219729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) 4229729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 4239729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 454500 # Layer occupancy (ticks) 4249729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) 4259729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) 4269729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) 4273021SN/A 4283021SN/A---------- End Simulation Statistics ---------- 429