stats.txt revision 9578:49b40999f4a2
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000125 # Number of seconds simulated 4sim_ticks 125334 # Number of ticks simulated 5final_tick 125334 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000 # Frequency of simulated ticks 7host_inst_rate 22451 # Simulator instruction rate (inst/s) 8host_op_rate 22449 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 483906 # Simulator tick rate (ticks/s) 10host_mem_usage 152108 # Number of bytes of host memory used 11host_seconds 0.26 # Real time elapsed on the host 12sim_insts 5814 # Number of instructions simulated 13sim_ops 5814 # Number of ops (including micro ops) simulated 14system.ruby.l1_cntrl0.cacheMemory.num_data_array_reads 0 # number of data array reads 15system.ruby.l1_cntrl0.cacheMemory.num_data_array_writes 0 # number of data array writes 16system.ruby.l1_cntrl0.cacheMemory.num_tag_array_reads 0 # number of tag array reads 17system.ruby.l1_cntrl0.cacheMemory.num_tag_array_writes 0 # number of tag array writes 18system.ruby.l1_cntrl0.cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array 19system.ruby.l1_cntrl0.cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array 20system.cpu.dtb.read_hits 0 # DTB read hits 21system.cpu.dtb.read_misses 0 # DTB read misses 22system.cpu.dtb.read_accesses 0 # DTB read accesses 23system.cpu.dtb.write_hits 0 # DTB write hits 24system.cpu.dtb.write_misses 0 # DTB write misses 25system.cpu.dtb.write_accesses 0 # DTB write accesses 26system.cpu.dtb.hits 0 # DTB hits 27system.cpu.dtb.misses 0 # DTB misses 28system.cpu.dtb.accesses 0 # DTB accesses 29system.cpu.itb.read_hits 0 # DTB read hits 30system.cpu.itb.read_misses 0 # DTB read misses 31system.cpu.itb.read_accesses 0 # DTB read accesses 32system.cpu.itb.write_hits 0 # DTB write hits 33system.cpu.itb.write_misses 0 # DTB write misses 34system.cpu.itb.write_accesses 0 # DTB write accesses 35system.cpu.itb.hits 0 # DTB hits 36system.cpu.itb.misses 0 # DTB misses 37system.cpu.itb.accesses 0 # DTB accesses 38system.cpu.workload.num_syscalls 8 # Number of system calls 39system.cpu.numCycles 125334 # number of cpu cycles simulated 40system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 41system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 42system.cpu.committedInsts 5814 # Number of instructions committed 43system.cpu.committedOps 5814 # Number of ops (including micro ops) committed 44system.cpu.num_int_alu_accesses 5113 # Number of integer alu accesses 45system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses 46system.cpu.num_func_calls 194 # number of times a function call or return occured 47system.cpu.num_conditional_control_insts 676 # number of instructions that are conditional controls 48system.cpu.num_int_insts 5113 # number of integer instructions 49system.cpu.num_fp_insts 2 # number of float instructions 50system.cpu.num_int_register_reads 7284 # number of times the integer registers were read 51system.cpu.num_int_register_writes 3397 # number of times the integer registers were written 52system.cpu.num_fp_register_reads 3 # number of times the floating registers were read 53system.cpu.num_fp_register_writes 1 # number of times the floating registers were written 54system.cpu.num_mem_refs 2089 # number of memory refs 55system.cpu.num_load_insts 1163 # Number of load instructions 56system.cpu.num_store_insts 926 # Number of store instructions 57system.cpu.num_idle_cycles 0 # Number of idle cycles 58system.cpu.num_busy_cycles 125334 # Number of busy cycles 59system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 60system.cpu.idle_fraction 0 # Percentage of idle cycles 61 62---------- End Simulation Statistics ---------- 63