stats.txt revision 8835:7c68f84d7c4e
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000293 # Number of seconds simulated 4sim_ticks 292960 # Number of ticks simulated 5final_tick 292960 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000 # Frequency of simulated ticks 7host_inst_rate 71598 # Simulator instruction rate (inst/s) 8host_op_rate 71583 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3598224 # Simulator tick rate (ticks/s) 10host_mem_usage 221836 # Number of bytes of host memory used 11host_seconds 0.08 # Real time elapsed on the host 12sim_insts 5827 # Number of instructions simulated 13sim_ops 5827 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 27687 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 23312 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 3658 # Number of bytes written to this memory 17system.physmem.num_reads 6992 # Number of read requests responded to by this memory 18system.physmem.num_writes 925 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 94507783 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 79574003 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 12486346 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 106994129 # Total bandwidth to/from this memory (bytes/s) 24system.cpu.dtb.read_hits 0 # DTB read hits 25system.cpu.dtb.read_misses 0 # DTB read misses 26system.cpu.dtb.read_accesses 0 # DTB read accesses 27system.cpu.dtb.write_hits 0 # DTB write hits 28system.cpu.dtb.write_misses 0 # DTB write misses 29system.cpu.dtb.write_accesses 0 # DTB write accesses 30system.cpu.dtb.hits 0 # DTB hits 31system.cpu.dtb.misses 0 # DTB misses 32system.cpu.dtb.accesses 0 # DTB accesses 33system.cpu.itb.read_hits 0 # DTB read hits 34system.cpu.itb.read_misses 0 # DTB read misses 35system.cpu.itb.read_accesses 0 # DTB read accesses 36system.cpu.itb.write_hits 0 # DTB write hits 37system.cpu.itb.write_misses 0 # DTB write misses 38system.cpu.itb.write_accesses 0 # DTB write accesses 39system.cpu.itb.hits 0 # DTB hits 40system.cpu.itb.misses 0 # DTB misses 41system.cpu.itb.accesses 0 # DTB accesses 42system.cpu.workload.num_syscalls 8 # Number of system calls 43system.cpu.numCycles 292960 # number of cpu cycles simulated 44system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 45system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 46system.cpu.committedInsts 5827 # Number of instructions committed 47system.cpu.committedOps 5827 # Number of ops (including micro ops) committed 48system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses 49system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses 50system.cpu.num_func_calls 194 # number of times a function call or return occured 51system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls 52system.cpu.num_int_insts 5126 # number of integer instructions 53system.cpu.num_fp_insts 2 # number of float instructions 54system.cpu.num_int_register_reads 7300 # number of times the integer registers were read 55system.cpu.num_int_register_writes 3409 # number of times the integer registers were written 56system.cpu.num_fp_register_reads 3 # number of times the floating registers were read 57system.cpu.num_fp_register_writes 1 # number of times the floating registers were written 58system.cpu.num_mem_refs 2090 # number of memory refs 59system.cpu.num_load_insts 1164 # Number of load instructions 60system.cpu.num_store_insts 926 # Number of store instructions 61system.cpu.num_idle_cycles 0 # Number of idle cycles 62system.cpu.num_busy_cycles 292960 # Number of busy cycles 63system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 64system.cpu.idle_fraction 0 # Percentage of idle cycles 65 66---------- End Simulation Statistics ---------- 67