16167SN/A 26167SN/A---------- Begin Simulation Statistics ---------- 311680SCurtis.Dunham@arm.comsim_seconds 0.000106 # Number of seconds simulated 411680SCurtis.Dunham@arm.comsim_ticks 106125 # Number of ticks simulated 511680SCurtis.Dunham@arm.comfinal_tick 106125 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68540SN/Asim_freq 1000000000 # Frequency of simulated ticks 711860Sandreas.hansson@arm.comhost_inst_rate 95829 # Simulator instruction rate (inst/s) 811860Sandreas.hansson@arm.comhost_op_rate 95814 # Simulator op (including micro ops) rate (op/s) 911860Sandreas.hansson@arm.comhost_tick_rate 1802278 # Simulator tick rate (ticks/s) 1011860Sandreas.hansson@arm.comhost_mem_usage 414992 # Number of bytes of host memory used 1111860Sandreas.hansson@arm.comhost_seconds 0.06 # Real time elapsed on the host 1211390Ssteve.reinhardt@amd.comsim_insts 5641 # Number of instructions simulated 1311390Ssteve.reinhardt@amd.comsim_ops 5641 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1 # Clock period in ticks 1611680SCurtis.Dunham@arm.comsystem.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states 1711390Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytes_read::ruby.dir_cntrl0 94208 # Number of bytes read from this memory 1811390Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytes_read::total 94208 # Number of bytes read from this memory 1911390Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytes_written::ruby.dir_cntrl0 93952 # Number of bytes written to this memory 2011390Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytes_written::total 93952 # Number of bytes written to this memory 2111390Ssteve.reinhardt@amd.comsystem.mem_ctrls.num_reads::ruby.dir_cntrl0 1472 # Number of read requests responded to by this memory 2211390Ssteve.reinhardt@amd.comsystem.mem_ctrls.num_reads::total 1472 # Number of read requests responded to by this memory 2311390Ssteve.reinhardt@amd.comsystem.mem_ctrls.num_writes::ruby.dir_cntrl0 1468 # Number of write requests responded to by this memory 2411390Ssteve.reinhardt@amd.comsystem.mem_ctrls.num_writes::total 1468 # Number of write requests responded to by this memory 2511680SCurtis.Dunham@arm.comsystem.mem_ctrls.bw_read::ruby.dir_cntrl0 887707892 # Total read bandwidth from this memory (bytes/s) 2611680SCurtis.Dunham@arm.comsystem.mem_ctrls.bw_read::total 887707892 # Total read bandwidth from this memory (bytes/s) 2711680SCurtis.Dunham@arm.comsystem.mem_ctrls.bw_write::ruby.dir_cntrl0 885295642 # Write bandwidth from this memory (bytes/s) 2811680SCurtis.Dunham@arm.comsystem.mem_ctrls.bw_write::total 885295642 # Write bandwidth from this memory (bytes/s) 2911680SCurtis.Dunham@arm.comsystem.mem_ctrls.bw_total::ruby.dir_cntrl0 1773003534 # Total bandwidth to/from this memory (bytes/s) 3011680SCurtis.Dunham@arm.comsystem.mem_ctrls.bw_total::total 1773003534 # Total bandwidth to/from this memory (bytes/s) 3111390Ssteve.reinhardt@amd.comsystem.mem_ctrls.readReqs 1472 # Number of read requests accepted 3211390Ssteve.reinhardt@amd.comsystem.mem_ctrls.writeReqs 1468 # Number of write requests accepted 3311390Ssteve.reinhardt@amd.comsystem.mem_ctrls.readBursts 1472 # Number of DRAM read bursts, including those serviced by the write queue 3411390Ssteve.reinhardt@amd.comsystem.mem_ctrls.writeBursts 1468 # Number of DRAM write bursts, including those merged in the write queue 3511680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesReadDRAM 58880 # Total number of bytes read from DRAM 3611680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesReadWrQ 35328 # Total number of bytes read from write queue 3711680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesWritten 59776 # Total number of bytes written to DRAM 3811390Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytesReadSys 94208 # Total read bytes from the system interface side 3911390Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytesWrittenSys 93952 # Total written bytes from the system interface side 4011680SCurtis.Dunham@arm.comsystem.mem_ctrls.servicedByWrQ 552 # Number of DRAM read bursts serviced by the write queue 4111680SCurtis.Dunham@arm.comsystem.mem_ctrls.mergedWrBursts 510 # Number of DRAM write bursts merged with an existing one 4210526Snilay@cs.wisc.edusystem.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 4311680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::0 31 # Per bank write bursts 4410526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::1 0 # Per bank write bursts 4510526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::2 0 # Per bank write bursts 4610526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::3 0 # Per bank write bursts 4710526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::4 7 # Per bank write bursts 4810526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::5 3 # Per bank write bursts 4911390Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankRdBursts::6 13 # Per bank write bursts 5011680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::7 83 # Per bank write bursts 5111023Sjthestness@gmail.comsystem.mem_ctrls.perBankRdBursts::8 66 # Per bank write bursts 5211680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::9 250 # Per bank write bursts 5311680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::10 100 # Per bank write bursts 5411680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::11 44 # Per bank write bursts 5511680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::12 107 # Per bank write bursts 5611680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::13 46 # Per bank write bursts 5711680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::14 157 # Per bank write bursts 5811680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::15 13 # Per bank write bursts 5911680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankWrBursts::0 32 # Per bank write bursts 6010526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts 6110526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts 6210526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts 6310526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::4 7 # Per bank write bursts 6410526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::5 3 # Per bank write bursts 6511390Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankWrBursts::6 13 # Per bank write bursts 6611680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankWrBursts::7 75 # Per bank write bursts 6711390Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankWrBursts::8 60 # Per bank write bursts 6811680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankWrBursts::9 250 # Per bank write bursts 6911390Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankWrBursts::10 100 # Per bank write bursts 7011680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankWrBursts::11 45 # Per bank write bursts 7111680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankWrBursts::12 110 # Per bank write bursts 7211680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankWrBursts::13 48 # Per bank write bursts 7311680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankWrBursts::14 177 # Per bank write bursts 7411390Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankWrBursts::15 14 # Per bank write bursts 7510526Snilay@cs.wisc.edusystem.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry 7610526Snilay@cs.wisc.edusystem.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry 7711680SCurtis.Dunham@arm.comsystem.mem_ctrls.totGap 106076 # Total gap between requests 7810526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) 7910526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) 8010526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) 8110526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) 8210526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) 8310526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) 8411390Ssteve.reinhardt@amd.comsystem.mem_ctrls.readPktSize::6 1472 # Read request sizes (log2) 8510526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) 8610526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) 8710526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) 8810526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) 8910526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) 9010526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) 9111390Ssteve.reinhardt@amd.comsystem.mem_ctrls.writePktSize::6 1468 # Write request sizes (log2) 9211680SCurtis.Dunham@arm.comsystem.mem_ctrls.rdQLenPdf::0 920 # What read queue length does an incoming req see 9310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see 9410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see 9510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see 9610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see 9710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see 9810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see 9910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see 10010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see 10110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see 10210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see 10310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see 10410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see 10510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see 10610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see 10710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see 10810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see 10910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see 11010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see 11110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see 11210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see 11310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see 11410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see 11510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see 11610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see 11710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see 11810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see 11910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see 12010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see 12110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see 12210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see 12310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see 12410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see 12510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see 12610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see 12710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see 12810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see 12910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see 13010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see 13110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see 13210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see 13310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see 13410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see 13510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see 13610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see 13710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see 13810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see 13911680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::15 8 # What write queue length does an incoming req see 14011680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::16 11 # What write queue length does an incoming req see 14111680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::17 51 # What write queue length does an incoming req see 14211680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::18 61 # What write queue length does an incoming req see 14311390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::19 60 # What write queue length does an incoming req see 14411680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::20 61 # What write queue length does an incoming req see 14511390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::21 61 # What write queue length does an incoming req see 14611680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::22 58 # What write queue length does an incoming req see 14711680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::23 59 # What write queue length does an incoming req see 14811680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::24 57 # What write queue length does an incoming req see 14911680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::25 57 # What write queue length does an incoming req see 15011680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::26 57 # What write queue length does an incoming req see 15111680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::27 57 # What write queue length does an incoming req see 15211680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::28 57 # What write queue length does an incoming req see 15311680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::29 57 # What write queue length does an incoming req see 15411680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::30 57 # What write queue length does an incoming req see 15511680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::31 57 # What write queue length does an incoming req see 15611680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::32 57 # What write queue length does an incoming req see 15711680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see 15810892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see 15910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see 16010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see 16110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see 16210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see 16310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see 16410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see 16510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see 16610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see 16710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see 16810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see 16910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see 17010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see 17110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see 17210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see 17310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see 17410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see 17510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see 17610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see 17710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see 17810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see 17910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see 18010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see 18110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see 18210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see 18310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see 18410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see 18510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see 18610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see 18710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see 18811680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::samples 352 # Bytes accessed per row activation 18911680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::mean 334.181818 # Bytes accessed per row activation 19011680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::gmean 220.342342 # Bytes accessed per row activation 19111680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::stdev 312.466834 # Bytes accessed per row activation 19211680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::0-127 73 20.74% 20.74% # Bytes accessed per row activation 19311680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::128-255 116 32.95% 53.69% # Bytes accessed per row activation 19411680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::256-383 49 13.92% 67.61% # Bytes accessed per row activation 19511680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::384-511 31 8.81% 76.42% # Bytes accessed per row activation 19611680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::512-639 18 5.11% 81.53% # Bytes accessed per row activation 19711680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::640-767 13 3.69% 85.23% # Bytes accessed per row activation 19811680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::768-895 9 2.56% 87.78% # Bytes accessed per row activation 19911680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::896-1023 3 0.85% 88.64% # Bytes accessed per row activation 20011680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::1024-1151 40 11.36% 100.00% # Bytes accessed per row activation 20111680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::total 352 # Bytes accessed per row activation 20211680SCurtis.Dunham@arm.comsystem.mem_ctrls.rdPerTurnAround::samples 57 # Reads before turning the bus around for writes 20311680SCurtis.Dunham@arm.comsystem.mem_ctrls.rdPerTurnAround::mean 16 # Reads before turning the bus around for writes 20411680SCurtis.Dunham@arm.comsystem.mem_ctrls.rdPerTurnAround::gmean 15.842454 # Reads before turning the bus around for writes 20511680SCurtis.Dunham@arm.comsystem.mem_ctrls.rdPerTurnAround::stdev 2.738613 # Reads before turning the bus around for writes 20611680SCurtis.Dunham@arm.comsystem.mem_ctrls.rdPerTurnAround::12-13 2 3.51% 3.51% # Reads before turning the bus around for writes 20711680SCurtis.Dunham@arm.comsystem.mem_ctrls.rdPerTurnAround::14-15 25 43.86% 47.37% # Reads before turning the bus around for writes 20811680SCurtis.Dunham@arm.comsystem.mem_ctrls.rdPerTurnAround::16-17 25 43.86% 91.23% # Reads before turning the bus around for writes 20911680SCurtis.Dunham@arm.comsystem.mem_ctrls.rdPerTurnAround::18-19 4 7.02% 98.25% # Reads before turning the bus around for writes 21011680SCurtis.Dunham@arm.comsystem.mem_ctrls.rdPerTurnAround::34-35 1 1.75% 100.00% # Reads before turning the bus around for writes 21111680SCurtis.Dunham@arm.comsystem.mem_ctrls.rdPerTurnAround::total 57 # Reads before turning the bus around for writes 21211680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrPerTurnAround::samples 57 # Writes before turning the bus around for reads 21311680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrPerTurnAround::mean 16.385965 # Writes before turning the bus around for reads 21411680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrPerTurnAround::gmean 16.360622 # Writes before turning the bus around for reads 21511680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrPerTurnAround::stdev 0.959062 # Writes before turning the bus around for reads 21611680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrPerTurnAround::16 48 84.21% 84.21% # Writes before turning the bus around for reads 21711680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrPerTurnAround::17 1 1.75% 85.96% # Writes before turning the bus around for reads 21811680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrPerTurnAround::18 4 7.02% 92.98% # Writes before turning the bus around for reads 21911680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrPerTurnAround::19 3 5.26% 98.25% # Writes before turning the bus around for reads 22011680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrPerTurnAround::20 1 1.75% 100.00% # Writes before turning the bus around for reads 22111680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrPerTurnAround::total 57 # Writes before turning the bus around for reads 22211680SCurtis.Dunham@arm.comsystem.mem_ctrls.totQLat 18473 # Total ticks spent queuing 22311680SCurtis.Dunham@arm.comsystem.mem_ctrls.totMemAccLat 35953 # Total ticks spent from burst creation until serviced by the DRAM 22411680SCurtis.Dunham@arm.comsystem.mem_ctrls.totBusLat 4600 # Total ticks spent in databus transfers 22511680SCurtis.Dunham@arm.comsystem.mem_ctrls.avgQLat 20.08 # Average queueing delay per DRAM burst 22610526Snilay@cs.wisc.edusystem.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst 22711680SCurtis.Dunham@arm.comsystem.mem_ctrls.avgMemAccLat 39.08 # Average memory access latency per DRAM burst 22811680SCurtis.Dunham@arm.comsystem.mem_ctrls.avgRdBW 554.82 # Average DRAM read bandwidth in MiByte/s 22911680SCurtis.Dunham@arm.comsystem.mem_ctrls.avgWrBW 563.26 # Average achieved write bandwidth in MiByte/s 23011680SCurtis.Dunham@arm.comsystem.mem_ctrls.avgRdBWSys 887.71 # Average system read bandwidth in MiByte/s 23111680SCurtis.Dunham@arm.comsystem.mem_ctrls.avgWrBWSys 885.30 # Average system write bandwidth in MiByte/s 23210526Snilay@cs.wisc.edusystem.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 23311680SCurtis.Dunham@arm.comsystem.mem_ctrls.busUtil 8.73 # Data bus utilization in percentage 23411680SCurtis.Dunham@arm.comsystem.mem_ctrls.busUtilRead 4.33 # Data bus utilization in percentage for reads 23511680SCurtis.Dunham@arm.comsystem.mem_ctrls.busUtilWrite 4.40 # Data bus utilization in percentage for writes 23610526Snilay@cs.wisc.edusystem.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing 23711680SCurtis.Dunham@arm.comsystem.mem_ctrls.avgWrQLen 25.41 # Average write queue length when enqueuing 23811680SCurtis.Dunham@arm.comsystem.mem_ctrls.readRowHits 632 # Number of row buffer hits during reads 23911680SCurtis.Dunham@arm.comsystem.mem_ctrls.writeRowHits 865 # Number of row buffer hits during writes 24011680SCurtis.Dunham@arm.comsystem.mem_ctrls.readRowHitRate 68.70 # Row buffer hit rate for reads 24111680SCurtis.Dunham@arm.comsystem.mem_ctrls.writeRowHitRate 90.29 # Row buffer hit rate for writes 24211680SCurtis.Dunham@arm.comsystem.mem_ctrls.avgGap 36.08 # Average gap between requests 24311680SCurtis.Dunham@arm.comsystem.mem_ctrls.pageHitRate 79.71 # Row buffer hit rate, read and write combined 24411680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.actEnergy 542640 # Energy for activate commands per rank (pJ) 24511680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.preEnergy 289800 # Energy for precharge commands per rank (pJ) 24611680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.readEnergy 1565088 # Energy for read commands per rank (pJ) 24711680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.writeEnergy 1085760 # Energy for write commands per rank (pJ) 24811680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) 24911680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.actBackEnergy 15123696 # Energy for active background per rank (pJ) 25011680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.preBackEnergy 297600 # Energy for precharge background per rank (pJ) 25111680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.actPowerDownEnergy 24352224 # Energy for active power-down per rank (pJ) 25211680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.prePowerDownEnergy 7106304 # Energy for precharge power-down per rank (pJ) 25311680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.selfRefreshEnergy 647736.000000 # Energy for self refresh per rank (pJ) 25411680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.totalEnergy 59655384 # Total energy per rank (pJ) 25511680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.averagePower 562.123760 # Core power per rank (mW) 25611680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.totalIdleTime 71087 # Total Idle time Per DRAM Rank 25711680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.memoryStateTime::IDLE 340 # Time in different power states 25811680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.memoryStateTime::REF 3646 # Time in different power states 25911680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.memoryStateTime::SREF 185 # Time in different power states 26011680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.memoryStateTime::PRE_PDN 18506 # Time in different power states 26111680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.memoryStateTime::ACT 30044 # Time in different power states 26211680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.memoryStateTime::ACT_PDN 53404 # Time in different power states 26311680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.actEnergy 2006340 # Energy for activate commands per rank (pJ) 26411680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.preEnergy 1070328 # Energy for precharge commands per rank (pJ) 26511680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.readEnergy 8944992 # Energy for read commands per rank (pJ) 26611680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.writeEnergy 6715008 # Energy for write commands per rank (pJ) 26711680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.refreshEnergy 7990320.000000 # Energy for refresh commands per rank (pJ) 26811680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.actBackEnergy 16837800 # Energy for active background per rank (pJ) 26911680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.preBackEnergy 207360 # Energy for precharge background per rank (pJ) 27011680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.actPowerDownEnergy 31179912 # Energy for active power-down per rank (pJ) 27111680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.prePowerDownEnergy 108672 # Energy for precharge power-down per rank (pJ) 27211680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 27311680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.totalEnergy 75060732 # Total energy per rank (pJ) 27411680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.averagePower 707.286049 # Core power per rank (mW) 27511680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.totalIdleTime 68578 # Total Idle time Per DRAM Rank 27611680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.memoryStateTime::IDLE 148 # Time in different power states 27711680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.memoryStateTime::REF 3380 # Time in different power states 27811680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states 27911680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.memoryStateTime::PRE_PDN 283 # Time in different power states 28011680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.memoryStateTime::ACT 33937 # Time in different power states 28111680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.memoryStateTime::ACT_PDN 68377 # Time in different power states 28211680SCurtis.Dunham@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states 28310036SAli.Saidi@ARM.comsystem.cpu.clk_domain.clock 1 # Clock period in ticks 2848540SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 2858540SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 2868540SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 2878540SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 2888540SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 2898540SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 2906167SN/Asystem.cpu.dtb.hits 0 # DTB hits 2916167SN/Asystem.cpu.dtb.misses 0 # DTB misses 2928540SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 2938540SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 2948540SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 2958540SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 2968540SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 2978540SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 2988540SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 2996167SN/Asystem.cpu.itb.hits 0 # DTB hits 3006167SN/Asystem.cpu.itb.misses 0 # DTB misses 3018540SN/Asystem.cpu.itb.accesses 0 # DTB accesses 30211955Sgabeblack@google.comsystem.cpu.workload.numSyscalls 7 # Number of system calls 30311680SCurtis.Dunham@arm.comsystem.cpu.pwrStateResidencyTicks::ON 106125 # Cumulative time (in ticks) in various power states 30411680SCurtis.Dunham@arm.comsystem.cpu.numCycles 106125 # number of cpu cycles simulated 3058540SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 3067935SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 30711390Ssteve.reinhardt@amd.comsystem.cpu.committedInsts 5641 # Number of instructions committed 30811390Ssteve.reinhardt@amd.comsystem.cpu.committedOps 5641 # Number of ops (including micro ops) committed 30911390Ssteve.reinhardt@amd.comsystem.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses 3108540SN/Asystem.cpu.num_fp_alu_accesses 2 # Number of float alu accesses 31111390Ssteve.reinhardt@amd.comsystem.cpu.num_func_calls 191 # number of times a function call or return occured 31211390Ssteve.reinhardt@amd.comsystem.cpu.num_conditional_control_insts 651 # number of instructions that are conditional controls 31311390Ssteve.reinhardt@amd.comsystem.cpu.num_int_insts 4957 # number of integer instructions 3147935SN/Asystem.cpu.num_fp_insts 2 # number of float instructions 31511390Ssteve.reinhardt@amd.comsystem.cpu.num_int_register_reads 7072 # number of times the integer registers were read 31611390Ssteve.reinhardt@amd.comsystem.cpu.num_int_register_writes 3291 # number of times the integer registers were written 3177935SN/Asystem.cpu.num_fp_register_reads 3 # number of times the floating registers were read 3187935SN/Asystem.cpu.num_fp_register_writes 1 # number of times the floating registers were written 31911390Ssteve.reinhardt@amd.comsystem.cpu.num_mem_refs 2037 # number of memory refs 32011390Ssteve.reinhardt@amd.comsystem.cpu.num_load_insts 1135 # Number of load instructions 32110488Snilay@cs.wisc.edusystem.cpu.num_store_insts 902 # Number of store instructions 3227935SN/Asystem.cpu.num_idle_cycles 0 # Number of idle cycles 32311680SCurtis.Dunham@arm.comsystem.cpu.num_busy_cycles 106125 # Number of busy cycles 3248540SN/Asystem.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 3258540SN/Asystem.cpu.idle_fraction 0 # Percentage of idle cycles 32611390Ssteve.reinhardt@amd.comsystem.cpu.Branches 886 # Number of branches fetched 32711390Ssteve.reinhardt@amd.comsystem.cpu.op_class::No_OpClass 641 11.36% 11.36% # Class of executed instruction 32811390Ssteve.reinhardt@amd.comsystem.cpu.op_class::IntAlu 2960 52.46% 63.82% # Class of executed instruction 32911390Ssteve.reinhardt@amd.comsystem.cpu.op_class::IntMult 2 0.04% 63.86% # Class of executed instruction 33011390Ssteve.reinhardt@amd.comsystem.cpu.op_class::IntDiv 0 0.00% 63.86% # Class of executed instruction 33111390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatAdd 2 0.04% 63.90% # Class of executed instruction 33211390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction 33311390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction 33411390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction 33511687Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMultAcc 0 0.00% 63.90% # Class of executed instruction 33611390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction 33711687Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMisc 0 0.00% 63.90% # Class of executed instruction 33811390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction 33911390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction 34011390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction 34111390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdAlu 0 0.00% 63.90% # Class of executed instruction 34211390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdCmp 0 0.00% 63.90% # Class of executed instruction 34311390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdCvt 0 0.00% 63.90% # Class of executed instruction 34411390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdMisc 0 0.00% 63.90% # Class of executed instruction 34511390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdMult 0 0.00% 63.90% # Class of executed instruction 34611390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdMultAcc 0 0.00% 63.90% # Class of executed instruction 34711390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdShift 0 0.00% 63.90% # Class of executed instruction 34811390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdShiftAcc 0 0.00% 63.90% # Class of executed instruction 34911390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdSqrt 0 0.00% 63.90% # Class of executed instruction 35011390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatAdd 0 0.00% 63.90% # Class of executed instruction 35111390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatAlu 0 0.00% 63.90% # Class of executed instruction 35211390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatCmp 0 0.00% 63.90% # Class of executed instruction 35311390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatCvt 0 0.00% 63.90% # Class of executed instruction 35411390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatDiv 0 0.00% 63.90% # Class of executed instruction 35511390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatMisc 0 0.00% 63.90% # Class of executed instruction 35611390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction 35711390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction 35811390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction 35911390Ssteve.reinhardt@amd.comsystem.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction 36011390Ssteve.reinhardt@amd.comsystem.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction 36111687Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction 36211687Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction 36310220Sandreas.hansson@arm.comsystem.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 36410220Sandreas.hansson@arm.comsystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 36511390Ssteve.reinhardt@amd.comsystem.cpu.op_class::total 5642 # Class of executed instruction 36610628Sandreas.hansson@arm.comsystem.ruby.clk_domain.clock 1 # Clock period in ticks 36711680SCurtis.Dunham@arm.comsystem.ruby.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states 36810628Sandreas.hansson@arm.comsystem.ruby.delayHist::bucket_size 1 # delay histogram for all message 36910628Sandreas.hansson@arm.comsystem.ruby.delayHist::max_bucket 9 # delay histogram for all message 37011390Ssteve.reinhardt@amd.comsystem.ruby.delayHist::samples 2940 # delay histogram for all message 37111390Ssteve.reinhardt@amd.comsystem.ruby.delayHist | 2940 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message 37211390Ssteve.reinhardt@amd.comsystem.ruby.delayHist::total 2940 # delay histogram for all message 37311312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::bucket_size 1 37411312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::max_bucket 9 37511390Ssteve.reinhardt@amd.comsystem.ruby.outstanding_req_hist_seqr::samples 7679 37611312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::mean 1 37711312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::gmean 1 37811390Ssteve.reinhardt@amd.comsystem.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 7679 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 37911390Ssteve.reinhardt@amd.comsystem.ruby.outstanding_req_hist_seqr::total 7679 38011312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_seqr::bucket_size 64 38111312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_seqr::max_bucket 639 38211390Ssteve.reinhardt@amd.comsystem.ruby.latency_hist_seqr::samples 7678 38311680SCurtis.Dunham@arm.comsystem.ruby.latency_hist_seqr::mean 12.821959 38411680SCurtis.Dunham@arm.comsystem.ruby.latency_hist_seqr::gmean 2.158431 38511680SCurtis.Dunham@arm.comsystem.ruby.latency_hist_seqr::stdev 29.332675 38611680SCurtis.Dunham@arm.comsystem.ruby.latency_hist_seqr | 6783 88.34% 88.34% | 834 10.86% 99.21% | 40 0.52% 99.73% | 8 0.10% 99.83% | 8 0.10% 99.93% | 5 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 38711390Ssteve.reinhardt@amd.comsystem.ruby.latency_hist_seqr::total 7678 38811312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr::bucket_size 1 38911312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr::max_bucket 9 39011390Ssteve.reinhardt@amd.comsystem.ruby.hit_latency_hist_seqr::samples 6206 39111312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr::mean 1 39211312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr::gmean 1 39311390Ssteve.reinhardt@amd.comsystem.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 6206 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 39411390Ssteve.reinhardt@amd.comsystem.ruby.hit_latency_hist_seqr::total 6206 39511312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr::bucket_size 64 39611312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr::max_bucket 639 39711390Ssteve.reinhardt@amd.comsystem.ruby.miss_latency_hist_seqr::samples 1472 39811680SCurtis.Dunham@arm.comsystem.ruby.miss_latency_hist_seqr::mean 62.663723 39911680SCurtis.Dunham@arm.comsystem.ruby.miss_latency_hist_seqr::gmean 55.319189 40011680SCurtis.Dunham@arm.comsystem.ruby.miss_latency_hist_seqr::stdev 37.614530 40111680SCurtis.Dunham@arm.comsystem.ruby.miss_latency_hist_seqr | 577 39.20% 39.20% | 834 56.66% 95.86% | 40 2.72% 98.57% | 8 0.54% 99.12% | 8 0.54% 99.66% | 5 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 40211390Ssteve.reinhardt@amd.comsystem.ruby.miss_latency_hist_seqr::total 1472 40311390Ssteve.reinhardt@amd.comsystem.ruby.Directory.incomplete_times_seqr 1471 40411860Sandreas.hansson@arm.comsystem.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.013833 # Average number of messages in buffer 40511860Sandreas.hansson@arm.comsystem.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.997663 # Average number of cycles messages are stalled in this MB 40611860Sandreas.hansson@arm.comsystem.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.027703 # Average number of messages in buffer 40711860Sandreas.hansson@arm.comsystem.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.765826 # Average number of cycles messages are stalled in this MB 40811860Sandreas.hansson@arm.comsystem.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.013870 # Average number of messages in buffer 40911860Sandreas.hansson@arm.comsystem.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999350 # Average number of cycles messages are stalled in this MB 41011860Sandreas.hansson@arm.comsystem.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.027703 # Average number of messages in buffer 41111860Sandreas.hansson@arm.comsystem.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999359 # Average number of cycles messages are stalled in this MB 41211680SCurtis.Dunham@arm.comsystem.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states 41311390Ssteve.reinhardt@amd.comsystem.ruby.l1_cntrl0.cacheMemory.demand_hits 6206 # Number of cache demand hits 41411390Ssteve.reinhardt@amd.comsystem.ruby.l1_cntrl0.cacheMemory.demand_misses 1472 # Number of cache demand misses 41511390Ssteve.reinhardt@amd.comsystem.ruby.l1_cntrl0.cacheMemory.demand_accesses 7678 # Number of cache demand accesses 41611860Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.013833 # Average number of messages in buffer 41711860Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.983246 # Average number of cycles messages are stalled in this MB 41811860Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.072357 # Average number of messages in buffer 41911860Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999991 # Average number of cycles messages are stalled in this MB 42011860Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.055406 # Average number of messages in buffer 42111860Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999943 # Average number of cycles messages are stalled in this MB 42211860Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.013870 # Average number of messages in buffer 42311860Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.995053 # Average number of cycles messages are stalled in this MB 42411680SCurtis.Dunham@arm.comsystem.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states 42511680SCurtis.Dunham@arm.comsystem.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states 42610628Sandreas.hansson@arm.comsystem.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks 42711860Sandreas.hansson@arm.comsystem.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.013833 # Average number of messages in buffer 42811860Sandreas.hansson@arm.comsystem.ruby.network.routers0.port_buffers03.avg_stall_time 5.985696 # Average number of cycles messages are stalled in this MB 42911860Sandreas.hansson@arm.comsystem.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.013870 # Average number of messages in buffer 43011860Sandreas.hansson@arm.comsystem.ruby.network.routers0.port_buffers04.avg_stall_time 5.995816 # Average number of cycles messages are stalled in this MB 43111860Sandreas.hansson@arm.comsystem.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.083033 # Average number of messages in buffer 43211860Sandreas.hansson@arm.comsystem.ruby.network.routers0.port_buffers07.avg_stall_time 6.766579 # Average number of cycles messages are stalled in this MB 43311680SCurtis.Dunham@arm.comsystem.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states 43411680SCurtis.Dunham@arm.comsystem.ruby.network.routers0.percent_links_utilized 6.925795 43511390Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.msg_count.Control::2 1472 43611390Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.msg_count.Data::2 1468 43711390Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.msg_count.Response_Data::4 1472 43811390Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.msg_count.Writeback_Control::3 1468 43911390Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.msg_bytes.Control::2 11776 44011390Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.msg_bytes.Data::2 105696 44111390Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.msg_bytes.Response_Data::4 105984 44211390Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.msg_bytes.Writeback_Control::3 11744 44311860Sandreas.hansson@arm.comsystem.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.027703 # Average number of messages in buffer 44411860Sandreas.hansson@arm.comsystem.ruby.network.routers1.port_buffers02.avg_stall_time 10.766014 # Average number of cycles messages are stalled in this MB 44511860Sandreas.hansson@arm.comsystem.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.013833 # Average number of messages in buffer 44611860Sandreas.hansson@arm.comsystem.ruby.network.routers1.port_buffers06.avg_stall_time 1.995307 # Average number of cycles messages are stalled in this MB 44711860Sandreas.hansson@arm.comsystem.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.013870 # Average number of messages in buffer 44811860Sandreas.hansson@arm.comsystem.ruby.network.routers1.port_buffers07.avg_stall_time 1.998681 # Average number of cycles messages are stalled in this MB 44911680SCurtis.Dunham@arm.comsystem.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states 45011680SCurtis.Dunham@arm.comsystem.ruby.network.routers1.percent_links_utilized 6.925795 45111390Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.msg_count.Control::2 1472 45211390Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.msg_count.Data::2 1468 45311390Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.msg_count.Response_Data::4 1472 45411390Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.msg_count.Writeback_Control::3 1468 45511390Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.msg_bytes.Control::2 11776 45611390Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.msg_bytes.Data::2 105696 45711390Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.msg_bytes.Response_Data::4 105984 45811390Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.msg_bytes.Writeback_Control::3 11744 45911860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers02.avg_buf_msgs 0.027703 # Average number of messages in buffer 46011860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers02.avg_stall_time 7.766466 # Average number of cycles messages are stalled in this MB 46111860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers08.avg_buf_msgs 0.013833 # Average number of messages in buffer 46211860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers08.avg_stall_time 2.992933 # Average number of cycles messages are stalled in this MB 46311860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers09.avg_buf_msgs 0.013870 # Average number of messages in buffer 46411860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers09.avg_stall_time 2.997993 # Average number of cycles messages are stalled in this MB 46511860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers13.avg_buf_msgs 0.013833 # Average number of messages in buffer 46611860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers13.avg_stall_time 4.988127 # Average number of cycles messages are stalled in this MB 46711860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers14.avg_buf_msgs 0.013870 # Average number of messages in buffer 46811860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers14.avg_stall_time 4.996561 # Average number of cycles messages are stalled in this MB 46911860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers17.avg_buf_msgs 0.027703 # Average number of messages in buffer 47011860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers17.avg_stall_time 9.766184 # Average number of cycles messages are stalled in this MB 47111860Sandreas.hansson@arm.comsystem.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.013833 # Average number of messages in buffer 47211860Sandreas.hansson@arm.comsystem.ruby.network.routers2.port_buffers03.avg_stall_time 3.990540 # Average number of cycles messages are stalled in this MB 47311860Sandreas.hansson@arm.comsystem.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.013870 # Average number of messages in buffer 47411860Sandreas.hansson@arm.comsystem.ruby.network.routers2.port_buffers04.avg_stall_time 3.997286 # Average number of cycles messages are stalled in this MB 47511860Sandreas.hansson@arm.comsystem.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.027703 # Average number of messages in buffer 47611860Sandreas.hansson@arm.comsystem.ruby.network.routers2.port_buffers07.avg_stall_time 8.766334 # Average number of cycles messages are stalled in this MB 47711680SCurtis.Dunham@arm.comsystem.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states 47811680SCurtis.Dunham@arm.comsystem.ruby.network.routers2.percent_links_utilized 6.925795 47911390Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.msg_count.Control::2 1472 48011390Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.msg_count.Data::2 1468 48111390Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.msg_count.Response_Data::4 1472 48211390Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.msg_count.Writeback_Control::3 1468 48311390Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.msg_bytes.Control::2 11776 48411390Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.msg_bytes.Data::2 105696 48511390Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.msg_bytes.Response_Data::4 105984 48611390Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.msg_bytes.Writeback_Control::3 11744 48711680SCurtis.Dunham@arm.comsystem.ruby.network.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states 48811390Ssteve.reinhardt@amd.comsystem.ruby.network.msg_count.Control 4416 48911390Ssteve.reinhardt@amd.comsystem.ruby.network.msg_count.Data 4404 49011390Ssteve.reinhardt@amd.comsystem.ruby.network.msg_count.Response_Data 4416 49111390Ssteve.reinhardt@amd.comsystem.ruby.network.msg_count.Writeback_Control 4404 49211390Ssteve.reinhardt@amd.comsystem.ruby.network.msg_byte.Control 35328 49311390Ssteve.reinhardt@amd.comsystem.ruby.network.msg_byte.Data 317088 49411390Ssteve.reinhardt@amd.comsystem.ruby.network.msg_byte.Response_Data 317952 49511390Ssteve.reinhardt@amd.comsystem.ruby.network.msg_byte.Writeback_Control 35232 49611680SCurtis.Dunham@arm.comsystem.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states 49711680SCurtis.Dunham@arm.comsystem.ruby.network.routers0.throttle0.link_utilization 6.933333 49811390Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1472 49911390Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1468 50011390Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 105984 50111390Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 11744 50211680SCurtis.Dunham@arm.comsystem.ruby.network.routers0.throttle1.link_utilization 6.918257 50311390Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle1.msg_count.Control::2 1472 50411390Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle1.msg_count.Data::2 1468 50511390Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle1.msg_bytes.Control::2 11776 50611390Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle1.msg_bytes.Data::2 105696 50711680SCurtis.Dunham@arm.comsystem.ruby.network.routers1.throttle0.link_utilization 6.918257 50811390Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle0.msg_count.Control::2 1472 50911390Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle0.msg_count.Data::2 1468 51011390Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle0.msg_bytes.Control::2 11776 51111390Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle0.msg_bytes.Data::2 105696 51211680SCurtis.Dunham@arm.comsystem.ruby.network.routers1.throttle1.link_utilization 6.933333 51311390Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1472 51411390Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1468 51511390Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 105984 51611390Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 11744 51711680SCurtis.Dunham@arm.comsystem.ruby.network.routers2.throttle0.link_utilization 6.933333 51811390Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1472 51911390Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1468 52011390Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 105984 52111390Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 11744 52211680SCurtis.Dunham@arm.comsystem.ruby.network.routers2.throttle1.link_utilization 6.918257 52311390Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle1.msg_count.Control::2 1472 52411390Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle1.msg_count.Data::2 1468 52511390Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle1.msg_bytes.Control::2 11776 52611390Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle1.msg_bytes.Data::2 105696 52710013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 52810013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 52911390Ssteve.reinhardt@amd.comsystem.ruby.delayVCHist.vnet_1::samples 1472 # delay histogram for vnet_1 53011390Ssteve.reinhardt@amd.comsystem.ruby.delayVCHist.vnet_1 | 1472 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 53111390Ssteve.reinhardt@amd.comsystem.ruby.delayVCHist.vnet_1::total 1472 # delay histogram for vnet_1 53210013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 53310013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 53411390Ssteve.reinhardt@amd.comsystem.ruby.delayVCHist.vnet_2::samples 1468 # delay histogram for vnet_2 53511390Ssteve.reinhardt@amd.comsystem.ruby.delayVCHist.vnet_2 | 1468 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 53611390Ssteve.reinhardt@amd.comsystem.ruby.delayVCHist.vnet_2::total 1468 # delay histogram for vnet_2 53711390Ssteve.reinhardt@amd.comsystem.ruby.LD.latency_hist_seqr::bucket_size 64 53811390Ssteve.reinhardt@amd.comsystem.ruby.LD.latency_hist_seqr::max_bucket 639 53911390Ssteve.reinhardt@amd.comsystem.ruby.LD.latency_hist_seqr::samples 1135 54011680SCurtis.Dunham@arm.comsystem.ruby.LD.latency_hist_seqr::mean 35.394714 54111680SCurtis.Dunham@arm.comsystem.ruby.LD.latency_hist_seqr::gmean 10.319359 54211680SCurtis.Dunham@arm.comsystem.ruby.LD.latency_hist_seqr::stdev 39.399406 54311680SCurtis.Dunham@arm.comsystem.ruby.LD.latency_hist_seqr | 768 67.67% 67.67% | 344 30.31% 97.97% | 15 1.32% 99.30% | 4 0.35% 99.65% | 2 0.18% 99.82% | 2 0.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 54411390Ssteve.reinhardt@amd.comsystem.ruby.LD.latency_hist_seqr::total 1135 54511312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr::bucket_size 1 54611312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr::max_bucket 9 54711390Ssteve.reinhardt@amd.comsystem.ruby.LD.hit_latency_hist_seqr::samples 466 54811312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr::mean 1 54911312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr::gmean 1 55011390Ssteve.reinhardt@amd.comsystem.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 466 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 55111390Ssteve.reinhardt@amd.comsystem.ruby.LD.hit_latency_hist_seqr::total 466 55211390Ssteve.reinhardt@amd.comsystem.ruby.LD.miss_latency_hist_seqr::bucket_size 64 55311390Ssteve.reinhardt@amd.comsystem.ruby.LD.miss_latency_hist_seqr::max_bucket 639 55411390Ssteve.reinhardt@amd.comsystem.ruby.LD.miss_latency_hist_seqr::samples 669 55511680SCurtis.Dunham@arm.comsystem.ruby.LD.miss_latency_hist_seqr::mean 59.352765 55611680SCurtis.Dunham@arm.comsystem.ruby.LD.miss_latency_hist_seqr::gmean 52.447495 55711680SCurtis.Dunham@arm.comsystem.ruby.LD.miss_latency_hist_seqr::stdev 35.144031 55811680SCurtis.Dunham@arm.comsystem.ruby.LD.miss_latency_hist_seqr | 302 45.14% 45.14% | 344 51.42% 96.56% | 15 2.24% 98.80% | 4 0.60% 99.40% | 2 0.30% 99.70% | 2 0.30% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 55911390Ssteve.reinhardt@amd.comsystem.ruby.LD.miss_latency_hist_seqr::total 669 56011680SCurtis.Dunham@arm.comsystem.ruby.ST.latency_hist_seqr::bucket_size 32 56111680SCurtis.Dunham@arm.comsystem.ruby.ST.latency_hist_seqr::max_bucket 319 56211312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_seqr::samples 901 56311680SCurtis.Dunham@arm.comsystem.ruby.ST.latency_hist_seqr::mean 13.442841 56411680SCurtis.Dunham@arm.comsystem.ruby.ST.latency_hist_seqr::gmean 2.518866 56511680SCurtis.Dunham@arm.comsystem.ruby.ST.latency_hist_seqr::stdev 27.757167 56611680SCurtis.Dunham@arm.comsystem.ruby.ST.latency_hist_seqr | 684 75.92% 75.92% | 130 14.43% 90.34% | 81 8.99% 99.33% | 0 0.00% 99.33% | 1 0.11% 99.45% | 3 0.33% 99.78% | 0 0.00% 99.78% | 0 0.00% 99.78% | 1 0.11% 99.89% | 1 0.11% 100.00% 56711312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_seqr::total 901 56811312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::bucket_size 1 56911312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::max_bucket 9 57011312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::samples 684 57111312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::mean 1 57211312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::gmean 1 57311312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 684 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 57411312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::total 684 57511680SCurtis.Dunham@arm.comsystem.ruby.ST.miss_latency_hist_seqr::bucket_size 32 57611680SCurtis.Dunham@arm.comsystem.ruby.ST.miss_latency_hist_seqr::max_bucket 319 57711312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr::samples 217 57811680SCurtis.Dunham@arm.comsystem.ruby.ST.miss_latency_hist_seqr::mean 52.663594 57911680SCurtis.Dunham@arm.comsystem.ruby.ST.miss_latency_hist_seqr::gmean 46.326875 58011680SCurtis.Dunham@arm.comsystem.ruby.ST.miss_latency_hist_seqr::stdev 34.272225 58111680SCurtis.Dunham@arm.comsystem.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 130 59.91% 59.91% | 81 37.33% 97.24% | 0 0.00% 97.24% | 1 0.46% 97.70% | 3 1.38% 99.08% | 0 0.00% 99.08% | 0 0.00% 99.08% | 1 0.46% 99.54% | 1 0.46% 100.00% 58211312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr::total 217 58311312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist_seqr::bucket_size 64 58411312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist_seqr::max_bucket 639 58511390Ssteve.reinhardt@amd.comsystem.ruby.IFETCH.latency_hist_seqr::samples 5642 58611680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.latency_hist_seqr::mean 8.181850 58711680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.latency_hist_seqr::gmean 1.537199 58811680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.latency_hist_seqr::stdev 24.735651 58911680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.latency_hist_seqr | 5201 92.18% 92.18% | 409 7.25% 99.43% | 21 0.37% 99.81% | 4 0.07% 99.88% | 4 0.07% 99.95% | 3 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 59011390Ssteve.reinhardt@amd.comsystem.ruby.IFETCH.latency_hist_seqr::total 5642 59111312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 59211312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 59311390Ssteve.reinhardt@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::samples 5056 59411312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::mean 1 59511312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 59611390Ssteve.reinhardt@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5056 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 59711390Ssteve.reinhardt@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::total 5056 59811312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 59911312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 60011312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::samples 586 60111680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.miss_latency_hist_seqr::mean 70.146758 60211680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.miss_latency_hist_seqr::gmean 62.782043 60311680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.miss_latency_hist_seqr::stdev 40.099052 60411680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.miss_latency_hist_seqr | 145 24.74% 24.74% | 409 69.80% 94.54% | 21 3.58% 98.12% | 4 0.68% 98.81% | 4 0.68% 99.49% | 3 0.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 60511312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::total 586 60611312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 60711312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 60811390Ssteve.reinhardt@amd.comsystem.ruby.Directory.miss_mach_latency_hist_seqr::samples 1472 60911680SCurtis.Dunham@arm.comsystem.ruby.Directory.miss_mach_latency_hist_seqr::mean 62.663723 61011680SCurtis.Dunham@arm.comsystem.ruby.Directory.miss_mach_latency_hist_seqr::gmean 55.319189 61111680SCurtis.Dunham@arm.comsystem.ruby.Directory.miss_mach_latency_hist_seqr::stdev 37.614530 61211680SCurtis.Dunham@arm.comsystem.ruby.Directory.miss_mach_latency_hist_seqr | 577 39.20% 39.20% | 834 56.66% 95.86% | 40 2.72% 98.57% | 8 0.54% 99.12% | 8 0.54% 99.66% | 5 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 61311390Ssteve.reinhardt@amd.comsystem.ruby.Directory.miss_mach_latency_hist_seqr::total 1472 61411312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 61511312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 61611312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 61711312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan 61811312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 61911312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 62011312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 62111312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 62211312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 62311312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan 62411312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 62511312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 62611312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 62711312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 62811312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 62911312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan 63011312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 63111312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 63211312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8 63311312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 63411312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 63511312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 63611312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 63711312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan 63811312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% 63911312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 64011390Ssteve.reinhardt@amd.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 64111390Ssteve.reinhardt@amd.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 64211390Ssteve.reinhardt@amd.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 669 64311680SCurtis.Dunham@arm.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 59.352765 64411680SCurtis.Dunham@arm.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 52.447495 64511680SCurtis.Dunham@arm.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 35.144031 64611680SCurtis.Dunham@arm.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 302 45.14% 45.14% | 344 51.42% 96.56% | 15 2.24% 98.80% | 4 0.60% 99.40% | 2 0.30% 99.70% | 2 0.30% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 64711390Ssteve.reinhardt@amd.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 669 64811680SCurtis.Dunham@arm.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 64911680SCurtis.Dunham@arm.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 65011312Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 217 65111680SCurtis.Dunham@arm.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 52.663594 65211680SCurtis.Dunham@arm.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 46.326875 65311680SCurtis.Dunham@arm.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 34.272225 65411680SCurtis.Dunham@arm.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 130 59.91% 59.91% | 81 37.33% 97.24% | 0 0.00% 97.24% | 1 0.46% 97.70% | 3 1.38% 99.08% | 0 0.00% 99.08% | 0 0.00% 99.08% | 1 0.46% 99.54% | 1 0.46% 100.00% 65511312Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 217 65611312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 65711312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 65811312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 586 65911680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 70.146758 66011680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 62.782043 66111680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 40.099052 66211680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 145 24.74% 24.74% | 409 69.80% 94.54% | 21 3.58% 98.12% | 4 0.68% 98.81% | 4 0.68% 99.49% | 3 0.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 66311312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 586 66411390Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.GETX 1472 0.00% 0.00% 66511390Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.PUTX 1468 0.00% 0.00% 66611390Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.Memory_Data 1472 0.00% 0.00% 66711390Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.Memory_Ack 1468 0.00% 0.00% 66811390Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.I.GETX 1472 0.00% 0.00% 66911390Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.M.PUTX 1468 0.00% 0.00% 67011390Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.IM.Memory_Data 1472 0.00% 0.00% 67111390Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.MI.Memory_Ack 1468 0.00% 0.00% 67211390Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.Load 1135 0.00% 0.00% 67311390Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.Ifetch 5642 0.00% 0.00% 67410488Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Store 901 0.00% 0.00% 67511390Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.Data 1472 0.00% 0.00% 67611390Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.Replacement 1468 0.00% 0.00% 67711390Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.Writeback_Ack 1468 0.00% 0.00% 67811390Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.I.Load 669 0.00% 0.00% 67910488Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Ifetch 586 0.00% 0.00% 68010488Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Store 217 0.00% 0.00% 68111390Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.M.Load 466 0.00% 0.00% 68211390Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.M.Ifetch 5056 0.00% 0.00% 68310488Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Store 684 0.00% 0.00% 68411390Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.M.Replacement 1468 0.00% 0.00% 68511390Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.MI.Writeback_Ack 1468 0.00% 0.00% 68611390Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.IS.Data 1255 0.00% 0.00% 68710488Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IM.Data 217 0.00% 0.00% 6886167SN/A 6896167SN/A---------- End Simulation Statistics ---------- 690