stats.txt revision 9924
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000022 # Number of seconds simulated 4sim_ticks 21805500 # Number of ticks simulated 5final_tick 21805500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 31004 # Simulator instruction rate (inst/s) 8host_op_rate 31001 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 131093072 # Simulator tick rate (ticks/s) 10host_mem_usage 229800 # Number of bytes of host memory used 11host_seconds 0.17 # Real time elapsed on the host 12sim_insts 5156 # Number of instructions simulated 13sim_ops 5156 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory 16system.physmem.bytes_read::total 30528 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 477 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 983238174 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 416775584 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1400013758 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 983238174 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 983238174 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 983238174 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 416775584 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1400013758 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 477 # Total number of read requests accepted by DRAM controller 31system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller 32system.physmem.readBursts 477 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts 33system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts 34system.physmem.bytesRead 30528 # Total number of bytes read from memory 35system.physmem.bytesWritten 0 # Total number of bytes written to memory 36system.physmem.bytesConsumedRd 30528 # bytesRead derated as per pkt->getSize() 37system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 38system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q 39system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 40system.physmem.perBankRdReqs::0 30 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::2 1 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::4 7 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::5 3 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::6 13 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::7 54 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::8 63 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::9 77 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::10 44 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::11 20 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::12 51 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::13 29 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::14 77 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis 56system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 72system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 73system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 74system.physmem.totGap 21726000 # Total gap between requests 75system.physmem.readPktSize::0 0 # Categorize read packet sizes 76system.physmem.readPktSize::1 0 # Categorize read packet sizes 77system.physmem.readPktSize::2 0 # Categorize read packet sizes 78system.physmem.readPktSize::3 0 # Categorize read packet sizes 79system.physmem.readPktSize::4 0 # Categorize read packet sizes 80system.physmem.readPktSize::5 0 # Categorize read packet sizes 81system.physmem.readPktSize::6 477 # Categorize read packet sizes 82system.physmem.writePktSize::0 0 # Categorize write packet sizes 83system.physmem.writePktSize::1 0 # Categorize write packet sizes 84system.physmem.writePktSize::2 0 # Categorize write packet sizes 85system.physmem.writePktSize::3 0 # Categorize write packet sizes 86system.physmem.writePktSize::4 0 # Categorize write packet sizes 87system.physmem.writePktSize::5 0 # Categorize write packet sizes 88system.physmem.writePktSize::6 0 # Categorize write packet sizes 89system.physmem.rdQLenPdf::0 283 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 121system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 122system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 123system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 124system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 125system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 153system.physmem.bytesPerActivate::samples 103 # Bytes accessed per row activation 154system.physmem.bytesPerActivate::mean 241.708738 # Bytes accessed per row activation 155system.physmem.bytesPerActivate::gmean 156.390708 # Bytes accessed per row activation 156system.physmem.bytesPerActivate::stdev 303.503517 # Bytes accessed per row activation 157system.physmem.bytesPerActivate::64 39 37.86% 37.86% # Bytes accessed per row activation 158system.physmem.bytesPerActivate::128 15 14.56% 52.43% # Bytes accessed per row activation 159system.physmem.bytesPerActivate::192 16 15.53% 67.96% # Bytes accessed per row activation 160system.physmem.bytesPerActivate::256 7 6.80% 74.76% # Bytes accessed per row activation 161system.physmem.bytesPerActivate::320 8 7.77% 82.52% # Bytes accessed per row activation 162system.physmem.bytesPerActivate::384 3 2.91% 85.44% # Bytes accessed per row activation 163system.physmem.bytesPerActivate::448 3 2.91% 88.35% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::512 1 0.97% 89.32% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::576 4 3.88% 93.20% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::704 1 0.97% 94.17% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::832 2 1.94% 96.12% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::960 1 0.97% 97.09% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::1024 2 1.94% 99.03% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::2368 1 0.97% 100.00% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::total 103 # Bytes accessed per row activation 172system.physmem.totQLat 2353250 # Total cycles spent in queuing delays 173system.physmem.totMemAccLat 13414500 # Sum of mem lat for all requests 174system.physmem.totBusLat 2385000 # Total cycles spent in databus access 175system.physmem.totBankLat 8676250 # Total cycles spent in bank access 176system.physmem.avgQLat 4933.44 # Average queueing delay per request 177system.physmem.avgBankLat 18189.20 # Average bank access latency per request 178system.physmem.avgBusLat 5000.00 # Average bus latency per request 179system.physmem.avgMemAccLat 28122.64 # Average memory access latency 180system.physmem.avgRdBW 1400.01 # Average achieved read bandwidth in MB/s 181system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 182system.physmem.avgConsumedRdBW 1400.01 # Average consumed read bandwidth in MB/s 183system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 184system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 185system.physmem.busUtil 10.94 # Data bus utilization in percentage 186system.physmem.avgRdQLen 0.62 # Average read queue length over time 187system.physmem.avgWrQLen 0.00 # Average write queue length over time 188system.physmem.readRowHits 374 # Number of row buffer hits during reads 189system.physmem.writeRowHits 0 # Number of row buffer hits during writes 190system.physmem.readRowHitRate 78.41 # Row buffer hit rate for reads 191system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 192system.physmem.avgGap 45547.17 # Average gap between requests 193system.membus.throughput 1400013758 # Throughput (bytes/s) 194system.membus.trans_dist::ReadReq 426 # Transaction distribution 195system.membus.trans_dist::ReadResp 426 # Transaction distribution 196system.membus.trans_dist::ReadExReq 51 # Transaction distribution 197system.membus.trans_dist::ReadExResp 51 # Transaction distribution 198system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 954 # Packet count per connected master and slave (bytes) 199system.membus.pkt_count::total 954 # Packet count per connected master and slave (bytes) 200system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30528 # Cumulative packet size per connected master and slave (bytes) 201system.membus.tot_pkt_size::total 30528 # Cumulative packet size per connected master and slave (bytes) 202system.membus.data_through_bus 30528 # Total data (bytes) 203system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 204system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks) 205system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) 206system.membus.respLayer1.occupancy 4480000 # Layer occupancy (ticks) 207system.membus.respLayer1.utilization 20.5 # Layer utilization (%) 208system.cpu.branchPred.lookups 2187 # Number of BP lookups 209system.cpu.branchPred.condPredicted 1490 # Number of conditional branches predicted 210system.cpu.branchPred.condIncorrect 438 # Number of conditional branches incorrect 211system.cpu.branchPred.BTBLookups 1664 # Number of BTB lookups 212system.cpu.branchPred.BTBHits 502 # Number of BTB hits 213system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 214system.cpu.branchPred.BTBHitPct 30.168269 # BTB Hit Percentage 215system.cpu.branchPred.usedRAS 261 # Number of times the RAS was used to get a target. 216system.cpu.branchPred.RASInCorrect 67 # Number of incorrect RAS predictions. 217system.cpu.dtb.read_hits 0 # DTB read hits 218system.cpu.dtb.read_misses 0 # DTB read misses 219system.cpu.dtb.read_accesses 0 # DTB read accesses 220system.cpu.dtb.write_hits 0 # DTB write hits 221system.cpu.dtb.write_misses 0 # DTB write misses 222system.cpu.dtb.write_accesses 0 # DTB write accesses 223system.cpu.dtb.hits 0 # DTB hits 224system.cpu.dtb.misses 0 # DTB misses 225system.cpu.dtb.accesses 0 # DTB accesses 226system.cpu.itb.read_hits 0 # DTB read hits 227system.cpu.itb.read_misses 0 # DTB read misses 228system.cpu.itb.read_accesses 0 # DTB read accesses 229system.cpu.itb.write_hits 0 # DTB write hits 230system.cpu.itb.write_misses 0 # DTB write misses 231system.cpu.itb.write_accesses 0 # DTB write accesses 232system.cpu.itb.hits 0 # DTB hits 233system.cpu.itb.misses 0 # DTB misses 234system.cpu.itb.accesses 0 # DTB accesses 235system.cpu.workload.num_syscalls 8 # Number of system calls 236system.cpu.numCycles 43612 # number of cpu cycles simulated 237system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 238system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 239system.cpu.fetch.icacheStallCycles 8859 # Number of cycles fetch is stalled on an Icache miss 240system.cpu.fetch.Insts 13212 # Number of instructions fetch has processed 241system.cpu.fetch.Branches 2187 # Number of branches that fetch encountered 242system.cpu.fetch.predictedBranches 763 # Number of branches that fetch has predicted taken 243system.cpu.fetch.Cycles 3230 # Number of cycles fetch has run and was not squashing or blocked 244system.cpu.fetch.SquashCycles 1384 # Number of cycles fetch has spent squashing 245system.cpu.fetch.BlockedCycles 1326 # Number of cycles fetch has spent blocked 246system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps 247system.cpu.fetch.CacheLines 1985 # Number of cache lines fetched 248system.cpu.fetch.IcacheSquashes 280 # Number of outstanding Icache misses that were squashed 249system.cpu.fetch.rateDist::samples 14475 # Number of instructions fetched each cycle (Total) 250system.cpu.fetch.rateDist::mean 0.912746 # Number of instructions fetched each cycle (Total) 251system.cpu.fetch.rateDist::stdev 2.223376 # Number of instructions fetched each cycle (Total) 252system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 253system.cpu.fetch.rateDist::0 11245 77.69% 77.69% # Number of instructions fetched each cycle (Total) 254system.cpu.fetch.rateDist::1 1331 9.20% 86.88% # Number of instructions fetched each cycle (Total) 255system.cpu.fetch.rateDist::2 104 0.72% 87.60% # Number of instructions fetched each cycle (Total) 256system.cpu.fetch.rateDist::3 131 0.91% 88.50% # Number of instructions fetched each cycle (Total) 257system.cpu.fetch.rateDist::4 305 2.11% 90.61% # Number of instructions fetched each cycle (Total) 258system.cpu.fetch.rateDist::5 118 0.82% 91.43% # Number of instructions fetched each cycle (Total) 259system.cpu.fetch.rateDist::6 150 1.04% 92.46% # Number of instructions fetched each cycle (Total) 260system.cpu.fetch.rateDist::7 158 1.09% 93.55% # Number of instructions fetched each cycle (Total) 261system.cpu.fetch.rateDist::8 933 6.45% 100.00% # Number of instructions fetched each cycle (Total) 262system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 263system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 264system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 265system.cpu.fetch.rateDist::total 14475 # Number of instructions fetched each cycle (Total) 266system.cpu.fetch.branchRate 0.050147 # Number of branch fetches per cycle 267system.cpu.fetch.rate 0.302944 # Number of inst fetches per cycle 268system.cpu.decode.IdleCycles 8926 # Number of cycles decode is idle 269system.cpu.decode.BlockedCycles 1578 # Number of cycles decode is blocked 270system.cpu.decode.RunCycles 3043 # Number of cycles decode is running 271system.cpu.decode.UnblockCycles 53 # Number of cycles decode is unblocking 272system.cpu.decode.SquashCycles 875 # Number of cycles decode is squashing 273system.cpu.decode.BranchResolved 167 # Number of times decode resolved a branch 274system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction 275system.cpu.decode.DecodedInsts 12329 # Number of instructions handled by decode 276system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode 277system.cpu.rename.SquashCycles 875 # Number of cycles rename is squashing 278system.cpu.rename.IdleCycles 9108 # Number of cycles rename is idle 279system.cpu.rename.BlockCycles 527 # Number of cycles rename is blocking 280system.cpu.rename.serializeStallCycles 901 # count of cycles rename stalled for serializing inst 281system.cpu.rename.RunCycles 2916 # Number of cycles rename is running 282system.cpu.rename.UnblockCycles 148 # Number of cycles rename is unblocking 283system.cpu.rename.RenamedInsts 11899 # Number of instructions processed by rename 284system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full 285system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full 286system.cpu.rename.LSQFullEvents 124 # Number of times rename has blocked due to LSQ full 287system.cpu.rename.RenamedOperands 7186 # Number of destination operands rename has renamed 288system.cpu.rename.RenameLookups 14116 # Number of register rename lookups that rename has made 289system.cpu.rename.int_rename_lookups 13887 # Number of integer rename lookups 290system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups 291system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed 292system.cpu.rename.UndoneMaps 3788 # Number of HB maps that are undone due to squashing 293system.cpu.rename.serializingInsts 16 # count of serializing insts renamed 294system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed 295system.cpu.rename.skidInsts 328 # count of insts added to the skid buffer 296system.cpu.memDep0.insertedLoads 2460 # Number of loads inserted to the mem dependence unit. 297system.cpu.memDep0.insertedStores 1193 # Number of stores inserted to the mem dependence unit. 298system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 299system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. 300system.cpu.iq.iqInstsAdded 9226 # Number of instructions added to the IQ (excludes non-spec) 301system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ 302system.cpu.iq.iqInstsIssued 8306 # Number of instructions issued 303system.cpu.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued 304system.cpu.iq.iqSquashedInstsExamined 3428 # Number of squashed instructions iterated over during squash; mainly for profiling 305system.cpu.iq.iqSquashedOperandsExamined 2082 # Number of squashed operands that are examined and possibly removed from graph 306system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed 307system.cpu.iq.issued_per_cycle::samples 14475 # Number of insts issued each cycle 308system.cpu.iq.issued_per_cycle::mean 0.573817 # Number of insts issued each cycle 309system.cpu.iq.issued_per_cycle::stdev 1.241522 # Number of insts issued each cycle 310system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 311system.cpu.iq.issued_per_cycle::0 10881 75.17% 75.17% # Number of insts issued each cycle 312system.cpu.iq.issued_per_cycle::1 1431 9.89% 85.06% # Number of insts issued each cycle 313system.cpu.iq.issued_per_cycle::2 893 6.17% 91.23% # Number of insts issued each cycle 314system.cpu.iq.issued_per_cycle::3 553 3.82% 95.05% # Number of insts issued each cycle 315system.cpu.iq.issued_per_cycle::4 356 2.46% 97.51% # Number of insts issued each cycle 316system.cpu.iq.issued_per_cycle::5 225 1.55% 99.06% # Number of insts issued each cycle 317system.cpu.iq.issued_per_cycle::6 88 0.61% 99.67% # Number of insts issued each cycle 318system.cpu.iq.issued_per_cycle::7 31 0.21% 99.88% # Number of insts issued each cycle 319system.cpu.iq.issued_per_cycle::8 17 0.12% 100.00% # Number of insts issued each cycle 320system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 321system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 322system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 323system.cpu.iq.issued_per_cycle::total 14475 # Number of insts issued each cycle 324system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 325system.cpu.iq.fu_full::IntAlu 5 3.12% 3.12% # attempts to use FU when none available 326system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available 327system.cpu.iq.fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available 328system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available 329system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.12% # attempts to use FU when none available 330system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.12% # attempts to use FU when none available 331system.cpu.iq.fu_full::FloatMult 0 0.00% 3.12% # attempts to use FU when none available 332system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.12% # attempts to use FU when none available 333system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.12% # attempts to use FU when none available 334system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.12% # attempts to use FU when none available 335system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.12% # attempts to use FU when none available 336system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.12% # attempts to use FU when none available 337system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.12% # attempts to use FU when none available 338system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.12% # attempts to use FU when none available 339system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.12% # attempts to use FU when none available 340system.cpu.iq.fu_full::SimdMult 0 0.00% 3.12% # attempts to use FU when none available 341system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.12% # attempts to use FU when none available 342system.cpu.iq.fu_full::SimdShift 0 0.00% 3.12% # attempts to use FU when none available 343system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.12% # attempts to use FU when none available 344system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.12% # attempts to use FU when none available 345system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.12% # attempts to use FU when none available 346system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.12% # attempts to use FU when none available 347system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.12% # attempts to use FU when none available 348system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.12% # attempts to use FU when none available 349system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.12% # attempts to use FU when none available 350system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.12% # attempts to use FU when none available 351system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available 352system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available 353system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available 354system.cpu.iq.fu_full::MemRead 101 63.12% 66.25% # attempts to use FU when none available 355system.cpu.iq.fu_full::MemWrite 54 33.75% 100.00% # attempts to use FU when none available 356system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 357system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 358system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 359system.cpu.iq.FU_type_0::IntAlu 4943 59.51% 59.51% # Type of FU issued 360system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.57% # Type of FU issued 361system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.60% # Type of FU issued 362system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.62% # Type of FU issued 363system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.62% # Type of FU issued 364system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.62% # Type of FU issued 365system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.62% # Type of FU issued 366system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.62% # Type of FU issued 367system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.62% # Type of FU issued 368system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.62% # Type of FU issued 369system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.62% # Type of FU issued 370system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.62% # Type of FU issued 371system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.62% # Type of FU issued 372system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.62% # Type of FU issued 373system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.62% # Type of FU issued 374system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.62% # Type of FU issued 375system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.62% # Type of FU issued 376system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.62% # Type of FU issued 377system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.62% # Type of FU issued 378system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.62% # Type of FU issued 379system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.62% # Type of FU issued 380system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.62% # Type of FU issued 381system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.62% # Type of FU issued 382system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.62% # Type of FU issued 383system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.62% # Type of FU issued 384system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.62% # Type of FU issued 385system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.62% # Type of FU issued 386system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.62% # Type of FU issued 387system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.62% # Type of FU issued 388system.cpu.iq.FU_type_0::MemRead 2250 27.09% 86.71% # Type of FU issued 389system.cpu.iq.FU_type_0::MemWrite 1104 13.29% 100.00% # Type of FU issued 390system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 391system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 392system.cpu.iq.FU_type_0::total 8306 # Type of FU issued 393system.cpu.iq.rate 0.190452 # Inst issue rate 394system.cpu.iq.fu_busy_cnt 160 # FU busy when requested 395system.cpu.iq.fu_busy_rate 0.019263 # FU busy rate (busy events/executed inst) 396system.cpu.iq.int_inst_queue_reads 31282 # Number of integer instruction queue reads 397system.cpu.iq.int_inst_queue_writes 12675 # Number of integer instruction queue writes 398system.cpu.iq.int_inst_queue_wakeup_accesses 7463 # Number of integer instruction queue wakeup accesses 399system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads 400system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 401system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses 402system.cpu.iq.int_alu_accesses 8464 # Number of integer alu accesses 403system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses 404system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores 405system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 406system.cpu.iew.lsq.thread0.squashedLoads 1297 # Number of loads squashed 407system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed 408system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations 409system.cpu.iew.lsq.thread0.squashedStores 268 # Number of stores squashed 410system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 411system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 412system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 413system.cpu.iew.lsq.thread0.cacheBlocked 35 # Number of times an access to memory failed due to the cache being blocked 414system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 415system.cpu.iew.iewSquashCycles 875 # Number of cycles IEW is squashing 416system.cpu.iew.iewBlockCycles 349 # Number of cycles IEW is blocking 417system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking 418system.cpu.iew.iewDispatchedInsts 10763 # Number of instructions dispatched to IQ 419system.cpu.iew.iewDispSquashedInsts 93 # Number of squashed instructions skipped by dispatch 420system.cpu.iew.iewDispLoadInsts 2460 # Number of dispatched load instructions 421system.cpu.iew.iewDispStoreInsts 1193 # Number of dispatched store instructions 422system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions 423system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall 424system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 425system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations 426system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly 427system.cpu.iew.predictedNotTakenIncorrect 362 # Number of branches that were predicted not taken incorrectly 428system.cpu.iew.branchMispredicts 463 # Number of branch mispredicts detected at execute 429system.cpu.iew.iewExecutedInsts 7925 # Number of executed instructions 430system.cpu.iew.iewExecLoadInsts 2110 # Number of load instructions executed 431system.cpu.iew.iewExecSquashedInsts 381 # Number of squashed instructions skipped in execute 432system.cpu.iew.exec_swp 0 # number of swp insts executed 433system.cpu.iew.exec_nop 1525 # number of nop insts executed 434system.cpu.iew.exec_refs 3189 # number of memory reference insts executed 435system.cpu.iew.exec_branches 1354 # Number of branches executed 436system.cpu.iew.exec_stores 1079 # Number of stores executed 437system.cpu.iew.exec_rate 0.181716 # Inst execution rate 438system.cpu.iew.wb_sent 7555 # cumulative count of insts sent to commit 439system.cpu.iew.wb_count 7465 # cumulative count of insts written-back 440system.cpu.iew.wb_producers 2921 # num instructions producing a value 441system.cpu.iew.wb_consumers 4197 # num instructions consuming a value 442system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 443system.cpu.iew.wb_rate 0.171168 # insts written-back per cycle 444system.cpu.iew.wb_fanout 0.695973 # average fanout of values written-back 445system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 446system.cpu.commit.commitSquashedInsts 4943 # The number of squashed insts skipped by commit 447system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards 448system.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted 449system.cpu.commit.committed_per_cycle::samples 13600 # Number of insts commited each cycle 450system.cpu.commit.committed_per_cycle::mean 0.427426 # Number of insts commited each cycle 451system.cpu.commit.committed_per_cycle::stdev 1.207995 # Number of insts commited each cycle 452system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 453system.cpu.commit.committed_per_cycle::0 11198 82.34% 82.34% # Number of insts commited each cycle 454system.cpu.commit.committed_per_cycle::1 999 7.35% 89.68% # Number of insts commited each cycle 455system.cpu.commit.committed_per_cycle::2 630 4.63% 94.32% # Number of insts commited each cycle 456system.cpu.commit.committed_per_cycle::3 315 2.32% 96.63% # Number of insts commited each cycle 457system.cpu.commit.committed_per_cycle::4 149 1.10% 97.73% # Number of insts commited each cycle 458system.cpu.commit.committed_per_cycle::5 94 0.69% 98.42% # Number of insts commited each cycle 459system.cpu.commit.committed_per_cycle::6 68 0.50% 98.92% # Number of insts commited each cycle 460system.cpu.commit.committed_per_cycle::7 41 0.30% 99.22% # Number of insts commited each cycle 461system.cpu.commit.committed_per_cycle::8 106 0.78% 100.00% # Number of insts commited each cycle 462system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 463system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 464system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 465system.cpu.commit.committed_per_cycle::total 13600 # Number of insts commited each cycle 466system.cpu.commit.committedInsts 5813 # Number of instructions committed 467system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed 468system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 469system.cpu.commit.refs 2088 # Number of memory references committed 470system.cpu.commit.loads 1163 # Number of loads committed 471system.cpu.commit.membars 0 # Number of memory barriers committed 472system.cpu.commit.branches 915 # Number of branches committed 473system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. 474system.cpu.commit.int_insts 5111 # Number of committed integer instructions. 475system.cpu.commit.function_calls 87 # Number of function calls committed. 476system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached 477system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 478system.cpu.rob.rob_reads 24237 # The number of ROB reads 479system.cpu.rob.rob_writes 22398 # The number of ROB writes 480system.cpu.timesIdled 285 # Number of times that the entire CPU went into an idle state and unscheduled itself 481system.cpu.idleCycles 29137 # Total number of cycles that the CPU has spent unscheduled due to idling 482system.cpu.committedInsts 5156 # Number of Instructions Simulated 483system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated 484system.cpu.committedInsts_total 5156 # Number of Instructions Simulated 485system.cpu.cpi 8.458495 # CPI: Cycles Per Instruction 486system.cpu.cpi_total 8.458495 # CPI: Total CPI of All Threads 487system.cpu.ipc 0.118224 # IPC: Instructions Per Cycle 488system.cpu.ipc_total 0.118224 # IPC: Total IPC of All Threads 489system.cpu.int_regfile_reads 10746 # number of integer regfile reads 490system.cpu.int_regfile_writes 5233 # number of integer regfile writes 491system.cpu.fp_regfile_reads 3 # number of floating regfile reads 492system.cpu.fp_regfile_writes 1 # number of floating regfile writes 493system.cpu.misc_regfile_reads 148 # number of misc regfile reads 494system.cpu.toL2Bus.throughput 1408818876 # Throughput (bytes/s) 495system.cpu.toL2Bus.trans_dist::ReadReq 429 # Transaction distribution 496system.cpu.toL2Bus.trans_dist::ReadResp 429 # Transaction distribution 497system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution 498system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution 499system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 676 # Packet count per connected master and slave (bytes) 500system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes) 501system.cpu.toL2Bus.pkt_count::total 960 # Packet count per connected master and slave (bytes) 502system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21632 # Cumulative packet size per connected master and slave (bytes) 503system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) 504system.cpu.toL2Bus.tot_pkt_size::total 30720 # Cumulative packet size per connected master and slave (bytes) 505system.cpu.toL2Bus.data_through_bus 30720 # Total data (bytes) 506system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 507system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks) 508system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 509system.cpu.toL2Bus.respLayer0.occupancy 573500 # Layer occupancy (ticks) 510system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) 511system.cpu.toL2Bus.respLayer1.occupancy 230000 # Layer occupancy (ticks) 512system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) 513system.cpu.icache.tags.replacements 17 # number of replacements 514system.cpu.icache.tags.tagsinuse 160.845390 # Cycle average of tags in use 515system.cpu.icache.tags.total_refs 1531 # Total number of references to valid blocks. 516system.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks. 517system.cpu.icache.tags.avg_refs 4.529586 # Average number of references to valid blocks. 518system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 519system.cpu.icache.tags.occ_blocks::cpu.inst 160.845390 # Average occupied blocks per requestor 520system.cpu.icache.tags.occ_percent::cpu.inst 0.078538 # Average percentage of cache occupancy 521system.cpu.icache.tags.occ_percent::total 0.078538 # Average percentage of cache occupancy 522system.cpu.icache.ReadReq_hits::cpu.inst 1531 # number of ReadReq hits 523system.cpu.icache.ReadReq_hits::total 1531 # number of ReadReq hits 524system.cpu.icache.demand_hits::cpu.inst 1531 # number of demand (read+write) hits 525system.cpu.icache.demand_hits::total 1531 # number of demand (read+write) hits 526system.cpu.icache.overall_hits::cpu.inst 1531 # number of overall hits 527system.cpu.icache.overall_hits::total 1531 # number of overall hits 528system.cpu.icache.ReadReq_misses::cpu.inst 454 # number of ReadReq misses 529system.cpu.icache.ReadReq_misses::total 454 # number of ReadReq misses 530system.cpu.icache.demand_misses::cpu.inst 454 # number of demand (read+write) misses 531system.cpu.icache.demand_misses::total 454 # number of demand (read+write) misses 532system.cpu.icache.overall_misses::cpu.inst 454 # number of overall misses 533system.cpu.icache.overall_misses::total 454 # number of overall misses 534system.cpu.icache.ReadReq_miss_latency::cpu.inst 31019250 # number of ReadReq miss cycles 535system.cpu.icache.ReadReq_miss_latency::total 31019250 # number of ReadReq miss cycles 536system.cpu.icache.demand_miss_latency::cpu.inst 31019250 # number of demand (read+write) miss cycles 537system.cpu.icache.demand_miss_latency::total 31019250 # number of demand (read+write) miss cycles 538system.cpu.icache.overall_miss_latency::cpu.inst 31019250 # number of overall miss cycles 539system.cpu.icache.overall_miss_latency::total 31019250 # number of overall miss cycles 540system.cpu.icache.ReadReq_accesses::cpu.inst 1985 # number of ReadReq accesses(hits+misses) 541system.cpu.icache.ReadReq_accesses::total 1985 # number of ReadReq accesses(hits+misses) 542system.cpu.icache.demand_accesses::cpu.inst 1985 # number of demand (read+write) accesses 543system.cpu.icache.demand_accesses::total 1985 # number of demand (read+write) accesses 544system.cpu.icache.overall_accesses::cpu.inst 1985 # number of overall (read+write) accesses 545system.cpu.icache.overall_accesses::total 1985 # number of overall (read+write) accesses 546system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.228715 # miss rate for ReadReq accesses 547system.cpu.icache.ReadReq_miss_rate::total 0.228715 # miss rate for ReadReq accesses 548system.cpu.icache.demand_miss_rate::cpu.inst 0.228715 # miss rate for demand accesses 549system.cpu.icache.demand_miss_rate::total 0.228715 # miss rate for demand accesses 550system.cpu.icache.overall_miss_rate::cpu.inst 0.228715 # miss rate for overall accesses 551system.cpu.icache.overall_miss_rate::total 0.228715 # miss rate for overall accesses 552system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68324.339207 # average ReadReq miss latency 553system.cpu.icache.ReadReq_avg_miss_latency::total 68324.339207 # average ReadReq miss latency 554system.cpu.icache.demand_avg_miss_latency::cpu.inst 68324.339207 # average overall miss latency 555system.cpu.icache.demand_avg_miss_latency::total 68324.339207 # average overall miss latency 556system.cpu.icache.overall_avg_miss_latency::cpu.inst 68324.339207 # average overall miss latency 557system.cpu.icache.overall_avg_miss_latency::total 68324.339207 # average overall miss latency 558system.cpu.icache.blocked_cycles::no_mshrs 47 # number of cycles access was blocked 559system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 560system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked 561system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 562system.cpu.icache.avg_blocked_cycles::no_mshrs 47 # average number of cycles each access was blocked 563system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 564system.cpu.icache.fast_writes 0 # number of fast writes performed 565system.cpu.icache.cache_copies 0 # number of cache copies performed 566system.cpu.icache.ReadReq_mshr_hits::cpu.inst 116 # number of ReadReq MSHR hits 567system.cpu.icache.ReadReq_mshr_hits::total 116 # number of ReadReq MSHR hits 568system.cpu.icache.demand_mshr_hits::cpu.inst 116 # number of demand (read+write) MSHR hits 569system.cpu.icache.demand_mshr_hits::total 116 # number of demand (read+write) MSHR hits 570system.cpu.icache.overall_mshr_hits::cpu.inst 116 # number of overall MSHR hits 571system.cpu.icache.overall_mshr_hits::total 116 # number of overall MSHR hits 572system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses 573system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses 574system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses 575system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses 576system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses 577system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses 578system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23858000 # number of ReadReq MSHR miss cycles 579system.cpu.icache.ReadReq_mshr_miss_latency::total 23858000 # number of ReadReq MSHR miss cycles 580system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23858000 # number of demand (read+write) MSHR miss cycles 581system.cpu.icache.demand_mshr_miss_latency::total 23858000 # number of demand (read+write) MSHR miss cycles 582system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23858000 # number of overall MSHR miss cycles 583system.cpu.icache.overall_mshr_miss_latency::total 23858000 # number of overall MSHR miss cycles 584system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.170277 # mshr miss rate for ReadReq accesses 585system.cpu.icache.ReadReq_mshr_miss_rate::total 0.170277 # mshr miss rate for ReadReq accesses 586system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.170277 # mshr miss rate for demand accesses 587system.cpu.icache.demand_mshr_miss_rate::total 0.170277 # mshr miss rate for demand accesses 588system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.170277 # mshr miss rate for overall accesses 589system.cpu.icache.overall_mshr_miss_rate::total 0.170277 # mshr miss rate for overall accesses 590system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70585.798817 # average ReadReq mshr miss latency 591system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70585.798817 # average ReadReq mshr miss latency 592system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70585.798817 # average overall mshr miss latency 593system.cpu.icache.demand_avg_mshr_miss_latency::total 70585.798817 # average overall mshr miss latency 594system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70585.798817 # average overall mshr miss latency 595system.cpu.icache.overall_avg_mshr_miss_latency::total 70585.798817 # average overall mshr miss latency 596system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 597system.cpu.l2cache.tags.replacements 0 # number of replacements 598system.cpu.l2cache.tags.tagsinuse 220.792115 # Cycle average of tags in use 599system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. 600system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks. 601system.cpu.l2cache.tags.avg_refs 0.007042 # Average number of references to valid blocks. 602system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 603system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.133804 # Average occupied blocks per requestor 604system.cpu.l2cache.tags.occ_blocks::cpu.data 57.658310 # Average occupied blocks per requestor 605system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004978 # Average percentage of cache occupancy 606system.cpu.l2cache.tags.occ_percent::cpu.data 0.001760 # Average percentage of cache occupancy 607system.cpu.l2cache.tags.occ_percent::total 0.006738 # Average percentage of cache occupancy 608system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits 609system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits 610system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 611system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 612system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 613system.cpu.l2cache.overall_hits::total 3 # number of overall hits 614system.cpu.l2cache.ReadReq_misses::cpu.inst 335 # number of ReadReq misses 615system.cpu.l2cache.ReadReq_misses::cpu.data 91 # number of ReadReq misses 616system.cpu.l2cache.ReadReq_misses::total 426 # number of ReadReq misses 617system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses 618system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses 619system.cpu.l2cache.demand_misses::cpu.inst 335 # number of demand (read+write) misses 620system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses 621system.cpu.l2cache.demand_misses::total 477 # number of demand (read+write) misses 622system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses 623system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses 624system.cpu.l2cache.overall_misses::total 477 # number of overall misses 625system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23490000 # number of ReadReq miss cycles 626system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7101750 # number of ReadReq miss cycles 627system.cpu.l2cache.ReadReq_miss_latency::total 30591750 # number of ReadReq miss cycles 628system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3862250 # number of ReadExReq miss cycles 629system.cpu.l2cache.ReadExReq_miss_latency::total 3862250 # number of ReadExReq miss cycles 630system.cpu.l2cache.demand_miss_latency::cpu.inst 23490000 # number of demand (read+write) miss cycles 631system.cpu.l2cache.demand_miss_latency::cpu.data 10964000 # number of demand (read+write) miss cycles 632system.cpu.l2cache.demand_miss_latency::total 34454000 # number of demand (read+write) miss cycles 633system.cpu.l2cache.overall_miss_latency::cpu.inst 23490000 # number of overall miss cycles 634system.cpu.l2cache.overall_miss_latency::cpu.data 10964000 # number of overall miss cycles 635system.cpu.l2cache.overall_miss_latency::total 34454000 # number of overall miss cycles 636system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses) 637system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) 638system.cpu.l2cache.ReadReq_accesses::total 429 # number of ReadReq accesses(hits+misses) 639system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) 640system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) 641system.cpu.l2cache.demand_accesses::cpu.inst 338 # number of demand (read+write) accesses 642system.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses 643system.cpu.l2cache.demand_accesses::total 480 # number of demand (read+write) accesses 644system.cpu.l2cache.overall_accesses::cpu.inst 338 # number of overall (read+write) accesses 645system.cpu.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses 646system.cpu.l2cache.overall_accesses::total 480 # number of overall (read+write) accesses 647system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991124 # miss rate for ReadReq accesses 648system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 649system.cpu.l2cache.ReadReq_miss_rate::total 0.993007 # miss rate for ReadReq accesses 650system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 651system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 652system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991124 # miss rate for demand accesses 653system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 654system.cpu.l2cache.demand_miss_rate::total 0.993750 # miss rate for demand accesses 655system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991124 # miss rate for overall accesses 656system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 657system.cpu.l2cache.overall_miss_rate::total 0.993750 # miss rate for overall accesses 658system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70119.402985 # average ReadReq miss latency 659system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78041.208791 # average ReadReq miss latency 660system.cpu.l2cache.ReadReq_avg_miss_latency::total 71811.619718 # average ReadReq miss latency 661system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75730.392157 # average ReadExReq miss latency 662system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75730.392157 # average ReadExReq miss latency 663system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70119.402985 # average overall miss latency 664system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77211.267606 # average overall miss latency 665system.cpu.l2cache.demand_avg_miss_latency::total 72230.607966 # average overall miss latency 666system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70119.402985 # average overall miss latency 667system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77211.267606 # average overall miss latency 668system.cpu.l2cache.overall_avg_miss_latency::total 72230.607966 # average overall miss latency 669system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 670system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 671system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 672system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 673system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 674system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 675system.cpu.l2cache.fast_writes 0 # number of fast writes performed 676system.cpu.l2cache.cache_copies 0 # number of cache copies performed 677system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 335 # number of ReadReq MSHR misses 678system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 679system.cpu.l2cache.ReadReq_mshr_misses::total 426 # number of ReadReq MSHR misses 680system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses 681system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses 682system.cpu.l2cache.demand_mshr_misses::cpu.inst 335 # number of demand (read+write) MSHR misses 683system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 684system.cpu.l2cache.demand_mshr_misses::total 477 # number of demand (read+write) MSHR misses 685system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses 686system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 687system.cpu.l2cache.overall_mshr_misses::total 477 # number of overall MSHR misses 688system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19249000 # number of ReadReq MSHR miss cycles 689system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5981750 # number of ReadReq MSHR miss cycles 690system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25230750 # number of ReadReq MSHR miss cycles 691system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3228750 # number of ReadExReq MSHR miss cycles 692system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3228750 # number of ReadExReq MSHR miss cycles 693system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19249000 # number of demand (read+write) MSHR miss cycles 694system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9210500 # number of demand (read+write) MSHR miss cycles 695system.cpu.l2cache.demand_mshr_miss_latency::total 28459500 # number of demand (read+write) MSHR miss cycles 696system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19249000 # number of overall MSHR miss cycles 697system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9210500 # number of overall MSHR miss cycles 698system.cpu.l2cache.overall_mshr_miss_latency::total 28459500 # number of overall MSHR miss cycles 699system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for ReadReq accesses 700system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 701system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993007 # mshr miss rate for ReadReq accesses 702system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 703system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 704system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for demand accesses 705system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 706system.cpu.l2cache.demand_mshr_miss_rate::total 0.993750 # mshr miss rate for demand accesses 707system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for overall accesses 708system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 709system.cpu.l2cache.overall_mshr_miss_rate::total 0.993750 # mshr miss rate for overall accesses 710system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57459.701493 # average ReadReq mshr miss latency 711system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65733.516484 # average ReadReq mshr miss latency 712system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59227.112676 # average ReadReq mshr miss latency 713system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63308.823529 # average ReadExReq mshr miss latency 714system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63308.823529 # average ReadExReq mshr miss latency 715system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57459.701493 # average overall mshr miss latency 716system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64862.676056 # average overall mshr miss latency 717system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59663.522013 # average overall mshr miss latency 718system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57459.701493 # average overall mshr miss latency 719system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64862.676056 # average overall mshr miss latency 720system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59663.522013 # average overall mshr miss latency 721system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 722system.cpu.dcache.tags.replacements 0 # number of replacements 723system.cpu.dcache.tags.tagsinuse 91.308892 # Cycle average of tags in use 724system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. 725system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. 726system.cpu.dcache.tags.avg_refs 16.866197 # Average number of references to valid blocks. 727system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 728system.cpu.dcache.tags.occ_blocks::cpu.data 91.308892 # Average occupied blocks per requestor 729system.cpu.dcache.tags.occ_percent::cpu.data 0.022292 # Average percentage of cache occupancy 730system.cpu.dcache.tags.occ_percent::total 0.022292 # Average percentage of cache occupancy 731system.cpu.dcache.ReadReq_hits::cpu.data 1832 # number of ReadReq hits 732system.cpu.dcache.ReadReq_hits::total 1832 # number of ReadReq hits 733system.cpu.dcache.WriteReq_hits::cpu.data 563 # number of WriteReq hits 734system.cpu.dcache.WriteReq_hits::total 563 # number of WriteReq hits 735system.cpu.dcache.demand_hits::cpu.data 2395 # number of demand (read+write) hits 736system.cpu.dcache.demand_hits::total 2395 # number of demand (read+write) hits 737system.cpu.dcache.overall_hits::cpu.data 2395 # number of overall hits 738system.cpu.dcache.overall_hits::total 2395 # number of overall hits 739system.cpu.dcache.ReadReq_misses::cpu.data 148 # number of ReadReq misses 740system.cpu.dcache.ReadReq_misses::total 148 # number of ReadReq misses 741system.cpu.dcache.WriteReq_misses::cpu.data 362 # number of WriteReq misses 742system.cpu.dcache.WriteReq_misses::total 362 # number of WriteReq misses 743system.cpu.dcache.demand_misses::cpu.data 510 # number of demand (read+write) misses 744system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses 745system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses 746system.cpu.dcache.overall_misses::total 510 # number of overall misses 747system.cpu.dcache.ReadReq_miss_latency::cpu.data 10243000 # number of ReadReq miss cycles 748system.cpu.dcache.ReadReq_miss_latency::total 10243000 # number of ReadReq miss cycles 749system.cpu.dcache.WriteReq_miss_latency::cpu.data 22828749 # number of WriteReq miss cycles 750system.cpu.dcache.WriteReq_miss_latency::total 22828749 # number of WriteReq miss cycles 751system.cpu.dcache.demand_miss_latency::cpu.data 33071749 # number of demand (read+write) miss cycles 752system.cpu.dcache.demand_miss_latency::total 33071749 # number of demand (read+write) miss cycles 753system.cpu.dcache.overall_miss_latency::cpu.data 33071749 # number of overall miss cycles 754system.cpu.dcache.overall_miss_latency::total 33071749 # number of overall miss cycles 755system.cpu.dcache.ReadReq_accesses::cpu.data 1980 # number of ReadReq accesses(hits+misses) 756system.cpu.dcache.ReadReq_accesses::total 1980 # number of ReadReq accesses(hits+misses) 757system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 758system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 759system.cpu.dcache.demand_accesses::cpu.data 2905 # number of demand (read+write) accesses 760system.cpu.dcache.demand_accesses::total 2905 # number of demand (read+write) accesses 761system.cpu.dcache.overall_accesses::cpu.data 2905 # number of overall (read+write) accesses 762system.cpu.dcache.overall_accesses::total 2905 # number of overall (read+write) accesses 763system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074747 # miss rate for ReadReq accesses 764system.cpu.dcache.ReadReq_miss_rate::total 0.074747 # miss rate for ReadReq accesses 765system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.391351 # miss rate for WriteReq accesses 766system.cpu.dcache.WriteReq_miss_rate::total 0.391351 # miss rate for WriteReq accesses 767system.cpu.dcache.demand_miss_rate::cpu.data 0.175559 # miss rate for demand accesses 768system.cpu.dcache.demand_miss_rate::total 0.175559 # miss rate for demand accesses 769system.cpu.dcache.overall_miss_rate::cpu.data 0.175559 # miss rate for overall accesses 770system.cpu.dcache.overall_miss_rate::total 0.175559 # miss rate for overall accesses 771system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69209.459459 # average ReadReq miss latency 772system.cpu.dcache.ReadReq_avg_miss_latency::total 69209.459459 # average ReadReq miss latency 773system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63062.842541 # average WriteReq miss latency 774system.cpu.dcache.WriteReq_avg_miss_latency::total 63062.842541 # average WriteReq miss latency 775system.cpu.dcache.demand_avg_miss_latency::cpu.data 64846.566667 # average overall miss latency 776system.cpu.dcache.demand_avg_miss_latency::total 64846.566667 # average overall miss latency 777system.cpu.dcache.overall_avg_miss_latency::cpu.data 64846.566667 # average overall miss latency 778system.cpu.dcache.overall_avg_miss_latency::total 64846.566667 # average overall miss latency 779system.cpu.dcache.blocked_cycles::no_mshrs 635 # number of cycles access was blocked 780system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 781system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked 782system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 783system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.727273 # average number of cycles each access was blocked 784system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 785system.cpu.dcache.fast_writes 0 # number of fast writes performed 786system.cpu.dcache.cache_copies 0 # number of cache copies performed 787system.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits 788system.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits 789system.cpu.dcache.WriteReq_mshr_hits::cpu.data 311 # number of WriteReq MSHR hits 790system.cpu.dcache.WriteReq_mshr_hits::total 311 # number of WriteReq MSHR hits 791system.cpu.dcache.demand_mshr_hits::cpu.data 368 # number of demand (read+write) MSHR hits 792system.cpu.dcache.demand_mshr_hits::total 368 # number of demand (read+write) MSHR hits 793system.cpu.dcache.overall_mshr_hits::cpu.data 368 # number of overall MSHR hits 794system.cpu.dcache.overall_mshr_hits::total 368 # number of overall MSHR hits 795system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 796system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses 797system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses 798system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses 799system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 800system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses 801system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 802system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses 803system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7196250 # number of ReadReq MSHR miss cycles 804system.cpu.dcache.ReadReq_mshr_miss_latency::total 7196250 # number of ReadReq MSHR miss cycles 805system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3914249 # number of WriteReq MSHR miss cycles 806system.cpu.dcache.WriteReq_mshr_miss_latency::total 3914249 # number of WriteReq MSHR miss cycles 807system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11110499 # number of demand (read+write) MSHR miss cycles 808system.cpu.dcache.demand_mshr_miss_latency::total 11110499 # number of demand (read+write) MSHR miss cycles 809system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11110499 # number of overall MSHR miss cycles 810system.cpu.dcache.overall_mshr_miss_latency::total 11110499 # number of overall MSHR miss cycles 811system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045960 # mshr miss rate for ReadReq accesses 812system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045960 # mshr miss rate for ReadReq accesses 813system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses 814system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses 815system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for demand accesses 816system.cpu.dcache.demand_mshr_miss_rate::total 0.048881 # mshr miss rate for demand accesses 817system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for overall accesses 818system.cpu.dcache.overall_mshr_miss_rate::total 0.048881 # mshr miss rate for overall accesses 819system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79079.670330 # average ReadReq mshr miss latency 820system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79079.670330 # average ReadReq mshr miss latency 821system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76749.980392 # average WriteReq mshr miss latency 822system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76749.980392 # average WriteReq mshr miss latency 823system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78242.950704 # average overall mshr miss latency 824system.cpu.dcache.demand_avg_mshr_miss_latency::total 78242.950704 # average overall mshr miss latency 825system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78242.950704 # average overall mshr miss latency 826system.cpu.dcache.overall_avg_mshr_miss_latency::total 78242.950704 # average overall mshr miss latency 827system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 828 829---------- End Simulation Statistics ---------- 830