stats.txt revision 9312
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000012 # Number of seconds simulated 4sim_ticks 12097500 # Number of ticks simulated 5final_tick 12097500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 46391 # Simulator instruction rate (inst/s) 8host_op_rate 46381 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 108798708 # Simulator tick rate (ticks/s) 10host_mem_usage 217720 # Number of bytes of host memory used 11host_seconds 0.11 # Real time elapsed on the host 12sim_insts 5156 # Number of instructions simulated 13sim_ops 5156 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 21696 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory 16system.physmem.bytes_read::total 30720 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 21696 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 21696 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 339 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 480 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1793428394 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 745939244 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 2539367638 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1793428394 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1793428394 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1793428394 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 745939244 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 2539367638 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 480 # Total number of read requests seen 31system.physmem.writeReqs 0 # Total number of write requests seen 32system.physmem.cpureqs 480 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 30720 # Total number of bytes read from memory 34system.physmem.bytesWritten 0 # Total number of bytes written to memory 35system.physmem.bytesConsumedRd 30720 # bytesRead derated as per pkt->getSize() 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 39system.physmem.perBankRdReqs::0 64 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 30 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 23 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 54 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 6 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 39 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 20 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 40 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 18 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 15 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 17 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 40 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 52 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 32 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 30 # Track reads on a per bank basis 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 73system.physmem.totGap 12035000 # Total gap between requests 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 480 # Categorize read packet sizes 81system.physmem.readPktSize::7 0 # Categorize read packet sizes 82system.physmem.readPktSize::8 0 # Categorize read packet sizes 83system.physmem.writePktSize::0 0 # categorize write packet sizes 84system.physmem.writePktSize::1 0 # categorize write packet sizes 85system.physmem.writePktSize::2 0 # categorize write packet sizes 86system.physmem.writePktSize::3 0 # categorize write packet sizes 87system.physmem.writePktSize::4 0 # categorize write packet sizes 88system.physmem.writePktSize::5 0 # categorize write packet sizes 89system.physmem.writePktSize::6 0 # categorize write packet sizes 90system.physmem.writePktSize::7 0 # categorize write packet sizes 91system.physmem.writePktSize::8 0 # categorize write packet sizes 92system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 93system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 94system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 95system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 96system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 97system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 98system.physmem.neitherpktsize::6 0 # categorize neither packet sizes 99system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 100system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 101system.physmem.rdQLenPdf::0 253 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 148 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 134system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 167system.physmem.totQLat 3039980 # Total cycles spent in queuing delays 168system.physmem.totMemAccLat 13667980 # Sum of mem lat for all requests 169system.physmem.totBusLat 1920000 # Total cycles spent in databus access 170system.physmem.totBankLat 8708000 # Total cycles spent in bank access 171system.physmem.avgQLat 6333.29 # Average queueing delay per request 172system.physmem.avgBankLat 18141.67 # Average bank access latency per request 173system.physmem.avgBusLat 4000.00 # Average bus latency per request 174system.physmem.avgMemAccLat 28474.96 # Average memory access latency 175system.physmem.avgRdBW 2539.37 # Average achieved read bandwidth in MB/s 176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 177system.physmem.avgConsumedRdBW 2539.37 # Average consumed read bandwidth in MB/s 178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 179system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 180system.physmem.busUtil 15.87 # Data bus utilization in percentage 181system.physmem.avgRdQLen 1.13 # Average read queue length over time 182system.physmem.avgWrQLen 0.00 # Average write queue length over time 183system.physmem.readRowHits 380 # Number of row buffer hits during reads 184system.physmem.writeRowHits 0 # Number of row buffer hits during writes 185system.physmem.readRowHitRate 79.17 # Row buffer hit rate for reads 186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 187system.physmem.avgGap 25072.92 # Average gap between requests 188system.cpu.dtb.read_hits 0 # DTB read hits 189system.cpu.dtb.read_misses 0 # DTB read misses 190system.cpu.dtb.read_accesses 0 # DTB read accesses 191system.cpu.dtb.write_hits 0 # DTB write hits 192system.cpu.dtb.write_misses 0 # DTB write misses 193system.cpu.dtb.write_accesses 0 # DTB write accesses 194system.cpu.dtb.hits 0 # DTB hits 195system.cpu.dtb.misses 0 # DTB misses 196system.cpu.dtb.accesses 0 # DTB accesses 197system.cpu.itb.read_hits 0 # DTB read hits 198system.cpu.itb.read_misses 0 # DTB read misses 199system.cpu.itb.read_accesses 0 # DTB read accesses 200system.cpu.itb.write_hits 0 # DTB write hits 201system.cpu.itb.write_misses 0 # DTB write misses 202system.cpu.itb.write_accesses 0 # DTB write accesses 203system.cpu.itb.hits 0 # DTB hits 204system.cpu.itb.misses 0 # DTB misses 205system.cpu.itb.accesses 0 # DTB accesses 206system.cpu.workload.num_syscalls 8 # Number of system calls 207system.cpu.numCycles 24196 # number of cpu cycles simulated 208system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 209system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 210system.cpu.BPredUnit.lookups 2174 # Number of BP lookups 211system.cpu.BPredUnit.condPredicted 1443 # Number of conditional branches predicted 212system.cpu.BPredUnit.condIncorrect 447 # Number of conditional branches incorrect 213system.cpu.BPredUnit.BTBLookups 1705 # Number of BTB lookups 214system.cpu.BPredUnit.BTBHits 494 # Number of BTB hits 215system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 216system.cpu.BPredUnit.usedRAS 283 # Number of times the RAS was used to get a target. 217system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. 218system.cpu.fetch.icacheStallCycles 8516 # Number of cycles fetch is stalled on an Icache miss 219system.cpu.fetch.Insts 13177 # Number of instructions fetch has processed 220system.cpu.fetch.Branches 2174 # Number of branches that fetch encountered 221system.cpu.fetch.predictedBranches 777 # Number of branches that fetch has predicted taken 222system.cpu.fetch.Cycles 3260 # Number of cycles fetch has run and was not squashing or blocked 223system.cpu.fetch.SquashCycles 1345 # Number of cycles fetch has spent squashing 224system.cpu.fetch.BlockedCycles 699 # Number of cycles fetch has spent blocked 225system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 226system.cpu.fetch.PendingTrapStallCycles 157 # Number of stall cycles due to pending traps 227system.cpu.fetch.CacheLines 1979 # Number of cache lines fetched 228system.cpu.fetch.IcacheSquashes 260 # Number of outstanding Icache misses that were squashed 229system.cpu.fetch.rateDist::samples 13523 # Number of instructions fetched each cycle (Total) 230system.cpu.fetch.rateDist::mean 0.974414 # Number of instructions fetched each cycle (Total) 231system.cpu.fetch.rateDist::stdev 2.279455 # Number of instructions fetched each cycle (Total) 232system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 233system.cpu.fetch.rateDist::0 10263 75.89% 75.89% # Number of instructions fetched each cycle (Total) 234system.cpu.fetch.rateDist::1 1359 10.05% 85.94% # Number of instructions fetched each cycle (Total) 235system.cpu.fetch.rateDist::2 113 0.84% 86.78% # Number of instructions fetched each cycle (Total) 236system.cpu.fetch.rateDist::3 150 1.11% 87.89% # Number of instructions fetched each cycle (Total) 237system.cpu.fetch.rateDist::4 301 2.23% 90.11% # Number of instructions fetched each cycle (Total) 238system.cpu.fetch.rateDist::5 101 0.75% 90.86% # Number of instructions fetched each cycle (Total) 239system.cpu.fetch.rateDist::6 159 1.18% 92.04% # Number of instructions fetched each cycle (Total) 240system.cpu.fetch.rateDist::7 137 1.01% 93.05% # Number of instructions fetched each cycle (Total) 241system.cpu.fetch.rateDist::8 940 6.95% 100.00% # Number of instructions fetched each cycle (Total) 242system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 243system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 244system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 245system.cpu.fetch.rateDist::total 13523 # Number of instructions fetched each cycle (Total) 246system.cpu.fetch.branchRate 0.089850 # Number of branch fetches per cycle 247system.cpu.fetch.rate 0.544594 # Number of inst fetches per cycle 248system.cpu.decode.IdleCycles 8657 # Number of cycles decode is idle 249system.cpu.decode.BlockedCycles 898 # Number of cycles decode is blocked 250system.cpu.decode.RunCycles 3079 # Number of cycles decode is running 251system.cpu.decode.UnblockCycles 45 # Number of cycles decode is unblocking 252system.cpu.decode.SquashCycles 844 # Number of cycles decode is squashing 253system.cpu.decode.BranchResolved 154 # Number of times decode resolved a branch 254system.cpu.decode.BranchMispred 47 # Number of times decode detected a branch misprediction 255system.cpu.decode.DecodedInsts 12246 # Number of instructions handled by decode 256system.cpu.decode.SquashedInsts 178 # Number of squashed instructions handled by decode 257system.cpu.rename.SquashCycles 844 # Number of cycles rename is squashing 258system.cpu.rename.IdleCycles 8855 # Number of cycles rename is idle 259system.cpu.rename.BlockCycles 196 # Number of cycles rename is blocking 260system.cpu.rename.serializeStallCycles 599 # count of cycles rename stalled for serializing inst 261system.cpu.rename.RunCycles 2928 # Number of cycles rename is running 262system.cpu.rename.UnblockCycles 101 # Number of cycles rename is unblocking 263system.cpu.rename.RenamedInsts 11668 # Number of instructions processed by rename 264system.cpu.rename.LSQFullEvents 92 # Number of times rename has blocked due to LSQ full 265system.cpu.rename.RenamedOperands 7112 # Number of destination operands rename has renamed 266system.cpu.rename.RenameLookups 13873 # Number of register rename lookups that rename has made 267system.cpu.rename.int_rename_lookups 13869 # Number of integer rename lookups 268system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups 269system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed 270system.cpu.rename.UndoneMaps 3714 # Number of HB maps that are undone due to squashing 271system.cpu.rename.serializingInsts 18 # count of serializing insts renamed 272system.cpu.rename.tempSerializingInsts 12 # count of temporary serializing insts renamed 273system.cpu.rename.skidInsts 271 # count of insts added to the skid buffer 274system.cpu.memDep0.insertedLoads 2456 # Number of loads inserted to the mem dependence unit. 275system.cpu.memDep0.insertedStores 1189 # Number of stores inserted to the mem dependence unit. 276system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 277system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. 278system.cpu.iq.iqInstsAdded 9092 # Number of instructions added to the IQ (excludes non-spec) 279system.cpu.iq.iqNonSpecInstsAdded 14 # Number of non-speculative instructions added to the IQ 280system.cpu.iq.iqInstsIssued 8231 # Number of instructions issued 281system.cpu.iq.iqSquashedInstsIssued 55 # Number of squashed instructions issued 282system.cpu.iq.iqSquashedInstsExamined 3471 # Number of squashed instructions iterated over during squash; mainly for profiling 283system.cpu.iq.iqSquashedOperandsExamined 1958 # Number of squashed operands that are examined and possibly removed from graph 284system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed 285system.cpu.iq.issued_per_cycle::samples 13523 # Number of insts issued each cycle 286system.cpu.iq.issued_per_cycle::mean 0.608667 # Number of insts issued each cycle 287system.cpu.iq.issued_per_cycle::stdev 1.271089 # Number of insts issued each cycle 288system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 289system.cpu.iq.issued_per_cycle::0 9982 73.81% 73.81% # Number of insts issued each cycle 290system.cpu.iq.issued_per_cycle::1 1399 10.35% 84.16% # Number of insts issued each cycle 291system.cpu.iq.issued_per_cycle::2 867 6.41% 90.57% # Number of insts issued each cycle 292system.cpu.iq.issued_per_cycle::3 551 4.07% 94.65% # Number of insts issued each cycle 293system.cpu.iq.issued_per_cycle::4 358 2.65% 97.29% # Number of insts issued each cycle 294system.cpu.iq.issued_per_cycle::5 239 1.77% 99.06% # Number of insts issued each cycle 295system.cpu.iq.issued_per_cycle::6 85 0.63% 99.69% # Number of insts issued each cycle 296system.cpu.iq.issued_per_cycle::7 28 0.21% 99.90% # Number of insts issued each cycle 297system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle 298system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 299system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 300system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 301system.cpu.iq.issued_per_cycle::total 13523 # Number of insts issued each cycle 302system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 303system.cpu.iq.fu_full::IntAlu 3 2.00% 2.00% # attempts to use FU when none available 304system.cpu.iq.fu_full::IntMult 0 0.00% 2.00% # attempts to use FU when none available 305system.cpu.iq.fu_full::IntDiv 0 0.00% 2.00% # attempts to use FU when none available 306system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.00% # attempts to use FU when none available 307system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.00% # attempts to use FU when none available 308system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.00% # attempts to use FU when none available 309system.cpu.iq.fu_full::FloatMult 0 0.00% 2.00% # attempts to use FU when none available 310system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.00% # attempts to use FU when none available 311system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.00% # attempts to use FU when none available 312system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.00% # attempts to use FU when none available 313system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.00% # attempts to use FU when none available 314system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.00% # attempts to use FU when none available 315system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.00% # attempts to use FU when none available 316system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.00% # attempts to use FU when none available 317system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.00% # attempts to use FU when none available 318system.cpu.iq.fu_full::SimdMult 0 0.00% 2.00% # attempts to use FU when none available 319system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.00% # attempts to use FU when none available 320system.cpu.iq.fu_full::SimdShift 0 0.00% 2.00% # attempts to use FU when none available 321system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.00% # attempts to use FU when none available 322system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.00% # attempts to use FU when none available 323system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.00% # attempts to use FU when none available 324system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.00% # attempts to use FU when none available 325system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.00% # attempts to use FU when none available 326system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.00% # attempts to use FU when none available 327system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.00% # attempts to use FU when none available 328system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.00% # attempts to use FU when none available 329system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.00% # attempts to use FU when none available 330system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.00% # attempts to use FU when none available 331system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.00% # attempts to use FU when none available 332system.cpu.iq.fu_full::MemRead 95 63.33% 65.33% # attempts to use FU when none available 333system.cpu.iq.fu_full::MemWrite 52 34.67% 100.00% # attempts to use FU when none available 334system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 335system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 336system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 337system.cpu.iq.FU_type_0::IntAlu 4866 59.12% 59.12% # Type of FU issued 338system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.18% # Type of FU issued 339system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.20% # Type of FU issued 340system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.23% # Type of FU issued 341system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.23% # Type of FU issued 342system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.23% # Type of FU issued 343system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.23% # Type of FU issued 344system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.23% # Type of FU issued 345system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.23% # Type of FU issued 346system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.23% # Type of FU issued 347system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.23% # Type of FU issued 348system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.23% # Type of FU issued 349system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.23% # Type of FU issued 350system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.23% # Type of FU issued 351system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.23% # Type of FU issued 352system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.23% # Type of FU issued 353system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.23% # Type of FU issued 354system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.23% # Type of FU issued 355system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.23% # Type of FU issued 356system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.23% # Type of FU issued 357system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.23% # Type of FU issued 358system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.23% # Type of FU issued 359system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.23% # Type of FU issued 360system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.23% # Type of FU issued 361system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.23% # Type of FU issued 362system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.23% # Type of FU issued 363system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.23% # Type of FU issued 364system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.23% # Type of FU issued 365system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.23% # Type of FU issued 366system.cpu.iq.FU_type_0::MemRead 2254 27.38% 86.61% # Type of FU issued 367system.cpu.iq.FU_type_0::MemWrite 1102 13.39% 100.00% # Type of FU issued 368system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 369system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 370system.cpu.iq.FU_type_0::total 8231 # Type of FU issued 371system.cpu.iq.rate 0.340180 # Inst issue rate 372system.cpu.iq.fu_busy_cnt 150 # FU busy when requested 373system.cpu.iq.fu_busy_rate 0.018224 # FU busy rate (busy events/executed inst) 374system.cpu.iq.int_inst_queue_reads 30186 # Number of integer instruction queue reads 375system.cpu.iq.int_inst_queue_writes 12584 # Number of integer instruction queue writes 376system.cpu.iq.int_inst_queue_wakeup_accesses 7378 # Number of integer instruction queue wakeup accesses 377system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads 378system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 379system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses 380system.cpu.iq.int_alu_accesses 8379 # Number of integer alu accesses 381system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses 382system.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores 383system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 384system.cpu.iew.lsq.thread0.squashedLoads 1293 # Number of loads squashed 385system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 386system.cpu.iew.lsq.thread0.memOrderViolation 9 # Number of memory ordering violations 387system.cpu.iew.lsq.thread0.squashedStores 264 # Number of stores squashed 388system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 389system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 390system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 391system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 392system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 393system.cpu.iew.iewSquashCycles 844 # Number of cycles IEW is squashing 394system.cpu.iew.iewBlockCycles 139 # Number of cycles IEW is blocking 395system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking 396system.cpu.iew.iewDispatchedInsts 10561 # Number of instructions dispatched to IQ 397system.cpu.iew.iewDispSquashedInsts 111 # Number of squashed instructions skipped by dispatch 398system.cpu.iew.iewDispLoadInsts 2456 # Number of dispatched load instructions 399system.cpu.iew.iewDispStoreInsts 1189 # Number of dispatched store instructions 400system.cpu.iew.iewDispNonSpecInsts 14 # Number of dispatched non-speculative instructions 401system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall 402system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall 403system.cpu.iew.memOrderViolationEvents 9 # Number of memory order violations 404system.cpu.iew.predictedTakenIncorrect 110 # Number of branches that were predicted taken incorrectly 405system.cpu.iew.predictedNotTakenIncorrect 364 # Number of branches that were predicted not taken incorrectly 406system.cpu.iew.branchMispredicts 474 # Number of branch mispredicts detected at execute 407system.cpu.iew.iewExecutedInsts 7823 # Number of executed instructions 408system.cpu.iew.iewExecLoadInsts 2103 # Number of load instructions executed 409system.cpu.iew.iewExecSquashedInsts 408 # Number of squashed instructions skipped in execute 410system.cpu.iew.exec_swp 0 # number of swp insts executed 411system.cpu.iew.exec_nop 1455 # number of nop insts executed 412system.cpu.iew.exec_refs 3177 # number of memory reference insts executed 413system.cpu.iew.exec_branches 1335 # Number of branches executed 414system.cpu.iew.exec_stores 1074 # Number of stores executed 415system.cpu.iew.exec_rate 0.323318 # Inst execution rate 416system.cpu.iew.wb_sent 7479 # cumulative count of insts sent to commit 417system.cpu.iew.wb_count 7380 # cumulative count of insts written-back 418system.cpu.iew.wb_producers 2890 # num instructions producing a value 419system.cpu.iew.wb_consumers 4129 # num instructions consuming a value 420system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 421system.cpu.iew.wb_rate 0.305009 # insts written-back per cycle 422system.cpu.iew.wb_fanout 0.699927 # average fanout of values written-back 423system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 424system.cpu.commit.commitSquashedInsts 4740 # The number of squashed insts skipped by commit 425system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards 426system.cpu.commit.branchMispredicts 401 # The number of times a branch was mispredicted 427system.cpu.commit.committed_per_cycle::samples 12679 # Number of insts commited each cycle 428system.cpu.commit.committed_per_cycle::mean 0.458475 # Number of insts commited each cycle 429system.cpu.commit.committed_per_cycle::stdev 1.250836 # Number of insts commited each cycle 430system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 431system.cpu.commit.committed_per_cycle::0 10300 81.24% 81.24% # Number of insts commited each cycle 432system.cpu.commit.committed_per_cycle::1 973 7.67% 88.91% # Number of insts commited each cycle 433system.cpu.commit.committed_per_cycle::2 629 4.96% 93.87% # Number of insts commited each cycle 434system.cpu.commit.committed_per_cycle::3 317 2.50% 96.37% # Number of insts commited each cycle 435system.cpu.commit.committed_per_cycle::4 148 1.17% 97.54% # Number of insts commited each cycle 436system.cpu.commit.committed_per_cycle::5 88 0.69% 98.23% # Number of insts commited each cycle 437system.cpu.commit.committed_per_cycle::6 75 0.59% 98.82% # Number of insts commited each cycle 438system.cpu.commit.committed_per_cycle::7 43 0.34% 99.16% # Number of insts commited each cycle 439system.cpu.commit.committed_per_cycle::8 106 0.84% 100.00% # Number of insts commited each cycle 440system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 441system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 442system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 443system.cpu.commit.committed_per_cycle::total 12679 # Number of insts commited each cycle 444system.cpu.commit.committedInsts 5813 # Number of instructions committed 445system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed 446system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 447system.cpu.commit.refs 2088 # Number of memory references committed 448system.cpu.commit.loads 1163 # Number of loads committed 449system.cpu.commit.membars 0 # Number of memory barriers committed 450system.cpu.commit.branches 915 # Number of branches committed 451system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. 452system.cpu.commit.int_insts 5111 # Number of committed integer instructions. 453system.cpu.commit.function_calls 87 # Number of function calls committed. 454system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached 455system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 456system.cpu.rob.rob_reads 23113 # The number of ROB reads 457system.cpu.rob.rob_writes 21959 # The number of ROB writes 458system.cpu.timesIdled 270 # Number of times that the entire CPU went into an idle state and unscheduled itself 459system.cpu.idleCycles 10673 # Total number of cycles that the CPU has spent unscheduled due to idling 460system.cpu.committedInsts 5156 # Number of Instructions Simulated 461system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated 462system.cpu.committedInsts_total 5156 # Number of Instructions Simulated 463system.cpu.cpi 4.692785 # CPI: Cycles Per Instruction 464system.cpu.cpi_total 4.692785 # CPI: Total CPI of All Threads 465system.cpu.ipc 0.213093 # IPC: Instructions Per Cycle 466system.cpu.ipc_total 0.213093 # IPC: Total IPC of All Threads 467system.cpu.int_regfile_reads 10646 # number of integer regfile reads 468system.cpu.int_regfile_writes 5184 # number of integer regfile writes 469system.cpu.fp_regfile_reads 3 # number of floating regfile reads 470system.cpu.fp_regfile_writes 1 # number of floating regfile writes 471system.cpu.misc_regfile_reads 155 # number of misc regfile reads 472system.cpu.icache.replacements 17 # number of replacements 473system.cpu.icache.tagsinuse 162.253661 # Cycle average of tags in use 474system.cpu.icache.total_refs 1552 # Total number of references to valid blocks. 475system.cpu.icache.sampled_refs 342 # Sample count of references to valid blocks. 476system.cpu.icache.avg_refs 4.538012 # Average number of references to valid blocks. 477system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 478system.cpu.icache.occ_blocks::cpu.inst 162.253661 # Average occupied blocks per requestor 479system.cpu.icache.occ_percent::cpu.inst 0.079225 # Average percentage of cache occupancy 480system.cpu.icache.occ_percent::total 0.079225 # Average percentage of cache occupancy 481system.cpu.icache.ReadReq_hits::cpu.inst 1552 # number of ReadReq hits 482system.cpu.icache.ReadReq_hits::total 1552 # number of ReadReq hits 483system.cpu.icache.demand_hits::cpu.inst 1552 # number of demand (read+write) hits 484system.cpu.icache.demand_hits::total 1552 # number of demand (read+write) hits 485system.cpu.icache.overall_hits::cpu.inst 1552 # number of overall hits 486system.cpu.icache.overall_hits::total 1552 # number of overall hits 487system.cpu.icache.ReadReq_misses::cpu.inst 427 # number of ReadReq misses 488system.cpu.icache.ReadReq_misses::total 427 # number of ReadReq misses 489system.cpu.icache.demand_misses::cpu.inst 427 # number of demand (read+write) misses 490system.cpu.icache.demand_misses::total 427 # number of demand (read+write) misses 491system.cpu.icache.overall_misses::cpu.inst 427 # number of overall misses 492system.cpu.icache.overall_misses::total 427 # number of overall misses 493system.cpu.icache.ReadReq_miss_latency::cpu.inst 14343000 # number of ReadReq miss cycles 494system.cpu.icache.ReadReq_miss_latency::total 14343000 # number of ReadReq miss cycles 495system.cpu.icache.demand_miss_latency::cpu.inst 14343000 # number of demand (read+write) miss cycles 496system.cpu.icache.demand_miss_latency::total 14343000 # number of demand (read+write) miss cycles 497system.cpu.icache.overall_miss_latency::cpu.inst 14343000 # number of overall miss cycles 498system.cpu.icache.overall_miss_latency::total 14343000 # number of overall miss cycles 499system.cpu.icache.ReadReq_accesses::cpu.inst 1979 # number of ReadReq accesses(hits+misses) 500system.cpu.icache.ReadReq_accesses::total 1979 # number of ReadReq accesses(hits+misses) 501system.cpu.icache.demand_accesses::cpu.inst 1979 # number of demand (read+write) accesses 502system.cpu.icache.demand_accesses::total 1979 # number of demand (read+write) accesses 503system.cpu.icache.overall_accesses::cpu.inst 1979 # number of overall (read+write) accesses 504system.cpu.icache.overall_accesses::total 1979 # number of overall (read+write) accesses 505system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.215766 # miss rate for ReadReq accesses 506system.cpu.icache.ReadReq_miss_rate::total 0.215766 # miss rate for ReadReq accesses 507system.cpu.icache.demand_miss_rate::cpu.inst 0.215766 # miss rate for demand accesses 508system.cpu.icache.demand_miss_rate::total 0.215766 # miss rate for demand accesses 509system.cpu.icache.overall_miss_rate::cpu.inst 0.215766 # miss rate for overall accesses 510system.cpu.icache.overall_miss_rate::total 0.215766 # miss rate for overall accesses 511system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33590.163934 # average ReadReq miss latency 512system.cpu.icache.ReadReq_avg_miss_latency::total 33590.163934 # average ReadReq miss latency 513system.cpu.icache.demand_avg_miss_latency::cpu.inst 33590.163934 # average overall miss latency 514system.cpu.icache.demand_avg_miss_latency::total 33590.163934 # average overall miss latency 515system.cpu.icache.overall_avg_miss_latency::cpu.inst 33590.163934 # average overall miss latency 516system.cpu.icache.overall_avg_miss_latency::total 33590.163934 # average overall miss latency 517system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 518system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 519system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 520system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 521system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 522system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 523system.cpu.icache.fast_writes 0 # number of fast writes performed 524system.cpu.icache.cache_copies 0 # number of cache copies performed 525system.cpu.icache.ReadReq_mshr_hits::cpu.inst 85 # number of ReadReq MSHR hits 526system.cpu.icache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits 527system.cpu.icache.demand_mshr_hits::cpu.inst 85 # number of demand (read+write) MSHR hits 528system.cpu.icache.demand_mshr_hits::total 85 # number of demand (read+write) MSHR hits 529system.cpu.icache.overall_mshr_hits::cpu.inst 85 # number of overall MSHR hits 530system.cpu.icache.overall_mshr_hits::total 85 # number of overall MSHR hits 531system.cpu.icache.ReadReq_mshr_misses::cpu.inst 342 # number of ReadReq MSHR misses 532system.cpu.icache.ReadReq_mshr_misses::total 342 # number of ReadReq MSHR misses 533system.cpu.icache.demand_mshr_misses::cpu.inst 342 # number of demand (read+write) MSHR misses 534system.cpu.icache.demand_mshr_misses::total 342 # number of demand (read+write) MSHR misses 535system.cpu.icache.overall_mshr_misses::cpu.inst 342 # number of overall MSHR misses 536system.cpu.icache.overall_mshr_misses::total 342 # number of overall MSHR misses 537system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11802500 # number of ReadReq MSHR miss cycles 538system.cpu.icache.ReadReq_mshr_miss_latency::total 11802500 # number of ReadReq MSHR miss cycles 539system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11802500 # number of demand (read+write) MSHR miss cycles 540system.cpu.icache.demand_mshr_miss_latency::total 11802500 # number of demand (read+write) MSHR miss cycles 541system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11802500 # number of overall MSHR miss cycles 542system.cpu.icache.overall_mshr_miss_latency::total 11802500 # number of overall MSHR miss cycles 543system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.172815 # mshr miss rate for ReadReq accesses 544system.cpu.icache.ReadReq_mshr_miss_rate::total 0.172815 # mshr miss rate for ReadReq accesses 545system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.172815 # mshr miss rate for demand accesses 546system.cpu.icache.demand_mshr_miss_rate::total 0.172815 # mshr miss rate for demand accesses 547system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.172815 # mshr miss rate for overall accesses 548system.cpu.icache.overall_mshr_miss_rate::total 0.172815 # mshr miss rate for overall accesses 549system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34510.233918 # average ReadReq mshr miss latency 550system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34510.233918 # average ReadReq mshr miss latency 551system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34510.233918 # average overall mshr miss latency 552system.cpu.icache.demand_avg_mshr_miss_latency::total 34510.233918 # average overall mshr miss latency 553system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34510.233918 # average overall mshr miss latency 554system.cpu.icache.overall_avg_mshr_miss_latency::total 34510.233918 # average overall mshr miss latency 555system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 556system.cpu.dcache.replacements 0 # number of replacements 557system.cpu.dcache.tagsinuse 91.817694 # Cycle average of tags in use 558system.cpu.dcache.total_refs 2445 # Total number of references to valid blocks. 559system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. 560system.cpu.dcache.avg_refs 17.340426 # Average number of references to valid blocks. 561system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 562system.cpu.dcache.occ_blocks::cpu.data 91.817694 # Average occupied blocks per requestor 563system.cpu.dcache.occ_percent::cpu.data 0.022416 # Average percentage of cache occupancy 564system.cpu.dcache.occ_percent::total 0.022416 # Average percentage of cache occupancy 565system.cpu.dcache.ReadReq_hits::cpu.data 1868 # number of ReadReq hits 566system.cpu.dcache.ReadReq_hits::total 1868 # number of ReadReq hits 567system.cpu.dcache.WriteReq_hits::cpu.data 577 # number of WriteReq hits 568system.cpu.dcache.WriteReq_hits::total 577 # number of WriteReq hits 569system.cpu.dcache.demand_hits::cpu.data 2445 # number of demand (read+write) hits 570system.cpu.dcache.demand_hits::total 2445 # number of demand (read+write) hits 571system.cpu.dcache.overall_hits::cpu.data 2445 # number of overall hits 572system.cpu.dcache.overall_hits::total 2445 # number of overall hits 573system.cpu.dcache.ReadReq_misses::cpu.data 149 # number of ReadReq misses 574system.cpu.dcache.ReadReq_misses::total 149 # number of ReadReq misses 575system.cpu.dcache.WriteReq_misses::cpu.data 348 # number of WriteReq misses 576system.cpu.dcache.WriteReq_misses::total 348 # number of WriteReq misses 577system.cpu.dcache.demand_misses::cpu.data 497 # number of demand (read+write) misses 578system.cpu.dcache.demand_misses::total 497 # number of demand (read+write) misses 579system.cpu.dcache.overall_misses::cpu.data 497 # number of overall misses 580system.cpu.dcache.overall_misses::total 497 # number of overall misses 581system.cpu.dcache.ReadReq_miss_latency::cpu.data 5916000 # number of ReadReq miss cycles 582system.cpu.dcache.ReadReq_miss_latency::total 5916000 # number of ReadReq miss cycles 583system.cpu.dcache.WriteReq_miss_latency::cpu.data 9509000 # number of WriteReq miss cycles 584system.cpu.dcache.WriteReq_miss_latency::total 9509000 # number of WriteReq miss cycles 585system.cpu.dcache.demand_miss_latency::cpu.data 15425000 # number of demand (read+write) miss cycles 586system.cpu.dcache.demand_miss_latency::total 15425000 # number of demand (read+write) miss cycles 587system.cpu.dcache.overall_miss_latency::cpu.data 15425000 # number of overall miss cycles 588system.cpu.dcache.overall_miss_latency::total 15425000 # number of overall miss cycles 589system.cpu.dcache.ReadReq_accesses::cpu.data 2017 # number of ReadReq accesses(hits+misses) 590system.cpu.dcache.ReadReq_accesses::total 2017 # number of ReadReq accesses(hits+misses) 591system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 592system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 593system.cpu.dcache.demand_accesses::cpu.data 2942 # number of demand (read+write) accesses 594system.cpu.dcache.demand_accesses::total 2942 # number of demand (read+write) accesses 595system.cpu.dcache.overall_accesses::cpu.data 2942 # number of overall (read+write) accesses 596system.cpu.dcache.overall_accesses::total 2942 # number of overall (read+write) accesses 597system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.073872 # miss rate for ReadReq accesses 598system.cpu.dcache.ReadReq_miss_rate::total 0.073872 # miss rate for ReadReq accesses 599system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.376216 # miss rate for WriteReq accesses 600system.cpu.dcache.WriteReq_miss_rate::total 0.376216 # miss rate for WriteReq accesses 601system.cpu.dcache.demand_miss_rate::cpu.data 0.168933 # miss rate for demand accesses 602system.cpu.dcache.demand_miss_rate::total 0.168933 # miss rate for demand accesses 603system.cpu.dcache.overall_miss_rate::cpu.data 0.168933 # miss rate for overall accesses 604system.cpu.dcache.overall_miss_rate::total 0.168933 # miss rate for overall accesses 605system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39704.697987 # average ReadReq miss latency 606system.cpu.dcache.ReadReq_avg_miss_latency::total 39704.697987 # average ReadReq miss latency 607system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27324.712644 # average WriteReq miss latency 608system.cpu.dcache.WriteReq_avg_miss_latency::total 27324.712644 # average WriteReq miss latency 609system.cpu.dcache.demand_avg_miss_latency::cpu.data 31036.217304 # average overall miss latency 610system.cpu.dcache.demand_avg_miss_latency::total 31036.217304 # average overall miss latency 611system.cpu.dcache.overall_avg_miss_latency::cpu.data 31036.217304 # average overall miss latency 612system.cpu.dcache.overall_avg_miss_latency::total 31036.217304 # average overall miss latency 613system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 614system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 615system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 616system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 617system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 618system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 619system.cpu.dcache.fast_writes 0 # number of fast writes performed 620system.cpu.dcache.cache_copies 0 # number of cache copies performed 621system.cpu.dcache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits 622system.cpu.dcache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits 623system.cpu.dcache.WriteReq_mshr_hits::cpu.data 297 # number of WriteReq MSHR hits 624system.cpu.dcache.WriteReq_mshr_hits::total 297 # number of WriteReq MSHR hits 625system.cpu.dcache.demand_mshr_hits::cpu.data 356 # number of demand (read+write) MSHR hits 626system.cpu.dcache.demand_mshr_hits::total 356 # number of demand (read+write) MSHR hits 627system.cpu.dcache.overall_mshr_hits::cpu.data 356 # number of overall MSHR hits 628system.cpu.dcache.overall_mshr_hits::total 356 # number of overall MSHR hits 629system.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses 630system.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses 631system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses 632system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses 633system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 634system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses 635system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 636system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses 637system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3832000 # number of ReadReq MSHR miss cycles 638system.cpu.dcache.ReadReq_mshr_miss_latency::total 3832000 # number of ReadReq MSHR miss cycles 639system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1859000 # number of WriteReq MSHR miss cycles 640system.cpu.dcache.WriteReq_mshr_miss_latency::total 1859000 # number of WriteReq MSHR miss cycles 641system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5691000 # number of demand (read+write) MSHR miss cycles 642system.cpu.dcache.demand_mshr_miss_latency::total 5691000 # number of demand (read+write) MSHR miss cycles 643system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5691000 # number of overall MSHR miss cycles 644system.cpu.dcache.overall_mshr_miss_latency::total 5691000 # number of overall MSHR miss cycles 645system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044621 # mshr miss rate for ReadReq accesses 646system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044621 # mshr miss rate for ReadReq accesses 647system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses 648system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses 649system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.047927 # mshr miss rate for demand accesses 650system.cpu.dcache.demand_mshr_miss_rate::total 0.047927 # mshr miss rate for demand accesses 651system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.047927 # mshr miss rate for overall accesses 652system.cpu.dcache.overall_mshr_miss_rate::total 0.047927 # mshr miss rate for overall accesses 653system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 42577.777778 # average ReadReq mshr miss latency 654system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 42577.777778 # average ReadReq mshr miss latency 655system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36450.980392 # average WriteReq mshr miss latency 656system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36450.980392 # average WriteReq mshr miss latency 657system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 40361.702128 # average overall mshr miss latency 658system.cpu.dcache.demand_avg_mshr_miss_latency::total 40361.702128 # average overall mshr miss latency 659system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 40361.702128 # average overall mshr miss latency 660system.cpu.dcache.overall_avg_mshr_miss_latency::total 40361.702128 # average overall mshr miss latency 661system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 662system.cpu.l2cache.replacements 0 # number of replacements 663system.cpu.l2cache.tagsinuse 222.617700 # Cycle average of tags in use 664system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. 665system.cpu.l2cache.sampled_refs 429 # Sample count of references to valid blocks. 666system.cpu.l2cache.avg_refs 0.006993 # Average number of references to valid blocks. 667system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 668system.cpu.l2cache.occ_blocks::cpu.inst 164.369429 # Average occupied blocks per requestor 669system.cpu.l2cache.occ_blocks::cpu.data 58.248271 # Average occupied blocks per requestor 670system.cpu.l2cache.occ_percent::cpu.inst 0.005016 # Average percentage of cache occupancy 671system.cpu.l2cache.occ_percent::cpu.data 0.001778 # Average percentage of cache occupancy 672system.cpu.l2cache.occ_percent::total 0.006794 # Average percentage of cache occupancy 673system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits 674system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits 675system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 676system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 677system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 678system.cpu.l2cache.overall_hits::total 3 # number of overall hits 679system.cpu.l2cache.ReadReq_misses::cpu.inst 339 # number of ReadReq misses 680system.cpu.l2cache.ReadReq_misses::cpu.data 90 # number of ReadReq misses 681system.cpu.l2cache.ReadReq_misses::total 429 # number of ReadReq misses 682system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses 683system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses 684system.cpu.l2cache.demand_misses::cpu.inst 339 # number of demand (read+write) misses 685system.cpu.l2cache.demand_misses::cpu.data 141 # number of demand (read+write) misses 686system.cpu.l2cache.demand_misses::total 480 # number of demand (read+write) misses 687system.cpu.l2cache.overall_misses::cpu.inst 339 # number of overall misses 688system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses 689system.cpu.l2cache.overall_misses::total 480 # number of overall misses 690system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11455500 # number of ReadReq miss cycles 691system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3737500 # number of ReadReq miss cycles 692system.cpu.l2cache.ReadReq_miss_latency::total 15193000 # number of ReadReq miss cycles 693system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1807500 # number of ReadExReq miss cycles 694system.cpu.l2cache.ReadExReq_miss_latency::total 1807500 # number of ReadExReq miss cycles 695system.cpu.l2cache.demand_miss_latency::cpu.inst 11455500 # number of demand (read+write) miss cycles 696system.cpu.l2cache.demand_miss_latency::cpu.data 5545000 # number of demand (read+write) miss cycles 697system.cpu.l2cache.demand_miss_latency::total 17000500 # number of demand (read+write) miss cycles 698system.cpu.l2cache.overall_miss_latency::cpu.inst 11455500 # number of overall miss cycles 699system.cpu.l2cache.overall_miss_latency::cpu.data 5545000 # number of overall miss cycles 700system.cpu.l2cache.overall_miss_latency::total 17000500 # number of overall miss cycles 701system.cpu.l2cache.ReadReq_accesses::cpu.inst 342 # number of ReadReq accesses(hits+misses) 702system.cpu.l2cache.ReadReq_accesses::cpu.data 90 # number of ReadReq accesses(hits+misses) 703system.cpu.l2cache.ReadReq_accesses::total 432 # number of ReadReq accesses(hits+misses) 704system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) 705system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) 706system.cpu.l2cache.demand_accesses::cpu.inst 342 # number of demand (read+write) accesses 707system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses 708system.cpu.l2cache.demand_accesses::total 483 # number of demand (read+write) accesses 709system.cpu.l2cache.overall_accesses::cpu.inst 342 # number of overall (read+write) accesses 710system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses 711system.cpu.l2cache.overall_accesses::total 483 # number of overall (read+write) accesses 712system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991228 # miss rate for ReadReq accesses 713system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 714system.cpu.l2cache.ReadReq_miss_rate::total 0.993056 # miss rate for ReadReq accesses 715system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 716system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 717system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991228 # miss rate for demand accesses 718system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 719system.cpu.l2cache.demand_miss_rate::total 0.993789 # miss rate for demand accesses 720system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991228 # miss rate for overall accesses 721system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 722system.cpu.l2cache.overall_miss_rate::total 0.993789 # miss rate for overall accesses 723system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 33792.035398 # average ReadReq miss latency 724system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 41527.777778 # average ReadReq miss latency 725system.cpu.l2cache.ReadReq_avg_miss_latency::total 35414.918415 # average ReadReq miss latency 726system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 35441.176471 # average ReadExReq miss latency 727system.cpu.l2cache.ReadExReq_avg_miss_latency::total 35441.176471 # average ReadExReq miss latency 728system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 33792.035398 # average overall miss latency 729system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39326.241135 # average overall miss latency 730system.cpu.l2cache.demand_avg_miss_latency::total 35417.708333 # average overall miss latency 731system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 33792.035398 # average overall miss latency 732system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39326.241135 # average overall miss latency 733system.cpu.l2cache.overall_avg_miss_latency::total 35417.708333 # average overall miss latency 734system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 735system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 736system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 737system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 738system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 739system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 740system.cpu.l2cache.fast_writes 0 # number of fast writes performed 741system.cpu.l2cache.cache_copies 0 # number of cache copies performed 742system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 339 # number of ReadReq MSHR misses 743system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses 744system.cpu.l2cache.ReadReq_mshr_misses::total 429 # number of ReadReq MSHR misses 745system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses 746system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses 747system.cpu.l2cache.demand_mshr_misses::cpu.inst 339 # number of demand (read+write) MSHR misses 748system.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 749system.cpu.l2cache.demand_mshr_misses::total 480 # number of demand (read+write) MSHR misses 750system.cpu.l2cache.overall_mshr_misses::cpu.inst 339 # number of overall MSHR misses 751system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 752system.cpu.l2cache.overall_mshr_misses::total 480 # number of overall MSHR misses 753system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10252004 # number of ReadReq MSHR miss cycles 754system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3439074 # number of ReadReq MSHR miss cycles 755system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13691078 # number of ReadReq MSHR miss cycles 756system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1635054 # number of ReadExReq MSHR miss cycles 757system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1635054 # number of ReadExReq MSHR miss cycles 758system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10252004 # number of demand (read+write) MSHR miss cycles 759system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5074128 # number of demand (read+write) MSHR miss cycles 760system.cpu.l2cache.demand_mshr_miss_latency::total 15326132 # number of demand (read+write) MSHR miss cycles 761system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10252004 # number of overall MSHR miss cycles 762system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5074128 # number of overall MSHR miss cycles 763system.cpu.l2cache.overall_mshr_miss_latency::total 15326132 # number of overall MSHR miss cycles 764system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for ReadReq accesses 765system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 766system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993056 # mshr miss rate for ReadReq accesses 767system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 768system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 769system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for demand accesses 770system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 771system.cpu.l2cache.demand_mshr_miss_rate::total 0.993789 # mshr miss rate for demand accesses 772system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for overall accesses 773system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 774system.cpu.l2cache.overall_mshr_miss_rate::total 0.993789 # mshr miss rate for overall accesses 775system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 30241.899705 # average ReadReq mshr miss latency 776system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38211.933333 # average ReadReq mshr miss latency 777system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31913.934732 # average ReadReq mshr miss latency 778system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32059.882353 # average ReadExReq mshr miss latency 779system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 32059.882353 # average ReadExReq mshr miss latency 780system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 30241.899705 # average overall mshr miss latency 781system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35986.723404 # average overall mshr miss latency 782system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31929.441667 # average overall mshr miss latency 783system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 30241.899705 # average overall mshr miss latency 784system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35986.723404 # average overall mshr miss latency 785system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31929.441667 # average overall mshr miss latency 786system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 787 788---------- End Simulation Statistics ---------- 789