stats.txt revision 10229:aae7735450a9
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000022 # Number of seconds simulated 4sim_ticks 21843500 # Number of ticks simulated 5final_tick 21843500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 63396 # Simulator instruction rate (inst/s) 8host_op_rate 63384 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 268482897 # Simulator tick rate (ticks/s) 10host_mem_usage 267540 # Number of bytes of host memory used 11host_seconds 0.08 # Real time elapsed on the host 12sim_insts 5156 # Number of instructions simulated 13sim_ops 5156 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory 18system.physmem.bytes_read::total 30528 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 477 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 981527686 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 416050541 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1397578227 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 981527686 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 981527686 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 981527686 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 416050541 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1397578227 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 477 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 477 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 30528 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 30528 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 30 # Per bank write bursts 45system.physmem.perBankRdBursts::1 0 # Per bank write bursts 46system.physmem.perBankRdBursts::2 1 # Per bank write bursts 47system.physmem.perBankRdBursts::3 0 # Per bank write bursts 48system.physmem.perBankRdBursts::4 7 # Per bank write bursts 49system.physmem.perBankRdBursts::5 3 # Per bank write bursts 50system.physmem.perBankRdBursts::6 13 # Per bank write bursts 51system.physmem.perBankRdBursts::7 54 # Per bank write bursts 52system.physmem.perBankRdBursts::8 63 # Per bank write bursts 53system.physmem.perBankRdBursts::9 77 # Per bank write bursts 54system.physmem.perBankRdBursts::10 44 # Per bank write bursts 55system.physmem.perBankRdBursts::11 20 # Per bank write bursts 56system.physmem.perBankRdBursts::12 51 # Per bank write bursts 57system.physmem.perBankRdBursts::13 29 # Per bank write bursts 58system.physmem.perBankRdBursts::14 77 # Per bank write bursts 59system.physmem.perBankRdBursts::15 8 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 21764000 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 477 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 284 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 109 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 254.238532 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 174.990405 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 249.769927 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 31 28.44% 28.44% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 40 36.70% 65.14% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 16 14.68% 79.82% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 8 7.34% 87.16% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 4 3.67% 90.83% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 1 0.92% 91.74% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 3 2.75% 94.50% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 1 0.92% 95.41% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 5 4.59% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 109 # Bytes accessed per row activation 203system.physmem.totQLat 4715500 # Total ticks spent queuing 204system.physmem.totMemAccLat 13659250 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 2385000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 9885.74 # Average queueing delay per DRAM burst 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.physmem.avgMemAccLat 28635.74 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 1397.58 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 1397.58 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 10.92 # Data bus utilization in percentage 215system.physmem.busUtilRead 10.92 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 357 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 74.84 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 223system.physmem.avgGap 45626.83 # Average gap between requests 224system.physmem.pageHitRate 74.84 # Row buffer hit rate, read and write combined 225system.physmem.memoryStateTime::IDLE 11000 # Time in different power states 226system.physmem.memoryStateTime::REF 520000 # Time in different power states 227system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 228system.physmem.memoryStateTime::ACT 15319000 # Time in different power states 229system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 230system.membus.throughput 1397578227 # Throughput (bytes/s) 231system.membus.trans_dist::ReadReq 426 # Transaction distribution 232system.membus.trans_dist::ReadResp 426 # Transaction distribution 233system.membus.trans_dist::ReadExReq 51 # Transaction distribution 234system.membus.trans_dist::ReadExResp 51 # Transaction distribution 235system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 954 # Packet count per connected master and slave (bytes) 236system.membus.pkt_count::total 954 # Packet count per connected master and slave (bytes) 237system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30528 # Cumulative packet size per connected master and slave (bytes) 238system.membus.tot_pkt_size::total 30528 # Cumulative packet size per connected master and slave (bytes) 239system.membus.data_through_bus 30528 # Total data (bytes) 240system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 241system.membus.reqLayer0.occupancy 604500 # Layer occupancy (ticks) 242system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) 243system.membus.respLayer1.occupancy 4474250 # Layer occupancy (ticks) 244system.membus.respLayer1.utilization 20.5 # Layer utilization (%) 245system.cpu_clk_domain.clock 500 # Clock period in ticks 246system.cpu.branchPred.lookups 2174 # Number of BP lookups 247system.cpu.branchPred.condPredicted 1490 # Number of conditional branches predicted 248system.cpu.branchPred.condIncorrect 438 # Number of conditional branches incorrect 249system.cpu.branchPred.BTBLookups 1651 # Number of BTB lookups 250system.cpu.branchPred.BTBHits 492 # Number of BTB hits 251system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 252system.cpu.branchPred.BTBHitPct 29.800121 # BTB Hit Percentage 253system.cpu.branchPred.usedRAS 261 # Number of times the RAS was used to get a target. 254system.cpu.branchPred.RASInCorrect 67 # Number of incorrect RAS predictions. 255system.cpu.dtb.read_hits 0 # DTB read hits 256system.cpu.dtb.read_misses 0 # DTB read misses 257system.cpu.dtb.read_accesses 0 # DTB read accesses 258system.cpu.dtb.write_hits 0 # DTB write hits 259system.cpu.dtb.write_misses 0 # DTB write misses 260system.cpu.dtb.write_accesses 0 # DTB write accesses 261system.cpu.dtb.hits 0 # DTB hits 262system.cpu.dtb.misses 0 # DTB misses 263system.cpu.dtb.accesses 0 # DTB accesses 264system.cpu.itb.read_hits 0 # DTB read hits 265system.cpu.itb.read_misses 0 # DTB read misses 266system.cpu.itb.read_accesses 0 # DTB read accesses 267system.cpu.itb.write_hits 0 # DTB write hits 268system.cpu.itb.write_misses 0 # DTB write misses 269system.cpu.itb.write_accesses 0 # DTB write accesses 270system.cpu.itb.hits 0 # DTB hits 271system.cpu.itb.misses 0 # DTB misses 272system.cpu.itb.accesses 0 # DTB accesses 273system.cpu.workload.num_syscalls 8 # Number of system calls 274system.cpu.numCycles 43688 # number of cpu cycles simulated 275system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 276system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 277system.cpu.fetch.icacheStallCycles 8831 # Number of cycles fetch is stalled on an Icache miss 278system.cpu.fetch.Insts 13183 # Number of instructions fetch has processed 279system.cpu.fetch.Branches 2174 # Number of branches that fetch encountered 280system.cpu.fetch.predictedBranches 753 # Number of branches that fetch has predicted taken 281system.cpu.fetch.Cycles 3213 # Number of cycles fetch has run and was not squashing or blocked 282system.cpu.fetch.SquashCycles 1374 # Number of cycles fetch has spent squashing 283system.cpu.fetch.BlockedCycles 1402 # Number of cycles fetch has spent blocked 284system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps 285system.cpu.fetch.CacheLines 1965 # Number of cache lines fetched 286system.cpu.fetch.IcacheSquashes 277 # Number of outstanding Icache misses that were squashed 287system.cpu.fetch.rateDist::samples 14499 # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.rateDist::mean 0.909235 # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::stdev 2.221283 # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::0 11286 77.84% 77.84% # Number of instructions fetched each cycle (Total) 292system.cpu.fetch.rateDist::1 1317 9.08% 86.92% # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::2 104 0.72% 87.64% # Number of instructions fetched each cycle (Total) 294system.cpu.fetch.rateDist::3 131 0.90% 88.54% # Number of instructions fetched each cycle (Total) 295system.cpu.fetch.rateDist::4 305 2.10% 90.65% # Number of instructions fetched each cycle (Total) 296system.cpu.fetch.rateDist::5 115 0.79% 91.44% # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::6 150 1.03% 92.48% # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.rateDist::7 158 1.09% 93.57% # Number of instructions fetched each cycle (Total) 299system.cpu.fetch.rateDist::8 933 6.43% 100.00% # Number of instructions fetched each cycle (Total) 300system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 301system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 302system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.rateDist::total 14499 # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.branchRate 0.049762 # Number of branch fetches per cycle 305system.cpu.fetch.rate 0.301753 # Number of inst fetches per cycle 306system.cpu.decode.IdleCycles 8899 # Number of cycles decode is idle 307system.cpu.decode.BlockedCycles 1654 # Number of cycles decode is blocked 308system.cpu.decode.RunCycles 3025 # Number of cycles decode is running 309system.cpu.decode.UnblockCycles 53 # Number of cycles decode is unblocking 310system.cpu.decode.SquashCycles 868 # Number of cycles decode is squashing 311system.cpu.decode.BranchResolved 157 # Number of times decode resolved a branch 312system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction 313system.cpu.decode.DecodedInsts 12292 # Number of instructions handled by decode 314system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode 315system.cpu.rename.SquashCycles 868 # Number of cycles rename is squashing 316system.cpu.rename.IdleCycles 9081 # Number of cycles rename is idle 317system.cpu.rename.BlockCycles 531 # Number of cycles rename is blocking 318system.cpu.rename.serializeStallCycles 973 # count of cycles rename stalled for serializing inst 319system.cpu.rename.RunCycles 2898 # Number of cycles rename is running 320system.cpu.rename.UnblockCycles 148 # Number of cycles rename is unblocking 321system.cpu.rename.RenamedInsts 11862 # Number of instructions processed by rename 322system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full 323system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full 324system.cpu.rename.LSQFullEvents 124 # Number of times rename has blocked due to LSQ full 325system.cpu.rename.RenamedOperands 7176 # Number of destination operands rename has renamed 326system.cpu.rename.RenameLookups 14099 # Number of register rename lookups that rename has made 327system.cpu.rename.int_rename_lookups 13870 # Number of integer rename lookups 328system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups 329system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed 330system.cpu.rename.UndoneMaps 3778 # Number of HB maps that are undone due to squashing 331system.cpu.rename.serializingInsts 16 # count of serializing insts renamed 332system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed 333system.cpu.rename.skidInsts 328 # count of insts added to the skid buffer 334system.cpu.memDep0.insertedLoads 2457 # Number of loads inserted to the mem dependence unit. 335system.cpu.memDep0.insertedStores 1193 # Number of stores inserted to the mem dependence unit. 336system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 337system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. 338system.cpu.iq.iqInstsAdded 9210 # Number of instructions added to the IQ (excludes non-spec) 339system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ 340system.cpu.iq.iqInstsIssued 8293 # Number of instructions issued 341system.cpu.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued 342system.cpu.iq.iqSquashedInstsExamined 3412 # Number of squashed instructions iterated over during squash; mainly for profiling 343system.cpu.iq.iqSquashedOperandsExamined 2076 # Number of squashed operands that are examined and possibly removed from graph 344system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed 345system.cpu.iq.issued_per_cycle::samples 14499 # Number of insts issued each cycle 346system.cpu.iq.issued_per_cycle::mean 0.571970 # Number of insts issued each cycle 347system.cpu.iq.issued_per_cycle::stdev 1.240543 # Number of insts issued each cycle 348system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 349system.cpu.iq.issued_per_cycle::0 10916 75.29% 75.29% # Number of insts issued each cycle 350system.cpu.iq.issued_per_cycle::1 1422 9.81% 85.10% # Number of insts issued each cycle 351system.cpu.iq.issued_per_cycle::2 891 6.15% 91.24% # Number of insts issued each cycle 352system.cpu.iq.issued_per_cycle::3 553 3.81% 95.05% # Number of insts issued each cycle 353system.cpu.iq.issued_per_cycle::4 355 2.45% 97.50% # Number of insts issued each cycle 354system.cpu.iq.issued_per_cycle::5 226 1.56% 99.06% # Number of insts issued each cycle 355system.cpu.iq.issued_per_cycle::6 89 0.61% 99.68% # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::7 30 0.21% 99.88% # Number of insts issued each cycle 357system.cpu.iq.issued_per_cycle::8 17 0.12% 100.00% # Number of insts issued each cycle 358system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::total 14499 # Number of insts issued each cycle 362system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 363system.cpu.iq.fu_full::IntAlu 5 3.12% 3.12% # attempts to use FU when none available 364system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available 365system.cpu.iq.fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available 366system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available 367system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.12% # attempts to use FU when none available 368system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.12% # attempts to use FU when none available 369system.cpu.iq.fu_full::FloatMult 0 0.00% 3.12% # attempts to use FU when none available 370system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.12% # attempts to use FU when none available 371system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.12% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.12% # attempts to use FU when none available 373system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.12% # attempts to use FU when none available 374system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.12% # attempts to use FU when none available 375system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.12% # attempts to use FU when none available 376system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.12% # attempts to use FU when none available 377system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.12% # attempts to use FU when none available 378system.cpu.iq.fu_full::SimdMult 0 0.00% 3.12% # attempts to use FU when none available 379system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.12% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdShift 0 0.00% 3.12% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.12% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.12% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.12% # attempts to use FU when none available 384system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.12% # attempts to use FU when none available 385system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.12% # attempts to use FU when none available 386system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.12% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.12% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.12% # attempts to use FU when none available 389system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available 390system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available 391system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available 392system.cpu.iq.fu_full::MemRead 101 63.12% 66.25% # attempts to use FU when none available 393system.cpu.iq.fu_full::MemWrite 54 33.75% 100.00% # attempts to use FU when none available 394system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 395system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 396system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 397system.cpu.iq.FU_type_0::IntAlu 4933 59.48% 59.48% # Type of FU issued 398system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.54% # Type of FU issued 399system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.57% # Type of FU issued 400system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.59% # Type of FU issued 401system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.59% # Type of FU issued 402system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.59% # Type of FU issued 403system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.59% # Type of FU issued 404system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.59% # Type of FU issued 405system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.59% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.59% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.59% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.59% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.59% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.59% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.59% # Type of FU issued 412system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.59% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.59% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.59% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.59% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.59% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.59% # Type of FU issued 418system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.59% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.59% # Type of FU issued 420system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.59% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.59% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.59% # Type of FU issued 423system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.59% # Type of FU issued 424system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.59% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.59% # Type of FU issued 426system.cpu.iq.FU_type_0::MemRead 2247 27.10% 86.69% # Type of FU issued 427system.cpu.iq.FU_type_0::MemWrite 1104 13.31% 100.00% # Type of FU issued 428system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 429system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 430system.cpu.iq.FU_type_0::total 8293 # Type of FU issued 431system.cpu.iq.rate 0.189823 # Inst issue rate 432system.cpu.iq.fu_busy_cnt 160 # FU busy when requested 433system.cpu.iq.fu_busy_rate 0.019293 # FU busy rate (busy events/executed inst) 434system.cpu.iq.int_inst_queue_reads 31280 # Number of integer instruction queue reads 435system.cpu.iq.int_inst_queue_writes 12643 # Number of integer instruction queue writes 436system.cpu.iq.int_inst_queue_wakeup_accesses 7453 # Number of integer instruction queue wakeup accesses 437system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads 438system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 439system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses 440system.cpu.iq.int_alu_accesses 8451 # Number of integer alu accesses 441system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses 442system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores 443system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 444system.cpu.iew.lsq.thread0.squashedLoads 1294 # Number of loads squashed 445system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed 446system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations 447system.cpu.iew.lsq.thread0.squashedStores 268 # Number of stores squashed 448system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 449system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 450system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 451system.cpu.iew.lsq.thread0.cacheBlocked 32 # Number of times an access to memory failed due to the cache being blocked 452system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 453system.cpu.iew.iewSquashCycles 868 # Number of cycles IEW is squashing 454system.cpu.iew.iewBlockCycles 349 # Number of cycles IEW is blocking 455system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking 456system.cpu.iew.iewDispatchedInsts 10734 # Number of instructions dispatched to IQ 457system.cpu.iew.iewDispSquashedInsts 85 # Number of squashed instructions skipped by dispatch 458system.cpu.iew.iewDispLoadInsts 2457 # Number of dispatched load instructions 459system.cpu.iew.iewDispStoreInsts 1193 # Number of dispatched store instructions 460system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions 461system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall 462system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 463system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations 464system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly 465system.cpu.iew.predictedNotTakenIncorrect 362 # Number of branches that were predicted not taken incorrectly 466system.cpu.iew.branchMispredicts 463 # Number of branch mispredicts detected at execute 467system.cpu.iew.iewExecutedInsts 7912 # Number of executed instructions 468system.cpu.iew.iewExecLoadInsts 2107 # Number of load instructions executed 469system.cpu.iew.iewExecSquashedInsts 381 # Number of squashed instructions skipped in execute 470system.cpu.iew.exec_swp 0 # number of swp insts executed 471system.cpu.iew.exec_nop 1512 # number of nop insts executed 472system.cpu.iew.exec_refs 3186 # number of memory reference insts executed 473system.cpu.iew.exec_branches 1344 # Number of branches executed 474system.cpu.iew.exec_stores 1079 # Number of stores executed 475system.cpu.iew.exec_rate 0.181102 # Inst execution rate 476system.cpu.iew.wb_sent 7546 # cumulative count of insts sent to commit 477system.cpu.iew.wb_count 7455 # cumulative count of insts written-back 478system.cpu.iew.wb_producers 2921 # num instructions producing a value 479system.cpu.iew.wb_consumers 4197 # num instructions consuming a value 480system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 481system.cpu.iew.wb_rate 0.170642 # insts written-back per cycle 482system.cpu.iew.wb_fanout 0.695973 # average fanout of values written-back 483system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 484system.cpu.commit.commitSquashedInsts 4914 # The number of squashed insts skipped by commit 485system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards 486system.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted 487system.cpu.commit.committed_per_cycle::samples 13631 # Number of insts commited each cycle 488system.cpu.commit.committed_per_cycle::mean 0.426454 # Number of insts commited each cycle 489system.cpu.commit.committed_per_cycle::stdev 1.206792 # Number of insts commited each cycle 490system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 491system.cpu.commit.committed_per_cycle::0 11229 82.38% 82.38% # Number of insts commited each cycle 492system.cpu.commit.committed_per_cycle::1 999 7.33% 89.71% # Number of insts commited each cycle 493system.cpu.commit.committed_per_cycle::2 630 4.62% 94.33% # Number of insts commited each cycle 494system.cpu.commit.committed_per_cycle::3 315 2.31% 96.64% # Number of insts commited each cycle 495system.cpu.commit.committed_per_cycle::4 149 1.09% 97.73% # Number of insts commited each cycle 496system.cpu.commit.committed_per_cycle::5 94 0.69% 98.42% # Number of insts commited each cycle 497system.cpu.commit.committed_per_cycle::6 68 0.50% 98.92% # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::7 41 0.30% 99.22% # Number of insts commited each cycle 499system.cpu.commit.committed_per_cycle::8 106 0.78% 100.00% # Number of insts commited each cycle 500system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 501system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 502system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 503system.cpu.commit.committed_per_cycle::total 13631 # Number of insts commited each cycle 504system.cpu.commit.committedInsts 5813 # Number of instructions committed 505system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed 506system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 507system.cpu.commit.refs 2088 # Number of memory references committed 508system.cpu.commit.loads 1163 # Number of loads committed 509system.cpu.commit.membars 0 # Number of memory barriers committed 510system.cpu.commit.branches 915 # Number of branches committed 511system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. 512system.cpu.commit.int_insts 5111 # Number of committed integer instructions. 513system.cpu.commit.function_calls 87 # Number of function calls committed. 514system.cpu.commit.op_class_0::No_OpClass 657 11.30% 11.30% # Class of committed instruction 515system.cpu.commit.op_class_0::IntAlu 3062 52.68% 63.98% # Class of committed instruction 516system.cpu.commit.op_class_0::IntMult 3 0.05% 64.03% # Class of committed instruction 517system.cpu.commit.op_class_0::IntDiv 1 0.02% 64.05% # Class of committed instruction 518system.cpu.commit.op_class_0::FloatAdd 2 0.03% 64.08% # Class of committed instruction 519system.cpu.commit.op_class_0::FloatCmp 0 0.00% 64.08% # Class of committed instruction 520system.cpu.commit.op_class_0::FloatCvt 0 0.00% 64.08% # Class of committed instruction 521system.cpu.commit.op_class_0::FloatMult 0 0.00% 64.08% # Class of committed instruction 522system.cpu.commit.op_class_0::FloatDiv 0 0.00% 64.08% # Class of committed instruction 523system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.08% # Class of committed instruction 524system.cpu.commit.op_class_0::SimdAdd 0 0.00% 64.08% # Class of committed instruction 525system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.08% # Class of committed instruction 526system.cpu.commit.op_class_0::SimdAlu 0 0.00% 64.08% # Class of committed instruction 527system.cpu.commit.op_class_0::SimdCmp 0 0.00% 64.08% # Class of committed instruction 528system.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.08% # Class of committed instruction 529system.cpu.commit.op_class_0::SimdMisc 0 0.00% 64.08% # Class of committed instruction 530system.cpu.commit.op_class_0::SimdMult 0 0.00% 64.08% # Class of committed instruction 531system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 64.08% # Class of committed instruction 532system.cpu.commit.op_class_0::SimdShift 0 0.00% 64.08% # Class of committed instruction 533system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 64.08% # Class of committed instruction 534system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 64.08% # Class of committed instruction 535system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 64.08% # Class of committed instruction 536system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 64.08% # Class of committed instruction 537system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 64.08% # Class of committed instruction 538system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 64.08% # Class of committed instruction 539system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 64.08% # Class of committed instruction 540system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 64.08% # Class of committed instruction 541system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.08% # Class of committed instruction 542system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.08% # Class of committed instruction 543system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.08% # Class of committed instruction 544system.cpu.commit.op_class_0::MemRead 1163 20.01% 84.09% # Class of committed instruction 545system.cpu.commit.op_class_0::MemWrite 925 15.91% 100.00% # Class of committed instruction 546system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 547system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 548system.cpu.commit.op_class_0::total 5813 # Class of committed instruction 549system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached 550system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 551system.cpu.rob.rob_reads 24239 # The number of ROB reads 552system.cpu.rob.rob_writes 22333 # The number of ROB writes 553system.cpu.timesIdled 287 # Number of times that the entire CPU went into an idle state and unscheduled itself 554system.cpu.idleCycles 29189 # Total number of cycles that the CPU has spent unscheduled due to idling 555system.cpu.committedInsts 5156 # Number of Instructions Simulated 556system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated 557system.cpu.cpi 8.473235 # CPI: Cycles Per Instruction 558system.cpu.cpi_total 8.473235 # CPI: Total CPI of All Threads 559system.cpu.ipc 0.118019 # IPC: Instructions Per Cycle 560system.cpu.ipc_total 0.118019 # IPC: Total IPC of All Threads 561system.cpu.int_regfile_reads 10743 # number of integer regfile reads 562system.cpu.int_regfile_writes 5234 # number of integer regfile writes 563system.cpu.fp_regfile_reads 3 # number of floating regfile reads 564system.cpu.fp_regfile_writes 1 # number of floating regfile writes 565system.cpu.misc_regfile_reads 148 # number of misc regfile reads 566system.cpu.toL2Bus.throughput 1406368027 # Throughput (bytes/s) 567system.cpu.toL2Bus.trans_dist::ReadReq 429 # Transaction distribution 568system.cpu.toL2Bus.trans_dist::ReadResp 429 # Transaction distribution 569system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution 570system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution 571system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 676 # Packet count per connected master and slave (bytes) 572system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes) 573system.cpu.toL2Bus.pkt_count::total 960 # Packet count per connected master and slave (bytes) 574system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21632 # Cumulative packet size per connected master and slave (bytes) 575system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) 576system.cpu.toL2Bus.tot_pkt_size::total 30720 # Cumulative packet size per connected master and slave (bytes) 577system.cpu.toL2Bus.data_through_bus 30720 # Total data (bytes) 578system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 579system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks) 580system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 581system.cpu.toL2Bus.respLayer0.occupancy 571500 # Layer occupancy (ticks) 582system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) 583system.cpu.toL2Bus.respLayer1.occupancy 228250 # Layer occupancy (ticks) 584system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) 585system.cpu.icache.tags.replacements 17 # number of replacements 586system.cpu.icache.tags.tagsinuse 161.382673 # Cycle average of tags in use 587system.cpu.icache.tags.total_refs 1514 # Total number of references to valid blocks. 588system.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks. 589system.cpu.icache.tags.avg_refs 4.479290 # Average number of references to valid blocks. 590system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 591system.cpu.icache.tags.occ_blocks::cpu.inst 161.382673 # Average occupied blocks per requestor 592system.cpu.icache.tags.occ_percent::cpu.inst 0.078800 # Average percentage of cache occupancy 593system.cpu.icache.tags.occ_percent::total 0.078800 # Average percentage of cache occupancy 594system.cpu.icache.tags.occ_task_id_blocks::1024 321 # Occupied blocks per task id 595system.cpu.icache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id 596system.cpu.icache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id 597system.cpu.icache.tags.occ_task_id_percent::1024 0.156738 # Percentage of cache occupancy per task id 598system.cpu.icache.tags.tag_accesses 4268 # Number of tag accesses 599system.cpu.icache.tags.data_accesses 4268 # Number of data accesses 600system.cpu.icache.ReadReq_hits::cpu.inst 1514 # number of ReadReq hits 601system.cpu.icache.ReadReq_hits::total 1514 # number of ReadReq hits 602system.cpu.icache.demand_hits::cpu.inst 1514 # number of demand (read+write) hits 603system.cpu.icache.demand_hits::total 1514 # number of demand (read+write) hits 604system.cpu.icache.overall_hits::cpu.inst 1514 # number of overall hits 605system.cpu.icache.overall_hits::total 1514 # number of overall hits 606system.cpu.icache.ReadReq_misses::cpu.inst 451 # number of ReadReq misses 607system.cpu.icache.ReadReq_misses::total 451 # number of ReadReq misses 608system.cpu.icache.demand_misses::cpu.inst 451 # number of demand (read+write) misses 609system.cpu.icache.demand_misses::total 451 # number of demand (read+write) misses 610system.cpu.icache.overall_misses::cpu.inst 451 # number of overall misses 611system.cpu.icache.overall_misses::total 451 # number of overall misses 612system.cpu.icache.ReadReq_miss_latency::cpu.inst 31159250 # number of ReadReq miss cycles 613system.cpu.icache.ReadReq_miss_latency::total 31159250 # number of ReadReq miss cycles 614system.cpu.icache.demand_miss_latency::cpu.inst 31159250 # number of demand (read+write) miss cycles 615system.cpu.icache.demand_miss_latency::total 31159250 # number of demand (read+write) miss cycles 616system.cpu.icache.overall_miss_latency::cpu.inst 31159250 # number of overall miss cycles 617system.cpu.icache.overall_miss_latency::total 31159250 # number of overall miss cycles 618system.cpu.icache.ReadReq_accesses::cpu.inst 1965 # number of ReadReq accesses(hits+misses) 619system.cpu.icache.ReadReq_accesses::total 1965 # number of ReadReq accesses(hits+misses) 620system.cpu.icache.demand_accesses::cpu.inst 1965 # number of demand (read+write) accesses 621system.cpu.icache.demand_accesses::total 1965 # number of demand (read+write) accesses 622system.cpu.icache.overall_accesses::cpu.inst 1965 # number of overall (read+write) accesses 623system.cpu.icache.overall_accesses::total 1965 # number of overall (read+write) accesses 624system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229517 # miss rate for ReadReq accesses 625system.cpu.icache.ReadReq_miss_rate::total 0.229517 # miss rate for ReadReq accesses 626system.cpu.icache.demand_miss_rate::cpu.inst 0.229517 # miss rate for demand accesses 627system.cpu.icache.demand_miss_rate::total 0.229517 # miss rate for demand accesses 628system.cpu.icache.overall_miss_rate::cpu.inst 0.229517 # miss rate for overall accesses 629system.cpu.icache.overall_miss_rate::total 0.229517 # miss rate for overall accesses 630system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69089.246120 # average ReadReq miss latency 631system.cpu.icache.ReadReq_avg_miss_latency::total 69089.246120 # average ReadReq miss latency 632system.cpu.icache.demand_avg_miss_latency::cpu.inst 69089.246120 # average overall miss latency 633system.cpu.icache.demand_avg_miss_latency::total 69089.246120 # average overall miss latency 634system.cpu.icache.overall_avg_miss_latency::cpu.inst 69089.246120 # average overall miss latency 635system.cpu.icache.overall_avg_miss_latency::total 69089.246120 # average overall miss latency 636system.cpu.icache.blocked_cycles::no_mshrs 47 # number of cycles access was blocked 637system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 638system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked 639system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 640system.cpu.icache.avg_blocked_cycles::no_mshrs 47 # average number of cycles each access was blocked 641system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 642system.cpu.icache.fast_writes 0 # number of fast writes performed 643system.cpu.icache.cache_copies 0 # number of cache copies performed 644system.cpu.icache.ReadReq_mshr_hits::cpu.inst 113 # number of ReadReq MSHR hits 645system.cpu.icache.ReadReq_mshr_hits::total 113 # number of ReadReq MSHR hits 646system.cpu.icache.demand_mshr_hits::cpu.inst 113 # number of demand (read+write) MSHR hits 647system.cpu.icache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits 648system.cpu.icache.overall_mshr_hits::cpu.inst 113 # number of overall MSHR hits 649system.cpu.icache.overall_mshr_hits::total 113 # number of overall MSHR hits 650system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses 651system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses 652system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses 653system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses 654system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses 655system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses 656system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24154000 # number of ReadReq MSHR miss cycles 657system.cpu.icache.ReadReq_mshr_miss_latency::total 24154000 # number of ReadReq MSHR miss cycles 658system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24154000 # number of demand (read+write) MSHR miss cycles 659system.cpu.icache.demand_mshr_miss_latency::total 24154000 # number of demand (read+write) MSHR miss cycles 660system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24154000 # number of overall MSHR miss cycles 661system.cpu.icache.overall_mshr_miss_latency::total 24154000 # number of overall MSHR miss cycles 662system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for ReadReq accesses 663system.cpu.icache.ReadReq_mshr_miss_rate::total 0.172010 # mshr miss rate for ReadReq accesses 664system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for demand accesses 665system.cpu.icache.demand_mshr_miss_rate::total 0.172010 # mshr miss rate for demand accesses 666system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for overall accesses 667system.cpu.icache.overall_mshr_miss_rate::total 0.172010 # mshr miss rate for overall accesses 668system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71461.538462 # average ReadReq mshr miss latency 669system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71461.538462 # average ReadReq mshr miss latency 670system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71461.538462 # average overall mshr miss latency 671system.cpu.icache.demand_avg_mshr_miss_latency::total 71461.538462 # average overall mshr miss latency 672system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71461.538462 # average overall mshr miss latency 673system.cpu.icache.overall_avg_mshr_miss_latency::total 71461.538462 # average overall mshr miss latency 674system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 675system.cpu.l2cache.tags.replacements 0 # number of replacements 676system.cpu.l2cache.tags.tagsinuse 221.484913 # Cycle average of tags in use 677system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. 678system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks. 679system.cpu.l2cache.tags.avg_refs 0.007042 # Average number of references to valid blocks. 680system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 681system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.674419 # Average occupied blocks per requestor 682system.cpu.l2cache.tags.occ_blocks::cpu.data 57.810494 # Average occupied blocks per requestor 683system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004995 # Average percentage of cache occupancy 684system.cpu.l2cache.tags.occ_percent::cpu.data 0.001764 # Average percentage of cache occupancy 685system.cpu.l2cache.tags.occ_percent::total 0.006759 # Average percentage of cache occupancy 686system.cpu.l2cache.tags.occ_task_id_blocks::1024 426 # Occupied blocks per task id 687system.cpu.l2cache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id 688system.cpu.l2cache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id 689system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013000 # Percentage of cache occupancy per task id 690system.cpu.l2cache.tags.tag_accesses 4317 # Number of tag accesses 691system.cpu.l2cache.tags.data_accesses 4317 # Number of data accesses 692system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits 693system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits 694system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 695system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 696system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 697system.cpu.l2cache.overall_hits::total 3 # number of overall hits 698system.cpu.l2cache.ReadReq_misses::cpu.inst 335 # number of ReadReq misses 699system.cpu.l2cache.ReadReq_misses::cpu.data 91 # number of ReadReq misses 700system.cpu.l2cache.ReadReq_misses::total 426 # number of ReadReq misses 701system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses 702system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses 703system.cpu.l2cache.demand_misses::cpu.inst 335 # number of demand (read+write) misses 704system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses 705system.cpu.l2cache.demand_misses::total 477 # number of demand (read+write) misses 706system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses 707system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses 708system.cpu.l2cache.overall_misses::total 477 # number of overall misses 709system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23786000 # number of ReadReq miss cycles 710system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7056500 # number of ReadReq miss cycles 711system.cpu.l2cache.ReadReq_miss_latency::total 30842500 # number of ReadReq miss cycles 712system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3776250 # number of ReadExReq miss cycles 713system.cpu.l2cache.ReadExReq_miss_latency::total 3776250 # number of ReadExReq miss cycles 714system.cpu.l2cache.demand_miss_latency::cpu.inst 23786000 # number of demand (read+write) miss cycles 715system.cpu.l2cache.demand_miss_latency::cpu.data 10832750 # number of demand (read+write) miss cycles 716system.cpu.l2cache.demand_miss_latency::total 34618750 # number of demand (read+write) miss cycles 717system.cpu.l2cache.overall_miss_latency::cpu.inst 23786000 # number of overall miss cycles 718system.cpu.l2cache.overall_miss_latency::cpu.data 10832750 # number of overall miss cycles 719system.cpu.l2cache.overall_miss_latency::total 34618750 # number of overall miss cycles 720system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses) 721system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) 722system.cpu.l2cache.ReadReq_accesses::total 429 # number of ReadReq accesses(hits+misses) 723system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) 724system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) 725system.cpu.l2cache.demand_accesses::cpu.inst 338 # number of demand (read+write) accesses 726system.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses 727system.cpu.l2cache.demand_accesses::total 480 # number of demand (read+write) accesses 728system.cpu.l2cache.overall_accesses::cpu.inst 338 # number of overall (read+write) accesses 729system.cpu.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses 730system.cpu.l2cache.overall_accesses::total 480 # number of overall (read+write) accesses 731system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991124 # miss rate for ReadReq accesses 732system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 733system.cpu.l2cache.ReadReq_miss_rate::total 0.993007 # miss rate for ReadReq accesses 734system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 735system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 736system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991124 # miss rate for demand accesses 737system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 738system.cpu.l2cache.demand_miss_rate::total 0.993750 # miss rate for demand accesses 739system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991124 # miss rate for overall accesses 740system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 741system.cpu.l2cache.overall_miss_rate::total 0.993750 # miss rate for overall accesses 742system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71002.985075 # average ReadReq miss latency 743system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77543.956044 # average ReadReq miss latency 744system.cpu.l2cache.ReadReq_avg_miss_latency::total 72400.234742 # average ReadReq miss latency 745system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74044.117647 # average ReadExReq miss latency 746system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74044.117647 # average ReadExReq miss latency 747system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71002.985075 # average overall miss latency 748system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76286.971831 # average overall miss latency 749system.cpu.l2cache.demand_avg_miss_latency::total 72575.995807 # average overall miss latency 750system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71002.985075 # average overall miss latency 751system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76286.971831 # average overall miss latency 752system.cpu.l2cache.overall_avg_miss_latency::total 72575.995807 # average overall miss latency 753system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 754system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 755system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 756system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 757system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 758system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 759system.cpu.l2cache.fast_writes 0 # number of fast writes performed 760system.cpu.l2cache.cache_copies 0 # number of cache copies performed 761system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 335 # number of ReadReq MSHR misses 762system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 763system.cpu.l2cache.ReadReq_mshr_misses::total 426 # number of ReadReq MSHR misses 764system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses 765system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses 766system.cpu.l2cache.demand_mshr_misses::cpu.inst 335 # number of demand (read+write) MSHR misses 767system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 768system.cpu.l2cache.demand_mshr_misses::total 477 # number of demand (read+write) MSHR misses 769system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses 770system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 771system.cpu.l2cache.overall_mshr_misses::total 477 # number of overall MSHR misses 772system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19551000 # number of ReadReq MSHR miss cycles 773system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5938500 # number of ReadReq MSHR miss cycles 774system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25489500 # number of ReadReq MSHR miss cycles 775system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3144250 # number of ReadExReq MSHR miss cycles 776system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3144250 # number of ReadExReq MSHR miss cycles 777system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19551000 # number of demand (read+write) MSHR miss cycles 778system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9082750 # number of demand (read+write) MSHR miss cycles 779system.cpu.l2cache.demand_mshr_miss_latency::total 28633750 # number of demand (read+write) MSHR miss cycles 780system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19551000 # number of overall MSHR miss cycles 781system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9082750 # number of overall MSHR miss cycles 782system.cpu.l2cache.overall_mshr_miss_latency::total 28633750 # number of overall MSHR miss cycles 783system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for ReadReq accesses 784system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 785system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993007 # mshr miss rate for ReadReq accesses 786system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 787system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 788system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for demand accesses 789system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 790system.cpu.l2cache.demand_mshr_miss_rate::total 0.993750 # mshr miss rate for demand accesses 791system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for overall accesses 792system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 793system.cpu.l2cache.overall_mshr_miss_rate::total 0.993750 # mshr miss rate for overall accesses 794system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58361.194030 # average ReadReq mshr miss latency 795system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65258.241758 # average ReadReq mshr miss latency 796system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59834.507042 # average ReadReq mshr miss latency 797system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61651.960784 # average ReadExReq mshr miss latency 798system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61651.960784 # average ReadExReq mshr miss latency 799system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58361.194030 # average overall mshr miss latency 800system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63963.028169 # average overall mshr miss latency 801system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60028.825996 # average overall mshr miss latency 802system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58361.194030 # average overall mshr miss latency 803system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63963.028169 # average overall mshr miss latency 804system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60028.825996 # average overall mshr miss latency 805system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 806system.cpu.dcache.tags.replacements 0 # number of replacements 807system.cpu.dcache.tags.tagsinuse 91.603992 # Cycle average of tags in use 808system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. 809system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. 810system.cpu.dcache.tags.avg_refs 16.866197 # Average number of references to valid blocks. 811system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 812system.cpu.dcache.tags.occ_blocks::cpu.data 91.603992 # Average occupied blocks per requestor 813system.cpu.dcache.tags.occ_percent::cpu.data 0.022364 # Average percentage of cache occupancy 814system.cpu.dcache.tags.occ_percent::total 0.022364 # Average percentage of cache occupancy 815system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id 816system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 817system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id 818system.cpu.dcache.tags.occ_task_id_percent::1024 0.034668 # Percentage of cache occupancy per task id 819system.cpu.dcache.tags.tag_accesses 5952 # Number of tag accesses 820system.cpu.dcache.tags.data_accesses 5952 # Number of data accesses 821system.cpu.dcache.ReadReq_hits::cpu.data 1832 # number of ReadReq hits 822system.cpu.dcache.ReadReq_hits::total 1832 # number of ReadReq hits 823system.cpu.dcache.WriteReq_hits::cpu.data 563 # number of WriteReq hits 824system.cpu.dcache.WriteReq_hits::total 563 # number of WriteReq hits 825system.cpu.dcache.demand_hits::cpu.data 2395 # number of demand (read+write) hits 826system.cpu.dcache.demand_hits::total 2395 # number of demand (read+write) hits 827system.cpu.dcache.overall_hits::cpu.data 2395 # number of overall hits 828system.cpu.dcache.overall_hits::total 2395 # number of overall hits 829system.cpu.dcache.ReadReq_misses::cpu.data 148 # number of ReadReq misses 830system.cpu.dcache.ReadReq_misses::total 148 # number of ReadReq misses 831system.cpu.dcache.WriteReq_misses::cpu.data 362 # number of WriteReq misses 832system.cpu.dcache.WriteReq_misses::total 362 # number of WriteReq misses 833system.cpu.dcache.demand_misses::cpu.data 510 # number of demand (read+write) misses 834system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses 835system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses 836system.cpu.dcache.overall_misses::total 510 # number of overall misses 837system.cpu.dcache.ReadReq_miss_latency::cpu.data 10242750 # number of ReadReq miss cycles 838system.cpu.dcache.ReadReq_miss_latency::total 10242750 # number of ReadReq miss cycles 839system.cpu.dcache.WriteReq_miss_latency::cpu.data 22302249 # number of WriteReq miss cycles 840system.cpu.dcache.WriteReq_miss_latency::total 22302249 # number of WriteReq miss cycles 841system.cpu.dcache.demand_miss_latency::cpu.data 32544999 # number of demand (read+write) miss cycles 842system.cpu.dcache.demand_miss_latency::total 32544999 # number of demand (read+write) miss cycles 843system.cpu.dcache.overall_miss_latency::cpu.data 32544999 # number of overall miss cycles 844system.cpu.dcache.overall_miss_latency::total 32544999 # number of overall miss cycles 845system.cpu.dcache.ReadReq_accesses::cpu.data 1980 # number of ReadReq accesses(hits+misses) 846system.cpu.dcache.ReadReq_accesses::total 1980 # number of ReadReq accesses(hits+misses) 847system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 848system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 849system.cpu.dcache.demand_accesses::cpu.data 2905 # number of demand (read+write) accesses 850system.cpu.dcache.demand_accesses::total 2905 # number of demand (read+write) accesses 851system.cpu.dcache.overall_accesses::cpu.data 2905 # number of overall (read+write) accesses 852system.cpu.dcache.overall_accesses::total 2905 # number of overall (read+write) accesses 853system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074747 # miss rate for ReadReq accesses 854system.cpu.dcache.ReadReq_miss_rate::total 0.074747 # miss rate for ReadReq accesses 855system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.391351 # miss rate for WriteReq accesses 856system.cpu.dcache.WriteReq_miss_rate::total 0.391351 # miss rate for WriteReq accesses 857system.cpu.dcache.demand_miss_rate::cpu.data 0.175559 # miss rate for demand accesses 858system.cpu.dcache.demand_miss_rate::total 0.175559 # miss rate for demand accesses 859system.cpu.dcache.overall_miss_rate::cpu.data 0.175559 # miss rate for overall accesses 860system.cpu.dcache.overall_miss_rate::total 0.175559 # miss rate for overall accesses 861system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69207.770270 # average ReadReq miss latency 862system.cpu.dcache.ReadReq_avg_miss_latency::total 69207.770270 # average ReadReq miss latency 863system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61608.422652 # average WriteReq miss latency 864system.cpu.dcache.WriteReq_avg_miss_latency::total 61608.422652 # average WriteReq miss latency 865system.cpu.dcache.demand_avg_miss_latency::cpu.data 63813.723529 # average overall miss latency 866system.cpu.dcache.demand_avg_miss_latency::total 63813.723529 # average overall miss latency 867system.cpu.dcache.overall_avg_miss_latency::cpu.data 63813.723529 # average overall miss latency 868system.cpu.dcache.overall_avg_miss_latency::total 63813.723529 # average overall miss latency 869system.cpu.dcache.blocked_cycles::no_mshrs 611 # number of cycles access was blocked 870system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 871system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked 872system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 873system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.545455 # average number of cycles each access was blocked 874system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 875system.cpu.dcache.fast_writes 0 # number of fast writes performed 876system.cpu.dcache.cache_copies 0 # number of cache copies performed 877system.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits 878system.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits 879system.cpu.dcache.WriteReq_mshr_hits::cpu.data 311 # number of WriteReq MSHR hits 880system.cpu.dcache.WriteReq_mshr_hits::total 311 # number of WriteReq MSHR hits 881system.cpu.dcache.demand_mshr_hits::cpu.data 368 # number of demand (read+write) MSHR hits 882system.cpu.dcache.demand_mshr_hits::total 368 # number of demand (read+write) MSHR hits 883system.cpu.dcache.overall_mshr_hits::cpu.data 368 # number of overall MSHR hits 884system.cpu.dcache.overall_mshr_hits::total 368 # number of overall MSHR hits 885system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 886system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses 887system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses 888system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses 889system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 890system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses 891system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 892system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses 893system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7151000 # number of ReadReq MSHR miss cycles 894system.cpu.dcache.ReadReq_mshr_miss_latency::total 7151000 # number of ReadReq MSHR miss cycles 895system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3828249 # number of WriteReq MSHR miss cycles 896system.cpu.dcache.WriteReq_mshr_miss_latency::total 3828249 # number of WriteReq MSHR miss cycles 897system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10979249 # number of demand (read+write) MSHR miss cycles 898system.cpu.dcache.demand_mshr_miss_latency::total 10979249 # number of demand (read+write) MSHR miss cycles 899system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10979249 # number of overall MSHR miss cycles 900system.cpu.dcache.overall_mshr_miss_latency::total 10979249 # number of overall MSHR miss cycles 901system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045960 # mshr miss rate for ReadReq accesses 902system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045960 # mshr miss rate for ReadReq accesses 903system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses 904system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses 905system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for demand accesses 906system.cpu.dcache.demand_mshr_miss_rate::total 0.048881 # mshr miss rate for demand accesses 907system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for overall accesses 908system.cpu.dcache.overall_mshr_miss_rate::total 0.048881 # mshr miss rate for overall accesses 909system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78582.417582 # average ReadReq mshr miss latency 910system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78582.417582 # average ReadReq mshr miss latency 911system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75063.705882 # average WriteReq mshr miss latency 912system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75063.705882 # average WriteReq mshr miss latency 913system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77318.654930 # average overall mshr miss latency 914system.cpu.dcache.demand_avg_mshr_miss_latency::total 77318.654930 # average overall mshr miss latency 915system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77318.654930 # average overall mshr miss latency 916system.cpu.dcache.overall_avg_mshr_miss_latency::total 77318.654930 # average overall mshr miss latency 917system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 918 919---------- End Simulation Statistics ---------- 920