stats.txt revision 9797
16039SN/A 26039SN/A---------- Begin Simulation Statistics ---------- 39729Sandreas.hansson@arm.comsim_seconds 0.000022 # Number of seconds simulated 49797Sandreas.hansson@arm.comsim_ticks 21805500 # Number of ticks simulated 59797Sandreas.hansson@arm.comfinal_tick 21805500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79797Sandreas.hansson@arm.comhost_inst_rate 79844 # Simulator instruction rate (inst/s) 89797Sandreas.hansson@arm.comhost_op_rate 79828 # Simulator op (including micro ops) rate (op/s) 99797Sandreas.hansson@arm.comhost_tick_rate 337538221 # Simulator tick rate (ticks/s) 109797Sandreas.hansson@arm.comhost_mem_usage 228256 # Number of bytes of host memory used 119797Sandreas.hansson@arm.comhost_seconds 0.06 # Real time elapsed on the host 129150SAli.Saidi@ARM.comsim_insts 5156 # Number of instructions simulated 139150SAli.Saidi@ARM.comsim_ops 5156 # Number of ops (including micro ops) simulated 149797Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory 159490Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory 169797Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 30528 # Number of bytes read from this memory 179797Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory 189797Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory 199797Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory 209490Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory 219797Sandreas.hansson@arm.comsystem.physmem.num_reads::total 477 # Number of read requests responded to by this memory 229797Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 983238174 # Total read bandwidth from this memory (bytes/s) 239797Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 416775584 # Total read bandwidth from this memory (bytes/s) 249797Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1400013758 # Total read bandwidth from this memory (bytes/s) 259797Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 983238174 # Instruction read bandwidth from this memory (bytes/s) 269797Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 983238174 # Instruction read bandwidth from this memory (bytes/s) 279797Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 983238174 # Total bandwidth to/from this memory (bytes/s) 289797Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 416775584 # Total bandwidth to/from this memory (bytes/s) 299797Sandreas.hansson@arm.comsystem.physmem.bw_total::total 1400013758 # Total bandwidth to/from this memory (bytes/s) 309797Sandreas.hansson@arm.comsystem.physmem.readReqs 477 # Total number of read requests seen 319312Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Total number of write requests seen 329797Sandreas.hansson@arm.comsystem.physmem.cpureqs 477 # Reqs generatd by CPU via cache - shady 339797Sandreas.hansson@arm.comsystem.physmem.bytesRead 30528 # Total number of bytes read from memory 349312Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to memory 359797Sandreas.hansson@arm.comsystem.physmem.bytesConsumedRd 30528 # bytesRead derated as per pkt->getSize() 369312Sandreas.hansson@arm.comsystem.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 379312Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 389312Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 399729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::0 30 # Track reads on a per bank basis 409729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis 419729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::2 1 # Track reads on a per bank basis 429729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis 439729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::4 7 # Track reads on a per bank basis 449729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::5 3 # Track reads on a per bank basis 459729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::6 13 # Track reads on a per bank basis 469729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::7 54 # Track reads on a per bank basis 479797Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::8 63 # Track reads on a per bank basis 489729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::9 77 # Track reads on a per bank basis 499729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::10 44 # Track reads on a per bank basis 509729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::11 20 # Track reads on a per bank basis 519729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::12 51 # Track reads on a per bank basis 529729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::13 29 # Track reads on a per bank basis 539729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::14 77 # Track reads on a per bank basis 549729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis 559312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 569312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 579312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 589312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 599312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 609312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 619312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 629312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 639312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 649312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 659312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 669312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 679312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 689312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 699312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 709312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 719312Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 729312Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 739797Sandreas.hansson@arm.comsystem.physmem.totGap 21726000 # Total gap between requests 749312Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Categorize read packet sizes 759312Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Categorize read packet sizes 769312Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Categorize read packet sizes 779312Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Categorize read packet sizes 789312Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Categorize read packet sizes 799312Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Categorize read packet sizes 809797Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 477 # Categorize read packet sizes 819568Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Categorize write packet sizes 829568Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Categorize write packet sizes 839568Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Categorize write packet sizes 849568Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Categorize write packet sizes 859568Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Categorize write packet sizes 869568Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Categorize write packet sizes 879568Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Categorize write packet sizes 889797Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 283 # What read queue length does an incoming req see 899797Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see 909797Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see 919729Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see 929729Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 939322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 949312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 959312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 969312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 979312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 989312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 999312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1009312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1019312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1029312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1039312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1049312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1059312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1069312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 1529729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 103 # Bytes accessed per row activation 1539797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 241.708738 # Bytes accessed per row activation 1549797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 156.390708 # Bytes accessed per row activation 1559797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 303.503517 # Bytes accessed per row activation 1569729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::64 39 37.86% 37.86% # Bytes accessed per row activation 1579729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128 15 14.56% 52.43% # Bytes accessed per row activation 1589729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::192 16 15.53% 67.96% # Bytes accessed per row activation 1599729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256 7 6.80% 74.76% # Bytes accessed per row activation 1609729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::320 8 7.77% 82.52% # Bytes accessed per row activation 1619797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384 3 2.91% 85.44% # Bytes accessed per row activation 1629797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::448 3 2.91% 88.35% # Bytes accessed per row activation 1639729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512 1 0.97% 89.32% # Bytes accessed per row activation 1649729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::576 4 3.88% 93.20% # Bytes accessed per row activation 1659729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::704 1 0.97% 94.17% # Bytes accessed per row activation 1669729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::832 2 1.94% 96.12% # Bytes accessed per row activation 1679729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::960 1 0.97% 97.09% # Bytes accessed per row activation 1689729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024 2 1.94% 99.03% # Bytes accessed per row activation 1699729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2368 1 0.97% 100.00% # Bytes accessed per row activation 1709729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 103 # Bytes accessed per row activation 1719797Sandreas.hansson@arm.comsystem.physmem.totQLat 2353250 # Total cycles spent in queuing delays 1729797Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 13414500 # Sum of mem lat for all requests 1739797Sandreas.hansson@arm.comsystem.physmem.totBusLat 2385000 # Total cycles spent in databus access 1749729Sandreas.hansson@arm.comsystem.physmem.totBankLat 8676250 # Total cycles spent in bank access 1759797Sandreas.hansson@arm.comsystem.physmem.avgQLat 4933.44 # Average queueing delay per request 1769797Sandreas.hansson@arm.comsystem.physmem.avgBankLat 18189.20 # Average bank access latency per request 1779490Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per request 1789797Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 28122.64 # Average memory access latency 1799797Sandreas.hansson@arm.comsystem.physmem.avgRdBW 1400.01 # Average achieved read bandwidth in MB/s 1809312Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 1819797Sandreas.hansson@arm.comsystem.physmem.avgConsumedRdBW 1400.01 # Average consumed read bandwidth in MB/s 1829312Sandreas.hansson@arm.comsystem.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 1839490Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 1849797Sandreas.hansson@arm.comsystem.physmem.busUtil 10.94 # Data bus utilization in percentage 1859729Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 0.62 # Average read queue length over time 1869312Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length over time 1879797Sandreas.hansson@arm.comsystem.physmem.readRowHits 374 # Number of row buffer hits during reads 1889312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 1899797Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 78.41 # Row buffer hit rate for reads 1909312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 1919797Sandreas.hansson@arm.comsystem.physmem.avgGap 45547.17 # Average gap between requests 1929797Sandreas.hansson@arm.comsystem.membus.throughput 1400013758 # Throughput (bytes/s) 1939797Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 426 # Transaction distribution 1949797Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 426 # Transaction distribution 1959729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 51 # Transaction distribution 1969729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 51 # Transaction distribution 1979797Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side 954 # Packet count per connected master and slave (bytes) 1989797Sandreas.hansson@arm.comsystem.membus.pkt_count 954 # Packet count per connected master and slave (bytes) 1999797Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side 30528 # Cumulative packet size per connected master and slave (bytes) 2009797Sandreas.hansson@arm.comsystem.membus.tot_pkt_size 30528 # Cumulative packet size per connected master and slave (bytes) 2019797Sandreas.hansson@arm.comsystem.membus.data_through_bus 30528 # Total data (bytes) 2029729Sandreas.hansson@arm.comsystem.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 2039797Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks) 2049797Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 2.8 # Layer utilization (%) 2059797Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 4480000 # Layer occupancy (ticks) 2069797Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 20.5 # Layer utilization (%) 2079797Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 2187 # Number of BP lookups 2089797Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 1490 # Number of conditional branches predicted 2099729Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 438 # Number of conditional branches incorrect 2109797Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 1664 # Number of BTB lookups 2119797Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 502 # Number of BTB hits 2129481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 2139797Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 30.168269 # BTB Hit Percentage 2149797Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 261 # Number of times the RAS was used to get a target. 2159797Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 67 # Number of incorrect RAS predictions. 2168428SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 2178428SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 2188428SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 2198428SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 2208428SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 2218428SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 2226039SN/Asystem.cpu.dtb.hits 0 # DTB hits 2236039SN/Asystem.cpu.dtb.misses 0 # DTB misses 2248428SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 2258428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 2268428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 2278428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 2288428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 2298428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 2308428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 2318428SN/Asystem.cpu.itb.hits 0 # DTB hits 2328428SN/Asystem.cpu.itb.misses 0 # DTB misses 2338428SN/Asystem.cpu.itb.accesses 0 # DTB accesses 2348428SN/Asystem.cpu.workload.num_syscalls 8 # Number of system calls 2359797Sandreas.hansson@arm.comsystem.cpu.numCycles 43612 # number of cpu cycles simulated 2368428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2378428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 2389797Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 8859 # Number of cycles fetch is stalled on an Icache miss 2399797Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 13212 # Number of instructions fetch has processed 2409797Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 2187 # Number of branches that fetch encountered 2419797Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 763 # Number of branches that fetch has predicted taken 2429797Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 3230 # Number of cycles fetch has run and was not squashing or blocked 2439797Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 1384 # Number of cycles fetch has spent squashing 2449797Sandreas.hansson@arm.comsystem.cpu.fetch.BlockedCycles 1326 # Number of cycles fetch has spent blocked 2459322Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps 2469797Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 1985 # Number of cache lines fetched 2479797Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 280 # Number of outstanding Icache misses that were squashed 2489797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 14475 # Number of instructions fetched each cycle (Total) 2499797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 0.912746 # Number of instructions fetched each cycle (Total) 2509797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 2.223376 # Number of instructions fetched each cycle (Total) 2516291SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 2529797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 11245 77.69% 77.69% # Number of instructions fetched each cycle (Total) 2539797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 1331 9.20% 86.88% # Number of instructions fetched each cycle (Total) 2549729Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 104 0.72% 87.60% # Number of instructions fetched each cycle (Total) 2559797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 131 0.91% 88.50% # Number of instructions fetched each cycle (Total) 2569797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 305 2.11% 90.61% # Number of instructions fetched each cycle (Total) 2579797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 118 0.82% 91.43% # Number of instructions fetched each cycle (Total) 2589797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 150 1.04% 92.46% # Number of instructions fetched each cycle (Total) 2599797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 158 1.09% 93.55% # Number of instructions fetched each cycle (Total) 2609797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 933 6.45% 100.00% # Number of instructions fetched each cycle (Total) 2616291SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 2626291SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 2636291SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 2649797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 14475 # Number of instructions fetched each cycle (Total) 2659797Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.050147 # Number of branch fetches per cycle 2669797Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.302944 # Number of inst fetches per cycle 2679797Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 8926 # Number of cycles decode is idle 2689797Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 1578 # Number of cycles decode is blocked 2699797Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 3043 # Number of cycles decode is running 2709729Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 53 # Number of cycles decode is unblocking 2719797Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 875 # Number of cycles decode is squashing 2729797Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 167 # Number of times decode resolved a branch 2739797Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction 2749797Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 12329 # Number of instructions handled by decode 2759490Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode 2769797Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 875 # Number of cycles rename is squashing 2779797Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 9108 # Number of cycles rename is idle 2789797Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 527 # Number of cycles rename is blocking 2799797Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 901 # count of cycles rename stalled for serializing inst 2809797Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 2916 # Number of cycles rename is running 2819729Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 148 # Number of cycles rename is unblocking 2829797Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 11899 # Number of instructions processed by rename 2839729Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full 2849490Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full 2859729Sandreas.hansson@arm.comsystem.cpu.rename.LSQFullEvents 124 # Number of times rename has blocked due to LSQ full 2869797Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 7186 # Number of destination operands rename has renamed 2879797Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 14116 # Number of register rename lookups that rename has made 2889797Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 14112 # Number of integer rename lookups 2898554SN/Asystem.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups 2909150SAli.Saidi@ARM.comsystem.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed 2919797Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 3788 # Number of HB maps that are undone due to squashing 2929797Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 16 # count of serializing insts renamed 2939797Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed 2949797Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 328 # count of insts added to the skid buffer 2959797Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 2460 # Number of loads inserted to the mem dependence unit. 2969729Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 1193 # Number of stores inserted to the mem dependence unit. 2978428SN/Asystem.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 2988428SN/Asystem.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. 2999797Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 9226 # Number of instructions added to the IQ (excludes non-spec) 3009729Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ 3019797Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 8306 # Number of instructions issued 3029797Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued 3039797Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 3428 # Number of squashed instructions iterated over during squash; mainly for profiling 3049797Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 2082 # Number of squashed operands that are examined and possibly removed from graph 3059729Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed 3069797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 14475 # Number of insts issued each cycle 3079797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.573817 # Number of insts issued each cycle 3089797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.241522 # Number of insts issued each cycle 3098428SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 3109797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 10881 75.17% 75.17% # Number of insts issued each cycle 3119797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 1431 9.89% 85.06% # Number of insts issued each cycle 3129797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 893 6.17% 91.23% # Number of insts issued each cycle 3139797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 553 3.82% 95.05% # Number of insts issued each cycle 3149797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 356 2.46% 97.51% # Number of insts issued each cycle 3159797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 225 1.55% 99.06% # Number of insts issued each cycle 3169797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 88 0.61% 99.67% # Number of insts issued each cycle 3179797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 31 0.21% 99.88% # Number of insts issued each cycle 3189729Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 17 0.12% 100.00% # Number of insts issued each cycle 3198428SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 3208428SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 3218428SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 3229797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 14475 # Number of insts issued each cycle 3238428SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 3249797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 5 3.12% 3.12% # attempts to use FU when none available 3259797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available 3269797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available 3279797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available 3289797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 3.12% # attempts to use FU when none available 3299797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 3.12% # attempts to use FU when none available 3309797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 3.12% # attempts to use FU when none available 3319797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 3.12% # attempts to use FU when none available 3329797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.12% # attempts to use FU when none available 3339797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 3.12% # attempts to use FU when none available 3349797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.12% # attempts to use FU when none available 3359797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 3.12% # attempts to use FU when none available 3369797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 3.12% # attempts to use FU when none available 3379797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 3.12% # attempts to use FU when none available 3389797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 3.12% # attempts to use FU when none available 3399797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 3.12% # attempts to use FU when none available 3409797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.12% # attempts to use FU when none available 3419797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 3.12% # attempts to use FU when none available 3429797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.12% # attempts to use FU when none available 3439797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.12% # attempts to use FU when none available 3449797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.12% # attempts to use FU when none available 3459797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.12% # attempts to use FU when none available 3469797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.12% # attempts to use FU when none available 3479797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.12% # attempts to use FU when none available 3489797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.12% # attempts to use FU when none available 3499797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.12% # attempts to use FU when none available 3509797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available 3519797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available 3529797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available 3539797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 101 63.12% 66.25% # attempts to use FU when none available 3549797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 54 33.75% 100.00% # attempts to use FU when none available 3558428SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 3568428SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 3578241SN/Asystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 3589797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 4943 59.51% 59.51% # Type of FU issued 3599729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 5 0.06% 59.57% # Type of FU issued 3609797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.60% # Type of FU issued 3619729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.62% # Type of FU issued 3629729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.62% # Type of FU issued 3639729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.62% # Type of FU issued 3649729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.62% # Type of FU issued 3659729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.62% # Type of FU issued 3669729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.62% # Type of FU issued 3679729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.62% # Type of FU issued 3689729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.62% # Type of FU issued 3699729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.62% # Type of FU issued 3709729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.62% # Type of FU issued 3719729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.62% # Type of FU issued 3729729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.62% # Type of FU issued 3739729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.62% # Type of FU issued 3749729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.62% # Type of FU issued 3759729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.62% # Type of FU issued 3769729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.62% # Type of FU issued 3779729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.62% # Type of FU issued 3789729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.62% # Type of FU issued 3799729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.62% # Type of FU issued 3809729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.62% # Type of FU issued 3819729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.62% # Type of FU issued 3829729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.62% # Type of FU issued 3839729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.62% # Type of FU issued 3849729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.62% # Type of FU issued 3859729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.62% # Type of FU issued 3869729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.62% # Type of FU issued 3879797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 2250 27.09% 86.71% # Type of FU issued 3889797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 1104 13.29% 100.00% # Type of FU issued 3898241SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 3908241SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 3919797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 8306 # Type of FU issued 3929797Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.190452 # Inst issue rate 3939797Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 160 # FU busy when requested 3949797Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.019263 # FU busy rate (busy events/executed inst) 3959797Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 31282 # Number of integer instruction queue reads 3969797Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 12675 # Number of integer instruction queue writes 3979797Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 7463 # Number of integer instruction queue wakeup accesses 3988428SN/Asystem.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads 3998428SN/Asystem.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 4008428SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses 4019797Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 8464 # Number of integer alu accesses 4028428SN/Asystem.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses 4039729Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores 4048428SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 4059797Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1297 # Number of loads squashed 4069322Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed 4079490Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations 4089729Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 268 # Number of stores squashed 4098428SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 4108428SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 4118428SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 4129797Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 35 # Number of times an access to memory failed due to the cache being blocked 4138428SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 4149797Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 875 # Number of cycles IEW is squashing 4159797Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 349 # Number of cycles IEW is blocking 4169797Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking 4179797Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 10763 # Number of instructions dispatched to IQ 4189797Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 93 # Number of squashed instructions skipped by dispatch 4199797Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 2460 # Number of dispatched load instructions 4209729Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 1193 # Number of dispatched store instructions 4219729Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions 4229797Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall 4239322Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 4249490Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations 4259797Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly 4269797Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 362 # Number of branches that were predicted not taken incorrectly 4279797Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 463 # Number of branch mispredicts detected at execute 4289797Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 7925 # Number of executed instructions 4299797Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 2110 # Number of load instructions executed 4309797Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 381 # Number of squashed instructions skipped in execute 4318428SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 4329797Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 1525 # number of nop insts executed 4339797Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 3189 # number of memory reference insts executed 4349797Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 1354 # Number of branches executed 4359797Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 1079 # Number of stores executed 4369797Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.181716 # Inst execution rate 4379797Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 7555 # cumulative count of insts sent to commit 4389797Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 7465 # cumulative count of insts written-back 4399797Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 2921 # num instructions producing a value 4409797Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 4197 # num instructions consuming a value 4418428SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 4429797Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.171168 # insts written-back per cycle 4439797Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.695973 # average fanout of values written-back 4448428SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 4459797Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 4943 # The number of squashed insts skipped by commit 4468428SN/Asystem.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards 4479797Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted 4489797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 13600 # Number of insts commited each cycle 4499797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.427426 # Number of insts commited each cycle 4509797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.207995 # Number of insts commited each cycle 4518428SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 4529797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 11198 82.34% 82.34% # Number of insts commited each cycle 4539797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 999 7.35% 89.68% # Number of insts commited each cycle 4549797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 630 4.63% 94.32% # Number of insts commited each cycle 4559797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 315 2.32% 96.63% # Number of insts commited each cycle 4569797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 149 1.10% 97.73% # Number of insts commited each cycle 4579797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 94 0.69% 98.42% # Number of insts commited each cycle 4589797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 68 0.50% 98.92% # Number of insts commited each cycle 4599797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 41 0.30% 99.22% # Number of insts commited each cycle 4609729Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 106 0.78% 100.00% # Number of insts commited each cycle 4618428SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 4628428SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 4638428SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 4649797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 13600 # Number of insts commited each cycle 4659150SAli.Saidi@ARM.comsystem.cpu.commit.committedInsts 5813 # Number of instructions committed 4669150SAli.Saidi@ARM.comsystem.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed 4678428SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 4689150SAli.Saidi@ARM.comsystem.cpu.commit.refs 2088 # Number of memory references committed 4699150SAli.Saidi@ARM.comsystem.cpu.commit.loads 1163 # Number of loads committed 4708428SN/Asystem.cpu.commit.membars 0 # Number of memory barriers committed 4719150SAli.Saidi@ARM.comsystem.cpu.commit.branches 915 # Number of branches committed 4728428SN/Asystem.cpu.commit.fp_insts 2 # Number of committed floating point instructions. 4739150SAli.Saidi@ARM.comsystem.cpu.commit.int_insts 5111 # Number of committed integer instructions. 4748428SN/Asystem.cpu.commit.function_calls 87 # Number of function calls committed. 4759729Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached 4768428SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 4779797Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 24237 # The number of ROB reads 4789797Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 22398 # The number of ROB writes 4799797Sandreas.hansson@arm.comsystem.cpu.timesIdled 285 # Number of times that the entire CPU went into an idle state and unscheduled itself 4809797Sandreas.hansson@arm.comsystem.cpu.idleCycles 29137 # Total number of cycles that the CPU has spent unscheduled due to idling 4819150SAli.Saidi@ARM.comsystem.cpu.committedInsts 5156 # Number of Instructions Simulated 4829150SAli.Saidi@ARM.comsystem.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated 4839150SAli.Saidi@ARM.comsystem.cpu.committedInsts_total 5156 # Number of Instructions Simulated 4849797Sandreas.hansson@arm.comsystem.cpu.cpi 8.458495 # CPI: Cycles Per Instruction 4859797Sandreas.hansson@arm.comsystem.cpu.cpi_total 8.458495 # CPI: Total CPI of All Threads 4869797Sandreas.hansson@arm.comsystem.cpu.ipc 0.118224 # IPC: Instructions Per Cycle 4879797Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.118224 # IPC: Total IPC of All Threads 4889797Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 10746 # number of integer regfile reads 4899797Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 5233 # number of integer regfile writes 4908428SN/Asystem.cpu.fp_regfile_reads 3 # number of floating regfile reads 4918428SN/Asystem.cpu.fp_regfile_writes 1 # number of floating regfile writes 4929729Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 148 # number of misc regfile reads 4939797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.throughput 1408818876 # Throughput (bytes/s) 4949797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 429 # Transaction distribution 4959797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 429 # Transaction distribution 4969729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution 4979729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution 4989797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 676 # Packet count per connected master and slave (bytes) 4999729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 284 # Packet count per connected master and slave (bytes) 5009797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count 960 # Packet count per connected master and slave (bytes) 5019797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 21632 # Cumulative packet size per connected master and slave (bytes) 5029729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9088 # Cumulative packet size per connected master and slave (bytes) 5039797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size 30720 # Cumulative packet size per connected master and slave (bytes) 5049797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.data_through_bus 30720 # Total data (bytes) 5059729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 5069797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks) 5079729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 5089797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 573500 # Layer occupancy (ticks) 5099797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) 5109797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 230000 # Layer occupancy (ticks) 5119797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) 5129797Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 17 # number of replacements 5139797Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 160.845390 # Cycle average of tags in use 5149797Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 1531 # Total number of references to valid blocks. 5159797Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks. 5169797Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 4.529586 # Average number of references to valid blocks. 5179797Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 5189797Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 160.845390 # Average occupied blocks per requestor 5199797Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.078538 # Average percentage of cache occupancy 5209797Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.078538 # Average percentage of cache occupancy 5219797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1531 # number of ReadReq hits 5229797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 1531 # number of ReadReq hits 5239797Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 1531 # number of demand (read+write) hits 5249797Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 1531 # number of demand (read+write) hits 5259797Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 1531 # number of overall hits 5269797Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 1531 # number of overall hits 5279797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 454 # number of ReadReq misses 5289797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 454 # number of ReadReq misses 5299797Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 454 # number of demand (read+write) misses 5309797Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 454 # number of demand (read+write) misses 5319797Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 454 # number of overall misses 5329797Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 454 # number of overall misses 5339797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 31019250 # number of ReadReq miss cycles 5349797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 31019250 # number of ReadReq miss cycles 5359797Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 31019250 # number of demand (read+write) miss cycles 5369797Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 31019250 # number of demand (read+write) miss cycles 5379797Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 31019250 # number of overall miss cycles 5389797Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 31019250 # number of overall miss cycles 5399797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 1985 # number of ReadReq accesses(hits+misses) 5409797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 1985 # number of ReadReq accesses(hits+misses) 5419797Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 1985 # number of demand (read+write) accesses 5429797Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 1985 # number of demand (read+write) accesses 5439797Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 1985 # number of overall (read+write) accesses 5449797Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 1985 # number of overall (read+write) accesses 5459797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.228715 # miss rate for ReadReq accesses 5469797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.228715 # miss rate for ReadReq accesses 5479797Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.228715 # miss rate for demand accesses 5489797Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.228715 # miss rate for demand accesses 5499797Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.228715 # miss rate for overall accesses 5509797Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.228715 # miss rate for overall accesses 5519797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68324.339207 # average ReadReq miss latency 5529797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 68324.339207 # average ReadReq miss latency 5539797Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 68324.339207 # average overall miss latency 5549797Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 68324.339207 # average overall miss latency 5559797Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 68324.339207 # average overall miss latency 5569797Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 68324.339207 # average overall miss latency 5579797Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 47 # number of cycles access was blocked 5588428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5599322Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked 5608428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 5619797Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 47 # average number of cycles each access was blocked 5628983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5638428SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 5648428SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 5659797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 116 # number of ReadReq MSHR hits 5669797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 116 # number of ReadReq MSHR hits 5679797Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 116 # number of demand (read+write) MSHR hits 5689797Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 116 # number of demand (read+write) MSHR hits 5699797Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 116 # number of overall MSHR hits 5709797Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 116 # number of overall MSHR hits 5719797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses 5729797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses 5739797Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses 5749797Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses 5759797Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses 5769797Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses 5779797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23858000 # number of ReadReq MSHR miss cycles 5789797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 23858000 # number of ReadReq MSHR miss cycles 5799797Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 23858000 # number of demand (read+write) MSHR miss cycles 5809797Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 23858000 # number of demand (read+write) MSHR miss cycles 5819797Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 23858000 # number of overall MSHR miss cycles 5829797Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 23858000 # number of overall MSHR miss cycles 5839797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.170277 # mshr miss rate for ReadReq accesses 5849797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.170277 # mshr miss rate for ReadReq accesses 5859797Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.170277 # mshr miss rate for demand accesses 5869797Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.170277 # mshr miss rate for demand accesses 5879797Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.170277 # mshr miss rate for overall accesses 5889797Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.170277 # mshr miss rate for overall accesses 5899797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70585.798817 # average ReadReq mshr miss latency 5909797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70585.798817 # average ReadReq mshr miss latency 5919797Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70585.798817 # average overall mshr miss latency 5929797Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 70585.798817 # average overall mshr miss latency 5939797Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70585.798817 # average overall mshr miss latency 5949797Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 70585.798817 # average overall mshr miss latency 5958428SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 5969797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 5979797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 220.792115 # Cycle average of tags in use 5989797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. 5999797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks. 6009797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 0.007042 # Average number of references to valid blocks. 6019797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 6029797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 163.133804 # Average occupied blocks per requestor 6039797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 57.658310 # Average occupied blocks per requestor 6049797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.004978 # Average percentage of cache occupancy 6059797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.001760 # Average percentage of cache occupancy 6069797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.006738 # Average percentage of cache occupancy 6079348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits 6089348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits 6099348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 6109348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 6119348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 6129348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 3 # number of overall hits 6139797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 335 # number of ReadReq misses 6149490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 91 # number of ReadReq misses 6159797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 426 # number of ReadReq misses 6169348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses 6179348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses 6189797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 335 # number of demand (read+write) misses 6199490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses 6209797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 477 # number of demand (read+write) misses 6219797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses 6229490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses 6239797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 477 # number of overall misses 6249797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23490000 # number of ReadReq miss cycles 6259797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 7101750 # number of ReadReq miss cycles 6269797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 30591750 # number of ReadReq miss cycles 6279797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3862250 # number of ReadExReq miss cycles 6289797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 3862250 # number of ReadExReq miss cycles 6299797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 23490000 # number of demand (read+write) miss cycles 6309797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 10964000 # number of demand (read+write) miss cycles 6319797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 34454000 # number of demand (read+write) miss cycles 6329797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 23490000 # number of overall miss cycles 6339797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 10964000 # number of overall miss cycles 6349797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 34454000 # number of overall miss cycles 6359797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses) 6369490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) 6379797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 429 # number of ReadReq accesses(hits+misses) 6389348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) 6399348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) 6409797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 338 # number of demand (read+write) accesses 6419490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses 6429797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 480 # number of demand (read+write) accesses 6439797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 338 # number of overall (read+write) accesses 6449490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses 6459797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 480 # number of overall (read+write) accesses 6469797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991124 # miss rate for ReadReq accesses 6479348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 6489797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.993007 # miss rate for ReadReq accesses 6499348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 6509348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 6519797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.991124 # miss rate for demand accesses 6529348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 6539797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.993750 # miss rate for demand accesses 6549797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.991124 # miss rate for overall accesses 6559348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 6569797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.993750 # miss rate for overall accesses 6579797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70119.402985 # average ReadReq miss latency 6589797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78041.208791 # average ReadReq miss latency 6599797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 71811.619718 # average ReadReq miss latency 6609797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75730.392157 # average ReadExReq miss latency 6619797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 75730.392157 # average ReadExReq miss latency 6629797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70119.402985 # average overall miss latency 6639797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 77211.267606 # average overall miss latency 6649797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 72230.607966 # average overall miss latency 6659797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70119.402985 # average overall miss latency 6669797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 77211.267606 # average overall miss latency 6679797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 72230.607966 # average overall miss latency 6689348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 6699348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6709348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 6719348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 6729348SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 6739348SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6749348SAli.Saidi@ARM.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 6759348SAli.Saidi@ARM.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 6769797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 335 # number of ReadReq MSHR misses 6779490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 6789797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 426 # number of ReadReq MSHR misses 6799348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses 6809348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses 6819797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 335 # number of demand (read+write) MSHR misses 6829490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 6839797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 477 # number of demand (read+write) MSHR misses 6849797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses 6859490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 6869797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 477 # number of overall MSHR misses 6879797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19249000 # number of ReadReq MSHR miss cycles 6889797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5981750 # number of ReadReq MSHR miss cycles 6899797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 25230750 # number of ReadReq MSHR miss cycles 6909797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3228750 # number of ReadExReq MSHR miss cycles 6919797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3228750 # number of ReadExReq MSHR miss cycles 6929797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19249000 # number of demand (read+write) MSHR miss cycles 6939797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9210500 # number of demand (read+write) MSHR miss cycles 6949797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 28459500 # number of demand (read+write) MSHR miss cycles 6959797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19249000 # number of overall MSHR miss cycles 6969797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9210500 # number of overall MSHR miss cycles 6979797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 28459500 # number of overall MSHR miss cycles 6989797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for ReadReq accesses 6999348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 7009797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993007 # mshr miss rate for ReadReq accesses 7019348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 7029348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 7039797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for demand accesses 7049348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 7059797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.993750 # mshr miss rate for demand accesses 7069797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for overall accesses 7079348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 7089797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.993750 # mshr miss rate for overall accesses 7099797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57459.701493 # average ReadReq mshr miss latency 7109797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65733.516484 # average ReadReq mshr miss latency 7119797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59227.112676 # average ReadReq mshr miss latency 7129797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63308.823529 # average ReadExReq mshr miss latency 7139797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63308.823529 # average ReadExReq mshr miss latency 7149797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57459.701493 # average overall mshr miss latency 7159797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64862.676056 # average overall mshr miss latency 7169797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 59663.522013 # average overall mshr miss latency 7179797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57459.701493 # average overall mshr miss latency 7189797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64862.676056 # average overall mshr miss latency 7199797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 59663.522013 # average overall mshr miss latency 7209348SAli.Saidi@ARM.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 7219797Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 7229797Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 91.308892 # Cycle average of tags in use 7239797Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. 7249797Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. 7259797Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 16.866197 # Average number of references to valid blocks. 7269797Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 7279797Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 91.308892 # Average occupied blocks per requestor 7289797Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.022292 # Average percentage of cache occupancy 7299797Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.022292 # Average percentage of cache occupancy 7309797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1832 # number of ReadReq hits 7319797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 1832 # number of ReadReq hits 7329729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 563 # number of WriteReq hits 7339729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 563 # number of WriteReq hits 7349797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 2395 # number of demand (read+write) hits 7359797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 2395 # number of demand (read+write) hits 7369797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 2395 # number of overall hits 7379797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 2395 # number of overall hits 7389797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 148 # number of ReadReq misses 7399797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 148 # number of ReadReq misses 7409729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 362 # number of WriteReq misses 7419729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 362 # number of WriteReq misses 7429797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 510 # number of demand (read+write) misses 7439797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses 7449797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses 7459797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 510 # number of overall misses 7469797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 10243000 # number of ReadReq miss cycles 7479797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 10243000 # number of ReadReq miss cycles 7489797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 22828749 # number of WriteReq miss cycles 7499797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 22828749 # number of WriteReq miss cycles 7509797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 33071749 # number of demand (read+write) miss cycles 7519797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 33071749 # number of demand (read+write) miss cycles 7529797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 33071749 # number of overall miss cycles 7539797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 33071749 # number of overall miss cycles 7549797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1980 # number of ReadReq accesses(hits+misses) 7559797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 1980 # number of ReadReq accesses(hits+misses) 7568835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 7578835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 7589797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 2905 # number of demand (read+write) accesses 7599797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 2905 # number of demand (read+write) accesses 7609797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 2905 # number of overall (read+write) accesses 7619797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 2905 # number of overall (read+write) accesses 7629797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074747 # miss rate for ReadReq accesses 7639797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.074747 # miss rate for ReadReq accesses 7649729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.391351 # miss rate for WriteReq accesses 7659729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.391351 # miss rate for WriteReq accesses 7669797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.175559 # miss rate for demand accesses 7679797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.175559 # miss rate for demand accesses 7689797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.175559 # miss rate for overall accesses 7699797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.175559 # miss rate for overall accesses 7709797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69209.459459 # average ReadReq miss latency 7719797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 69209.459459 # average ReadReq miss latency 7729797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63062.842541 # average WriteReq miss latency 7739797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 63062.842541 # average WriteReq miss latency 7749797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 64846.566667 # average overall miss latency 7759797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 64846.566667 # average overall miss latency 7769797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 64846.566667 # average overall miss latency 7779797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 64846.566667 # average overall miss latency 7789797Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 635 # number of cycles access was blocked 7798428SN/Asystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 7809322Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked 7818428SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 7829797Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 57.727273 # average number of cycles each access was blocked 7838983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 7848428SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 7858428SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 7869797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits 7879797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits 7889729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 311 # number of WriteReq MSHR hits 7899729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 311 # number of WriteReq MSHR hits 7909797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 368 # number of demand (read+write) MSHR hits 7919797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 368 # number of demand (read+write) MSHR hits 7929797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 368 # number of overall MSHR hits 7939797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 368 # number of overall MSHR hits 7949490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 7959490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses 7968835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses 7978835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses 7989490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 7999490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses 8009490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 8019490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses 8029797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7196250 # number of ReadReq MSHR miss cycles 8039797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 7196250 # number of ReadReq MSHR miss cycles 8049797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3914249 # number of WriteReq MSHR miss cycles 8059797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 3914249 # number of WriteReq MSHR miss cycles 8069797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 11110499 # number of demand (read+write) MSHR miss cycles 8079797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 11110499 # number of demand (read+write) MSHR miss cycles 8089797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 11110499 # number of overall MSHR miss cycles 8099797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 11110499 # number of overall MSHR miss cycles 8109797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045960 # mshr miss rate for ReadReq accesses 8119797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045960 # mshr miss rate for ReadReq accesses 8128835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses 8139055Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses 8149797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for demand accesses 8159797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.048881 # mshr miss rate for demand accesses 8169797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for overall accesses 8179797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.048881 # mshr miss rate for overall accesses 8189797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79079.670330 # average ReadReq mshr miss latency 8199797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79079.670330 # average ReadReq mshr miss latency 8209797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76749.980392 # average WriteReq mshr miss latency 8219797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76749.980392 # average WriteReq mshr miss latency 8229797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78242.950704 # average overall mshr miss latency 8239797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 78242.950704 # average overall mshr miss latency 8249797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78242.950704 # average overall mshr miss latency 8259797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 78242.950704 # average overall mshr miss latency 8268428SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 8276039SN/A 8286039SN/A---------- End Simulation Statistics ---------- 829