stats.txt revision 9348
16039SN/A 26039SN/A---------- Begin Simulation Statistics ---------- 39348SAli.Saidi@ARM.comsim_seconds 0.000017 # Number of seconds simulated 49348SAli.Saidi@ARM.comsim_ticks 16532500 # Number of ticks simulated 59348SAli.Saidi@ARM.comfinal_tick 16532500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79348SAli.Saidi@ARM.comhost_inst_rate 48770 # Simulator instruction rate (inst/s) 89348SAli.Saidi@ARM.comhost_op_rate 48763 # Simulator op (including micro ops) rate (op/s) 99348SAli.Saidi@ARM.comhost_tick_rate 156337427 # Simulator tick rate (ticks/s) 109348SAli.Saidi@ARM.comhost_mem_usage 215260 # Number of bytes of host memory used 119348SAli.Saidi@ARM.comhost_seconds 0.11 # Real time elapsed on the host 129150SAli.Saidi@ARM.comsim_insts 5156 # Number of instructions simulated 139150SAli.Saidi@ARM.comsim_ops 5156 # Number of ops (including micro ops) simulated 149348SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory 159096Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory 169348SAli.Saidi@ARM.comsystem.physmem.bytes_read::total 30464 # Number of bytes read from this memory 179348SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory 189348SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory 199348SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory 209096Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory 219348SAli.Saidi@ARM.comsystem.physmem.num_reads::total 476 # Number of read requests responded to by this memory 229348SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.inst 1296839558 # Total read bandwidth from this memory (bytes/s) 239348SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.data 545833963 # Total read bandwidth from this memory (bytes/s) 249348SAli.Saidi@ARM.comsystem.physmem.bw_read::total 1842673522 # Total read bandwidth from this memory (bytes/s) 259348SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::cpu.inst 1296839558 # Instruction read bandwidth from this memory (bytes/s) 269348SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::total 1296839558 # Instruction read bandwidth from this memory (bytes/s) 279348SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.inst 1296839558 # Total bandwidth to/from this memory (bytes/s) 289348SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.data 545833963 # Total bandwidth to/from this memory (bytes/s) 299348SAli.Saidi@ARM.comsystem.physmem.bw_total::total 1842673522 # Total bandwidth to/from this memory (bytes/s) 309348SAli.Saidi@ARM.comsystem.physmem.readReqs 476 # Total number of read requests seen 319312Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Total number of write requests seen 329348SAli.Saidi@ARM.comsystem.physmem.cpureqs 476 # Reqs generatd by CPU via cache - shady 339348SAli.Saidi@ARM.comsystem.physmem.bytesRead 30464 # Total number of bytes read from memory 349312Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to memory 359348SAli.Saidi@ARM.comsystem.physmem.bytesConsumedRd 30464 # bytesRead derated as per pkt->getSize() 369312Sandreas.hansson@arm.comsystem.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 379312Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 389312Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 399312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::0 64 # Track reads on a per bank basis 409312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::1 30 # Track reads on a per bank basis 419312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::2 23 # Track reads on a per bank basis 429312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::3 54 # Track reads on a per bank basis 439312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::4 6 # Track reads on a per bank basis 449348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::5 38 # Track reads on a per bank basis 459312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis 469312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::7 20 # Track reads on a per bank basis 479312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::8 40 # Track reads on a per bank basis 489312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::9 18 # Track reads on a per bank basis 499312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::10 15 # Track reads on a per bank basis 509312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::11 17 # Track reads on a per bank basis 519312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::12 40 # Track reads on a per bank basis 529348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::13 50 # Track reads on a per bank basis 539312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::14 32 # Track reads on a per bank basis 549348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::15 29 # Track reads on a per bank basis 559312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 569312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 579312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 589312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 599312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 609312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 619312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 629312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 639312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 649312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 659312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 669312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 679312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 689312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 699312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 709312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 719312Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 729312Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 739348SAli.Saidi@ARM.comsystem.physmem.totGap 16452500 # Total gap between requests 749312Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Categorize read packet sizes 759312Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Categorize read packet sizes 769312Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Categorize read packet sizes 779312Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Categorize read packet sizes 789312Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Categorize read packet sizes 799312Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Categorize read packet sizes 809348SAli.Saidi@ARM.comsystem.physmem.readPktSize::6 476 # Categorize read packet sizes 819312Sandreas.hansson@arm.comsystem.physmem.readPktSize::7 0 # Categorize read packet sizes 829312Sandreas.hansson@arm.comsystem.physmem.readPktSize::8 0 # Categorize read packet sizes 839312Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # categorize write packet sizes 849312Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # categorize write packet sizes 859312Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # categorize write packet sizes 869312Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # categorize write packet sizes 879312Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # categorize write packet sizes 889312Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # categorize write packet sizes 899312Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # categorize write packet sizes 909312Sandreas.hansson@arm.comsystem.physmem.writePktSize::7 0 # categorize write packet sizes 919312Sandreas.hansson@arm.comsystem.physmem.writePktSize::8 0 # categorize write packet sizes 929312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::0 0 # categorize neither packet sizes 939312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::1 0 # categorize neither packet sizes 949312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::2 0 # categorize neither packet sizes 959312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::3 0 # categorize neither packet sizes 969312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::4 0 # categorize neither packet sizes 979312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::5 0 # categorize neither packet sizes 989312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::6 0 # categorize neither packet sizes 999312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::7 0 # categorize neither packet sizes 1009312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::8 0 # categorize neither packet sizes 1019348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::0 257 # What read queue length does an incoming req see 1029348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see 1039348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::2 49 # What read queue length does an incoming req see 1049348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see 1059348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see 1069322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1579312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1589312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1599312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1609312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1619312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1629312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1639312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1649312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1659312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 1669312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 1679348SAli.Saidi@ARM.comsystem.physmem.totQLat 2527972 # Total cycles spent in queuing delays 1689348SAli.Saidi@ARM.comsystem.physmem.totMemAccLat 13083972 # Sum of mem lat for all requests 1699348SAli.Saidi@ARM.comsystem.physmem.totBusLat 1904000 # Total cycles spent in databus access 1709348SAli.Saidi@ARM.comsystem.physmem.totBankLat 8652000 # Total cycles spent in bank access 1719348SAli.Saidi@ARM.comsystem.physmem.avgQLat 5310.87 # Average queueing delay per request 1729348SAli.Saidi@ARM.comsystem.physmem.avgBankLat 18176.47 # Average bank access latency per request 1739312Sandreas.hansson@arm.comsystem.physmem.avgBusLat 4000.00 # Average bus latency per request 1749348SAli.Saidi@ARM.comsystem.physmem.avgMemAccLat 27487.34 # Average memory access latency 1759348SAli.Saidi@ARM.comsystem.physmem.avgRdBW 1842.67 # Average achieved read bandwidth in MB/s 1769312Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 1779348SAli.Saidi@ARM.comsystem.physmem.avgConsumedRdBW 1842.67 # Average consumed read bandwidth in MB/s 1789312Sandreas.hansson@arm.comsystem.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 1799312Sandreas.hansson@arm.comsystem.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 1809348SAli.Saidi@ARM.comsystem.physmem.busUtil 11.52 # Data bus utilization in percentage 1819322Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 0.79 # Average read queue length over time 1829312Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length over time 1839348SAli.Saidi@ARM.comsystem.physmem.readRowHits 376 # Number of row buffer hits during reads 1849312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 1859348SAli.Saidi@ARM.comsystem.physmem.readRowHitRate 78.99 # Row buffer hit rate for reads 1869312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 1879348SAli.Saidi@ARM.comsystem.physmem.avgGap 34564.08 # Average gap between requests 1888428SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 1898428SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 1908428SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 1918428SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 1928428SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 1938428SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 1946039SN/Asystem.cpu.dtb.hits 0 # DTB hits 1956039SN/Asystem.cpu.dtb.misses 0 # DTB misses 1968428SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 1978428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 1988428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 1998428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 2008428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 2018428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 2028428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 2038428SN/Asystem.cpu.itb.hits 0 # DTB hits 2048428SN/Asystem.cpu.itb.misses 0 # DTB misses 2058428SN/Asystem.cpu.itb.accesses 0 # DTB accesses 2068428SN/Asystem.cpu.workload.num_syscalls 8 # Number of system calls 2079348SAli.Saidi@ARM.comsystem.cpu.numCycles 33066 # number of cpu cycles simulated 2088428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2098428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 2109348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.lookups 2120 # Number of BP lookups 2119348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.condPredicted 1453 # Number of conditional branches predicted 2129348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.condIncorrect 419 # Number of conditional branches incorrect 2139348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.BTBLookups 1651 # Number of BTB lookups 2149348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.BTBHits 517 # Number of BTB hits 2158428SN/Asystem.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 2169348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.usedRAS 258 # Number of times the RAS was used to get a target. 2179322Sandreas.hansson@arm.comsystem.cpu.BPredUnit.RASInCorrect 68 # Number of incorrect RAS predictions. 2189348SAli.Saidi@ARM.comsystem.cpu.fetch.icacheStallCycles 8641 # Number of cycles fetch is stalled on an Icache miss 2199348SAli.Saidi@ARM.comsystem.cpu.fetch.Insts 12896 # Number of instructions fetch has processed 2209348SAli.Saidi@ARM.comsystem.cpu.fetch.Branches 2120 # Number of branches that fetch encountered 2219348SAli.Saidi@ARM.comsystem.cpu.fetch.predictedBranches 775 # Number of branches that fetch has predicted taken 2229348SAli.Saidi@ARM.comsystem.cpu.fetch.Cycles 3199 # Number of cycles fetch has run and was not squashing or blocked 2239348SAli.Saidi@ARM.comsystem.cpu.fetch.SquashCycles 1339 # Number of cycles fetch has spent squashing 2249348SAli.Saidi@ARM.comsystem.cpu.fetch.BlockedCycles 1070 # Number of cycles fetch has spent blocked 2258464SN/Asystem.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 2269322Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps 2279348SAli.Saidi@ARM.comsystem.cpu.fetch.CacheLines 1948 # Number of cache lines fetched 2289348SAli.Saidi@ARM.comsystem.cpu.fetch.IcacheSquashes 270 # Number of outstanding Icache misses that were squashed 2299348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::samples 13947 # Number of instructions fetched each cycle (Total) 2309348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::mean 0.924643 # Number of instructions fetched each cycle (Total) 2319348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::stdev 2.229674 # Number of instructions fetched each cycle (Total) 2326291SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 2339348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::0 10748 77.06% 77.06% # Number of instructions fetched each cycle (Total) 2349348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::1 1351 9.69% 86.75% # Number of instructions fetched each cycle (Total) 2359348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::2 103 0.74% 87.49% # Number of instructions fetched each cycle (Total) 2369348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::3 137 0.98% 88.47% # Number of instructions fetched each cycle (Total) 2379348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::4 291 2.09% 90.56% # Number of instructions fetched each cycle (Total) 2389348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::5 93 0.67% 91.22% # Number of instructions fetched each cycle (Total) 2399348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::6 169 1.21% 92.44% # Number of instructions fetched each cycle (Total) 2409348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::7 155 1.11% 93.55% # Number of instructions fetched each cycle (Total) 2419348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::8 900 6.45% 100.00% # Number of instructions fetched each cycle (Total) 2426291SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 2436291SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 2446291SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 2459348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::total 13947 # Number of instructions fetched each cycle (Total) 2469348SAli.Saidi@ARM.comsystem.cpu.fetch.branchRate 0.064114 # Number of branch fetches per cycle 2479348SAli.Saidi@ARM.comsystem.cpu.fetch.rate 0.390008 # Number of inst fetches per cycle 2489348SAli.Saidi@ARM.comsystem.cpu.decode.IdleCycles 8777 # Number of cycles decode is idle 2499348SAli.Saidi@ARM.comsystem.cpu.decode.BlockedCycles 1236 # Number of cycles decode is blocked 2509348SAli.Saidi@ARM.comsystem.cpu.decode.RunCycles 3037 # Number of cycles decode is running 2519348SAli.Saidi@ARM.comsystem.cpu.decode.UnblockCycles 46 # Number of cycles decode is unblocking 2529348SAli.Saidi@ARM.comsystem.cpu.decode.SquashCycles 851 # Number of cycles decode is squashing 2539348SAli.Saidi@ARM.comsystem.cpu.decode.BranchResolved 137 # Number of times decode resolved a branch 2549348SAli.Saidi@ARM.comsystem.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction 2559322Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 12081 # Number of instructions handled by decode 2569348SAli.Saidi@ARM.comsystem.cpu.decode.SquashedInsts 166 # Number of squashed instructions handled by decode 2579348SAli.Saidi@ARM.comsystem.cpu.rename.SquashCycles 851 # Number of cycles rename is squashing 2589348SAli.Saidi@ARM.comsystem.cpu.rename.IdleCycles 8957 # Number of cycles rename is idle 2599348SAli.Saidi@ARM.comsystem.cpu.rename.BlockCycles 360 # Number of cycles rename is blocking 2609322Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 762 # count of cycles rename stalled for serializing inst 2619348SAli.Saidi@ARM.comsystem.cpu.rename.RunCycles 2904 # Number of cycles rename is running 2629348SAli.Saidi@ARM.comsystem.cpu.rename.UnblockCycles 113 # Number of cycles rename is unblocking 2639348SAli.Saidi@ARM.comsystem.cpu.rename.RenamedInsts 11654 # Number of instructions processed by rename 2649348SAli.Saidi@ARM.comsystem.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full 2659348SAli.Saidi@ARM.comsystem.cpu.rename.LSQFullEvents 97 # Number of times rename has blocked due to LSQ full 2669348SAli.Saidi@ARM.comsystem.cpu.rename.RenamedOperands 7041 # Number of destination operands rename has renamed 2679348SAli.Saidi@ARM.comsystem.cpu.rename.RenameLookups 13857 # Number of register rename lookups that rename has made 2689348SAli.Saidi@ARM.comsystem.cpu.rename.int_rename_lookups 13853 # Number of integer rename lookups 2698554SN/Asystem.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups 2709150SAli.Saidi@ARM.comsystem.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed 2719348SAli.Saidi@ARM.comsystem.cpu.rename.UndoneMaps 3643 # Number of HB maps that are undone due to squashing 2729322Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 17 # count of serializing insts renamed 2739322Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed 2749348SAli.Saidi@ARM.comsystem.cpu.rename.skidInsts 265 # count of insts added to the skid buffer 2759348SAli.Saidi@ARM.comsystem.cpu.memDep0.insertedLoads 2476 # Number of loads inserted to the mem dependence unit. 2769348SAli.Saidi@ARM.comsystem.cpu.memDep0.insertedStores 1198 # Number of stores inserted to the mem dependence unit. 2778428SN/Asystem.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 2788428SN/Asystem.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. 2799348SAli.Saidi@ARM.comsystem.cpu.iq.iqInstsAdded 9172 # Number of instructions added to the IQ (excludes non-spec) 2809322Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ 2819348SAli.Saidi@ARM.comsystem.cpu.iq.iqInstsIssued 8209 # Number of instructions issued 2829348SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedInstsIssued 55 # Number of squashed instructions issued 2839348SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedInstsExamined 3542 # Number of squashed instructions iterated over during squash; mainly for profiling 2849348SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedOperandsExamined 2140 # Number of squashed operands that are examined and possibly removed from graph 2859322Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed 2869348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::samples 13947 # Number of insts issued each cycle 2879348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::mean 0.588585 # Number of insts issued each cycle 2889348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::stdev 1.249847 # Number of insts issued each cycle 2898428SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 2909348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::0 10394 74.52% 74.52% # Number of insts issued each cycle 2919348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::1 1403 10.06% 84.58% # Number of insts issued each cycle 2929348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::2 889 6.37% 90.96% # Number of insts issued each cycle 2939348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::3 554 3.97% 94.93% # Number of insts issued each cycle 2949348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::4 357 2.56% 97.49% # Number of insts issued each cycle 2959348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::5 219 1.57% 99.06% # Number of insts issued each cycle 2969348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::6 88 0.63% 99.69% # Number of insts issued each cycle 2979322Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 29 0.21% 99.90% # Number of insts issued each cycle 2989285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle 2998428SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 3008428SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 3018428SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 3029348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::total 13947 # Number of insts issued each cycle 3038428SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 3049348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntAlu 6 3.73% 3.73% # attempts to use FU when none available 3059348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 3.73% # attempts to use FU when none available 3069348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 3.73% # attempts to use FU when none available 3079348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 3.73% # attempts to use FU when none available 3089348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 3.73% # attempts to use FU when none available 3099348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 3.73% # attempts to use FU when none available 3109348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 3.73% # attempts to use FU when none available 3119348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 3.73% # attempts to use FU when none available 3129348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.73% # attempts to use FU when none available 3139348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 3.73% # attempts to use FU when none available 3149348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.73% # attempts to use FU when none available 3159348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 3.73% # attempts to use FU when none available 3169348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 3.73% # attempts to use FU when none available 3179348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 3.73% # attempts to use FU when none available 3189348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 3.73% # attempts to use FU when none available 3199348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 3.73% # attempts to use FU when none available 3209348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.73% # attempts to use FU when none available 3219348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 3.73% # attempts to use FU when none available 3229348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.73% # attempts to use FU when none available 3239348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.73% # attempts to use FU when none available 3249348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.73% # attempts to use FU when none available 3259348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.73% # attempts to use FU when none available 3269348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.73% # attempts to use FU when none available 3279348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.73% # attempts to use FU when none available 3289348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.73% # attempts to use FU when none available 3299348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.73% # attempts to use FU when none available 3309348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.73% # attempts to use FU when none available 3319348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.73% # attempts to use FU when none available 3329348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.73% # attempts to use FU when none available 3339348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::MemRead 100 62.11% 65.84% # attempts to use FU when none available 3349348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::MemWrite 55 34.16% 100.00% # attempts to use FU when none available 3358428SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 3368428SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 3378241SN/Asystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 3389348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntAlu 4835 58.90% 58.90% # Type of FU issued 3399348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntMult 5 0.06% 58.96% # Type of FU issued 3409348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntDiv 2 0.02% 58.98% # Type of FU issued 3419348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.01% # Type of FU issued 3429348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.01% # Type of FU issued 3439348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.01% # Type of FU issued 3449348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.01% # Type of FU issued 3459348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.01% # Type of FU issued 3469348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.01% # Type of FU issued 3479348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.01% # Type of FU issued 3489348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.01% # Type of FU issued 3499348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.01% # Type of FU issued 3509348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.01% # Type of FU issued 3519348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.01% # Type of FU issued 3529348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.01% # Type of FU issued 3539348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.01% # Type of FU issued 3549348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.01% # Type of FU issued 3559348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.01% # Type of FU issued 3569348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.01% # Type of FU issued 3579348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.01% # Type of FU issued 3589348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.01% # Type of FU issued 3599348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.01% # Type of FU issued 3609348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.01% # Type of FU issued 3619348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.01% # Type of FU issued 3629348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.01% # Type of FU issued 3639348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.01% # Type of FU issued 3649348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.01% # Type of FU issued 3659348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.01% # Type of FU issued 3669348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.01% # Type of FU issued 3679348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::MemRead 2260 27.53% 86.54% # Type of FU issued 3689348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::MemWrite 1105 13.46% 100.00% # Type of FU issued 3698241SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 3708241SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 3719348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::total 8209 # Type of FU issued 3729348SAli.Saidi@ARM.comsystem.cpu.iq.rate 0.248261 # Inst issue rate 3739348SAli.Saidi@ARM.comsystem.cpu.iq.fu_busy_cnt 161 # FU busy when requested 3749348SAli.Saidi@ARM.comsystem.cpu.iq.fu_busy_rate 0.019613 # FU busy rate (busy events/executed inst) 3759348SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_reads 30577 # Number of integer instruction queue reads 3769348SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_writes 12735 # Number of integer instruction queue writes 3779348SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 7402 # Number of integer instruction queue wakeup accesses 3788428SN/Asystem.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads 3798428SN/Asystem.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 3808428SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses 3819348SAli.Saidi@ARM.comsystem.cpu.iq.int_alu_accesses 8368 # Number of integer alu accesses 3828428SN/Asystem.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses 3839348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.forwLoads 67 # Number of loads that had data forwarded from stores 3848428SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 3859348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.squashedLoads 1313 # Number of loads squashed 3869322Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed 3879322Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations 3889348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.squashedStores 273 # Number of stores squashed 3898428SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 3908428SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 3918428SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 3929348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.cacheBlocked 32 # Number of times an access to memory failed due to the cache being blocked 3938428SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 3949348SAli.Saidi@ARM.comsystem.cpu.iew.iewSquashCycles 851 # Number of cycles IEW is squashing 3959348SAli.Saidi@ARM.comsystem.cpu.iew.iewBlockCycles 242 # Number of cycles IEW is blocking 3969348SAli.Saidi@ARM.comsystem.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking 3979348SAli.Saidi@ARM.comsystem.cpu.iew.iewDispatchedInsts 10697 # Number of instructions dispatched to IQ 3989348SAli.Saidi@ARM.comsystem.cpu.iew.iewDispSquashedInsts 120 # Number of squashed instructions skipped by dispatch 3999348SAli.Saidi@ARM.comsystem.cpu.iew.iewDispLoadInsts 2476 # Number of dispatched load instructions 4009348SAli.Saidi@ARM.comsystem.cpu.iew.iewDispStoreInsts 1198 # Number of dispatched store instructions 4019322Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions 4029348SAli.Saidi@ARM.comsystem.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall 4039322Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 4049322Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations 4059348SAli.Saidi@ARM.comsystem.cpu.iew.predictedTakenIncorrect 103 # Number of branches that were predicted taken incorrectly 4069348SAli.Saidi@ARM.comsystem.cpu.iew.predictedNotTakenIncorrect 330 # Number of branches that were predicted not taken incorrectly 4079348SAli.Saidi@ARM.comsystem.cpu.iew.branchMispredicts 433 # Number of branch mispredicts detected at execute 4089348SAli.Saidi@ARM.comsystem.cpu.iew.iewExecutedInsts 7849 # Number of executed instructions 4099348SAli.Saidi@ARM.comsystem.cpu.iew.iewExecLoadInsts 2119 # Number of load instructions executed 4109348SAli.Saidi@ARM.comsystem.cpu.iew.iewExecSquashedInsts 360 # Number of squashed instructions skipped in execute 4118428SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 4129348SAli.Saidi@ARM.comsystem.cpu.iew.exec_nop 1512 # number of nop insts executed 4139348SAli.Saidi@ARM.comsystem.cpu.iew.exec_refs 3196 # number of memory reference insts executed 4149348SAli.Saidi@ARM.comsystem.cpu.iew.exec_branches 1341 # Number of branches executed 4159348SAli.Saidi@ARM.comsystem.cpu.iew.exec_stores 1077 # Number of stores executed 4169348SAli.Saidi@ARM.comsystem.cpu.iew.exec_rate 0.237374 # Inst execution rate 4179348SAli.Saidi@ARM.comsystem.cpu.iew.wb_sent 7488 # cumulative count of insts sent to commit 4189348SAli.Saidi@ARM.comsystem.cpu.iew.wb_count 7404 # cumulative count of insts written-back 4199348SAli.Saidi@ARM.comsystem.cpu.iew.wb_producers 2925 # num instructions producing a value 4209348SAli.Saidi@ARM.comsystem.cpu.iew.wb_consumers 4228 # num instructions consuming a value 4218428SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 4229348SAli.Saidi@ARM.comsystem.cpu.iew.wb_rate 0.223916 # insts written-back per cycle 4239348SAli.Saidi@ARM.comsystem.cpu.iew.wb_fanout 0.691816 # average fanout of values written-back 4248428SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 4259348SAli.Saidi@ARM.comsystem.cpu.commit.commitSquashedInsts 4876 # The number of squashed insts skipped by commit 4268428SN/Asystem.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards 4279348SAli.Saidi@ARM.comsystem.cpu.commit.branchMispredicts 377 # The number of times a branch was mispredicted 4289348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::samples 13096 # Number of insts commited each cycle 4299348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::mean 0.443876 # Number of insts commited each cycle 4309348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::stdev 1.229358 # Number of insts commited each cycle 4318428SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 4329348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::0 10722 81.87% 81.87% # Number of insts commited each cycle 4339348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::1 944 7.21% 89.08% # Number of insts commited each cycle 4349348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::2 654 4.99% 94.07% # Number of insts commited each cycle 4359348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::3 320 2.44% 96.52% # Number of insts commited each cycle 4369348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::4 142 1.08% 97.60% # Number of insts commited each cycle 4379348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::5 103 0.79% 98.39% # Number of insts commited each cycle 4389348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::6 65 0.50% 98.89% # Number of insts commited each cycle 4399348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::7 40 0.31% 99.19% # Number of insts commited each cycle 4409348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::8 106 0.81% 100.00% # Number of insts commited each cycle 4418428SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 4428428SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 4438428SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 4449348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::total 13096 # Number of insts commited each cycle 4459150SAli.Saidi@ARM.comsystem.cpu.commit.committedInsts 5813 # Number of instructions committed 4469150SAli.Saidi@ARM.comsystem.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed 4478428SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 4489150SAli.Saidi@ARM.comsystem.cpu.commit.refs 2088 # Number of memory references committed 4499150SAli.Saidi@ARM.comsystem.cpu.commit.loads 1163 # Number of loads committed 4508428SN/Asystem.cpu.commit.membars 0 # Number of memory barriers committed 4519150SAli.Saidi@ARM.comsystem.cpu.commit.branches 915 # Number of branches committed 4528428SN/Asystem.cpu.commit.fp_insts 2 # Number of committed floating point instructions. 4539150SAli.Saidi@ARM.comsystem.cpu.commit.int_insts 5111 # Number of committed integer instructions. 4548428SN/Asystem.cpu.commit.function_calls 87 # Number of function calls committed. 4559348SAli.Saidi@ARM.comsystem.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached 4568428SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 4579348SAli.Saidi@ARM.comsystem.cpu.rob.rob_reads 23666 # The number of ROB reads 4589348SAli.Saidi@ARM.comsystem.cpu.rob.rob_writes 22238 # The number of ROB writes 4599322Sandreas.hansson@arm.comsystem.cpu.timesIdled 285 # Number of times that the entire CPU went into an idle state and unscheduled itself 4609348SAli.Saidi@ARM.comsystem.cpu.idleCycles 19119 # Total number of cycles that the CPU has spent unscheduled due to idling 4619150SAli.Saidi@ARM.comsystem.cpu.committedInsts 5156 # Number of Instructions Simulated 4629150SAli.Saidi@ARM.comsystem.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated 4639150SAli.Saidi@ARM.comsystem.cpu.committedInsts_total 5156 # Number of Instructions Simulated 4649348SAli.Saidi@ARM.comsystem.cpu.cpi 6.413111 # CPI: Cycles Per Instruction 4659348SAli.Saidi@ARM.comsystem.cpu.cpi_total 6.413111 # CPI: Total CPI of All Threads 4669348SAli.Saidi@ARM.comsystem.cpu.ipc 0.155931 # IPC: Instructions Per Cycle 4679348SAli.Saidi@ARM.comsystem.cpu.ipc_total 0.155931 # IPC: Total IPC of All Threads 4689348SAli.Saidi@ARM.comsystem.cpu.int_regfile_reads 10670 # number of integer regfile reads 4699348SAli.Saidi@ARM.comsystem.cpu.int_regfile_writes 5185 # number of integer regfile writes 4708428SN/Asystem.cpu.fp_regfile_reads 3 # number of floating regfile reads 4718428SN/Asystem.cpu.fp_regfile_writes 1 # number of floating regfile writes 4729348SAli.Saidi@ARM.comsystem.cpu.misc_regfile_reads 147 # number of misc regfile reads 4739079SAli.Saidi@ARM.comsystem.cpu.icache.replacements 17 # number of replacements 4749348SAli.Saidi@ARM.comsystem.cpu.icache.tagsinuse 163.149412 # Cycle average of tags in use 4759348SAli.Saidi@ARM.comsystem.cpu.icache.total_refs 1502 # Total number of references to valid blocks. 4769348SAli.Saidi@ARM.comsystem.cpu.icache.sampled_refs 338 # Sample count of references to valid blocks. 4779348SAli.Saidi@ARM.comsystem.cpu.icache.avg_refs 4.443787 # Average number of references to valid blocks. 4788428SN/Asystem.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 4799348SAli.Saidi@ARM.comsystem.cpu.icache.occ_blocks::cpu.inst 163.149412 # Average occupied blocks per requestor 4809348SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::cpu.inst 0.079663 # Average percentage of cache occupancy 4819348SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::total 0.079663 # Average percentage of cache occupancy 4829348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1502 # number of ReadReq hits 4839348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::total 1502 # number of ReadReq hits 4849348SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::cpu.inst 1502 # number of demand (read+write) hits 4859348SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::total 1502 # number of demand (read+write) hits 4869348SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::cpu.inst 1502 # number of overall hits 4879348SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::total 1502 # number of overall hits 4889348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::cpu.inst 446 # number of ReadReq misses 4899348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::total 446 # number of ReadReq misses 4909348SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::cpu.inst 446 # number of demand (read+write) misses 4919348SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::total 446 # number of demand (read+write) misses 4929348SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::cpu.inst 446 # number of overall misses 4939348SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::total 446 # number of overall misses 4949348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 21402000 # number of ReadReq miss cycles 4959348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_latency::total 21402000 # number of ReadReq miss cycles 4969348SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_latency::cpu.inst 21402000 # number of demand (read+write) miss cycles 4979348SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_latency::total 21402000 # number of demand (read+write) miss cycles 4989348SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_latency::cpu.inst 21402000 # number of overall miss cycles 4999348SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_latency::total 21402000 # number of overall miss cycles 5009348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 1948 # number of ReadReq accesses(hits+misses) 5019348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::total 1948 # number of ReadReq accesses(hits+misses) 5029348SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::cpu.inst 1948 # number of demand (read+write) accesses 5039348SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::total 1948 # number of demand (read+write) accesses 5049348SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::cpu.inst 1948 # number of overall (read+write) accesses 5059348SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::total 1948 # number of overall (read+write) accesses 5069348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.228953 # miss rate for ReadReq accesses 5079348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::total 0.228953 # miss rate for ReadReq accesses 5089348SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.228953 # miss rate for demand accesses 5099348SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::total 0.228953 # miss rate for demand accesses 5109348SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.228953 # miss rate for overall accesses 5119348SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::total 0.228953 # miss rate for overall accesses 5129348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47986.547085 # average ReadReq miss latency 5139348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 47986.547085 # average ReadReq miss latency 5149348SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 47986.547085 # average overall miss latency 5159348SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_miss_latency::total 47986.547085 # average overall miss latency 5169348SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 47986.547085 # average overall miss latency 5179348SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_miss_latency::total 47986.547085 # average overall miss latency 5189348SAli.Saidi@ARM.comsystem.cpu.icache.blocked_cycles::no_mshrs 6 # number of cycles access was blocked 5198428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5209322Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked 5218428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 5229348SAli.Saidi@ARM.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 6 # average number of cycles each access was blocked 5238983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5248428SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 5258428SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 5269348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 108 # number of ReadReq MSHR hits 5279348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_hits::total 108 # number of ReadReq MSHR hits 5289348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 108 # number of demand (read+write) MSHR hits 5299348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits 5309348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 108 # number of overall MSHR hits 5319348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_hits::total 108 # number of overall MSHR hits 5329348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses 5339348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses 5349348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses 5359348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses 5369348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses 5379348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses 5389348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16954500 # number of ReadReq MSHR miss cycles 5399348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 16954500 # number of ReadReq MSHR miss cycles 5409348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 16954500 # number of demand (read+write) MSHR miss cycles 5419348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::total 16954500 # number of demand (read+write) MSHR miss cycles 5429348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 16954500 # number of overall MSHR miss cycles 5439348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::total 16954500 # number of overall MSHR miss cycles 5449348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.173511 # mshr miss rate for ReadReq accesses 5459348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.173511 # mshr miss rate for ReadReq accesses 5469348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.173511 # mshr miss rate for demand accesses 5479348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.173511 # mshr miss rate for demand accesses 5489348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.173511 # mshr miss rate for overall accesses 5499348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.173511 # mshr miss rate for overall accesses 5509348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50161.242604 # average ReadReq mshr miss latency 5519348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50161.242604 # average ReadReq mshr miss latency 5529348SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50161.242604 # average overall mshr miss latency 5539348SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 50161.242604 # average overall mshr miss latency 5549348SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50161.242604 # average overall mshr miss latency 5559348SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 50161.242604 # average overall mshr miss latency 5568428SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 5579348SAli.Saidi@ARM.comsystem.cpu.l2cache.replacements 0 # number of replacements 5589348SAli.Saidi@ARM.comsystem.cpu.l2cache.tagsinuse 223.784369 # Cycle average of tags in use 5599348SAli.Saidi@ARM.comsystem.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. 5609348SAli.Saidi@ARM.comsystem.cpu.l2cache.sampled_refs 425 # Sample count of references to valid blocks. 5619348SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_refs 0.007059 # Average number of references to valid blocks. 5629348SAli.Saidi@ARM.comsystem.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 5639348SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_blocks::cpu.inst 165.662974 # Average occupied blocks per requestor 5649348SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_blocks::cpu.data 58.121395 # Average occupied blocks per requestor 5659348SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::cpu.inst 0.005056 # Average percentage of cache occupancy 5669348SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::cpu.data 0.001774 # Average percentage of cache occupancy 5679348SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::total 0.006829 # Average percentage of cache occupancy 5689348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits 5699348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits 5709348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 5719348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 5729348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 5739348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 3 # number of overall hits 5749348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 335 # number of ReadReq misses 5759348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 90 # number of ReadReq misses 5769348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::total 425 # number of ReadReq misses 5779348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses 5789348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses 5799348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.inst 335 # number of demand (read+write) misses 5809348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.data 141 # number of demand (read+write) misses 5819348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::total 476 # number of demand (read+write) misses 5829348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses 5839348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses 5849348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::total 476 # number of overall misses 5859348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16586500 # number of ReadReq miss cycles 5869348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 5449500 # number of ReadReq miss cycles 5879348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::total 22036000 # number of ReadReq miss cycles 5889348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2702000 # number of ReadExReq miss cycles 5899348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 2702000 # number of ReadExReq miss cycles 5909348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 16586500 # number of demand (read+write) miss cycles 5919348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 8151500 # number of demand (read+write) miss cycles 5929348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::total 24738000 # number of demand (read+write) miss cycles 5939348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 16586500 # number of overall miss cycles 5949348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 8151500 # number of overall miss cycles 5959348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::total 24738000 # number of overall miss cycles 5969348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses) 5979348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 90 # number of ReadReq accesses(hits+misses) 5989348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::total 428 # number of ReadReq accesses(hits+misses) 5999348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) 6009348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) 6019348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.inst 338 # number of demand (read+write) accesses 6029348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses 6039348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::total 479 # number of demand (read+write) accesses 6049348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.inst 338 # number of overall (read+write) accesses 6059348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses 6069348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::total 479 # number of overall (read+write) accesses 6079348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991124 # miss rate for ReadReq accesses 6089348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 6099348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.992991 # miss rate for ReadReq accesses 6109348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 6119348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 6129348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.991124 # miss rate for demand accesses 6139348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 6149348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::total 0.993737 # miss rate for demand accesses 6159348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.991124 # miss rate for overall accesses 6169348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 6179348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::total 0.993737 # miss rate for overall accesses 6189348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49511.940299 # average ReadReq miss latency 6199348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 60550 # average ReadReq miss latency 6209348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 51849.411765 # average ReadReq miss latency 6219348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52980.392157 # average ReadExReq miss latency 6229348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 52980.392157 # average ReadExReq miss latency 6239348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49511.940299 # average overall miss latency 6249348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 57812.056738 # average overall miss latency 6259348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::total 51970.588235 # average overall miss latency 6269348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49511.940299 # average overall miss latency 6279348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 57812.056738 # average overall miss latency 6289348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::total 51970.588235 # average overall miss latency 6299348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 6309348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6319348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 6329348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 6339348SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 6349348SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6359348SAli.Saidi@ARM.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 6369348SAli.Saidi@ARM.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 6379348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 335 # number of ReadReq MSHR misses 6389348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses 6399348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses 6409348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses 6419348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses 6429348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 335 # number of demand (read+write) MSHR misses 6439348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 6449348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::total 476 # number of demand (read+write) MSHR misses 6459348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses 6469348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 6479348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::total 476 # number of overall MSHR misses 6489348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12363045 # number of ReadReq MSHR miss cycles 6499348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4340573 # number of ReadReq MSHR miss cycles 6509348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 16703618 # number of ReadReq MSHR miss cycles 6519348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2071054 # number of ReadExReq MSHR miss cycles 6529348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2071054 # number of ReadExReq MSHR miss cycles 6539348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12363045 # number of demand (read+write) MSHR miss cycles 6549348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6411627 # number of demand (read+write) MSHR miss cycles 6559348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 18774672 # number of demand (read+write) MSHR miss cycles 6569348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12363045 # number of overall MSHR miss cycles 6579348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6411627 # number of overall MSHR miss cycles 6589348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 18774672 # number of overall MSHR miss cycles 6599348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for ReadReq accesses 6609348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 6619348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.992991 # mshr miss rate for ReadReq accesses 6629348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 6639348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 6649348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for demand accesses 6659348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 6669348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.993737 # mshr miss rate for demand accesses 6679348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for overall accesses 6689348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 6699348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.993737 # mshr miss rate for overall accesses 6709348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36904.611940 # average ReadReq mshr miss latency 6719348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48228.588889 # average ReadReq mshr miss latency 6729348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39302.630588 # average ReadReq mshr miss latency 6739348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40608.901961 # average ReadExReq mshr miss latency 6749348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40608.901961 # average ReadExReq mshr miss latency 6759348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36904.611940 # average overall mshr miss latency 6769348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 45472.531915 # average overall mshr miss latency 6779348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 39442.588235 # average overall mshr miss latency 6789348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36904.611940 # average overall mshr miss latency 6799348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 45472.531915 # average overall mshr miss latency 6809348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 39442.588235 # average overall mshr miss latency 6819348SAli.Saidi@ARM.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 6828428SN/Asystem.cpu.dcache.replacements 0 # number of replacements 6839348SAli.Saidi@ARM.comsystem.cpu.dcache.tagsinuse 92.011405 # Cycle average of tags in use 6849348SAli.Saidi@ARM.comsystem.cpu.dcache.total_refs 2420 # Total number of references to valid blocks. 6859096Sandreas.hansson@arm.comsystem.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. 6869348SAli.Saidi@ARM.comsystem.cpu.dcache.avg_refs 17.163121 # Average number of references to valid blocks. 6878428SN/Asystem.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 6889348SAli.Saidi@ARM.comsystem.cpu.dcache.occ_blocks::cpu.data 92.011405 # Average occupied blocks per requestor 6899348SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::cpu.data 0.022464 # Average percentage of cache occupancy 6909348SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::total 0.022464 # Average percentage of cache occupancy 6919348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1848 # number of ReadReq hits 6929348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_hits::total 1848 # number of ReadReq hits 6939322Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits 6949322Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 572 # number of WriteReq hits 6959348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_hits::cpu.data 2420 # number of demand (read+write) hits 6969348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_hits::total 2420 # number of demand (read+write) hits 6979348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_hits::cpu.data 2420 # number of overall hits 6989348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_hits::total 2420 # number of overall hits 6999348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::cpu.data 151 # number of ReadReq misses 7009348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::total 151 # number of ReadReq misses 7019322Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 353 # number of WriteReq misses 7029322Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 353 # number of WriteReq misses 7039348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::cpu.data 504 # number of demand (read+write) misses 7049348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::total 504 # number of demand (read+write) misses 7059348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::cpu.data 504 # number of overall misses 7069348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::total 504 # number of overall misses 7079348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 8901000 # number of ReadReq miss cycles 7089348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_latency::total 8901000 # number of ReadReq miss cycles 7099348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 15603499 # number of WriteReq miss cycles 7109348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_latency::total 15603499 # number of WriteReq miss cycles 7119348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_latency::cpu.data 24504499 # number of demand (read+write) miss cycles 7129348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_latency::total 24504499 # number of demand (read+write) miss cycles 7139348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_latency::cpu.data 24504499 # number of overall miss cycles 7149348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_latency::total 24504499 # number of overall miss cycles 7159348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1999 # number of ReadReq accesses(hits+misses) 7169348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_accesses::total 1999 # number of ReadReq accesses(hits+misses) 7178835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 7188835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 7199348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_accesses::cpu.data 2924 # number of demand (read+write) accesses 7209348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_accesses::total 2924 # number of demand (read+write) accesses 7219348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_accesses::cpu.data 2924 # number of overall (read+write) accesses 7229348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_accesses::total 2924 # number of overall (read+write) accesses 7239348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075538 # miss rate for ReadReq accesses 7249348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.075538 # miss rate for ReadReq accesses 7259322Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381622 # miss rate for WriteReq accesses 7269322Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.381622 # miss rate for WriteReq accesses 7279348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.172367 # miss rate for demand accesses 7289348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::total 0.172367 # miss rate for demand accesses 7299348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.172367 # miss rate for overall accesses 7309348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_rate::total 0.172367 # miss rate for overall accesses 7319348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58947.019868 # average ReadReq miss latency 7329348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 58947.019868 # average ReadReq miss latency 7339348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44202.546742 # average WriteReq miss latency 7349348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 44202.546742 # average WriteReq miss latency 7359348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 48620.037698 # average overall miss latency 7369348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_miss_latency::total 48620.037698 # average overall miss latency 7379348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 48620.037698 # average overall miss latency 7389348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_miss_latency::total 48620.037698 # average overall miss latency 7399348SAli.Saidi@ARM.comsystem.cpu.dcache.blocked_cycles::no_mshrs 502 # number of cycles access was blocked 7408428SN/Asystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 7419322Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked 7428428SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 7439348SAli.Saidi@ARM.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 45.636364 # average number of cycles each access was blocked 7448983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 7458428SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 7468428SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 7479348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits 7489348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits 7499322Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 302 # number of WriteReq MSHR hits 7509322Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 302 # number of WriteReq MSHR hits 7519348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 363 # number of demand (read+write) MSHR hits 7529348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_hits::total 363 # number of demand (read+write) MSHR hits 7539348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 363 # number of overall MSHR hits 7549348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_hits::total 363 # number of overall MSHR hits 7559096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses 7569096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses 7578835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses 7588835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses 7599096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 7609096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses 7619096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 7629096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses 7639348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5543000 # number of ReadReq MSHR miss cycles 7649348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 5543000 # number of ReadReq MSHR miss cycles 7659348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2753999 # number of WriteReq MSHR miss cycles 7669348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 2753999 # number of WriteReq MSHR miss cycles 7679348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 8296999 # number of demand (read+write) MSHR miss cycles 7689348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_latency::total 8296999 # number of demand (read+write) MSHR miss cycles 7699348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 8296999 # number of overall MSHR miss cycles 7709348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_latency::total 8296999 # number of overall MSHR miss cycles 7719348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045023 # mshr miss rate for ReadReq accesses 7729348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045023 # mshr miss rate for ReadReq accesses 7738835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses 7749055Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses 7759348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048222 # mshr miss rate for demand accesses 7769348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.048222 # mshr miss rate for demand accesses 7779348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048222 # mshr miss rate for overall accesses 7789348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.048222 # mshr miss rate for overall accesses 7799348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61588.888889 # average ReadReq mshr miss latency 7809348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61588.888889 # average ReadReq mshr miss latency 7819348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53999.980392 # average WriteReq mshr miss latency 7829348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53999.980392 # average WriteReq mshr miss latency 7839348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58843.964539 # average overall mshr miss latency 7849348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 58843.964539 # average overall mshr miss latency 7859348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58843.964539 # average overall mshr miss latency 7869348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 58843.964539 # average overall mshr miss latency 7878428SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 7886039SN/A 7896039SN/A---------- End Simulation Statistics ---------- 790