stats.txt revision 9322
16039SN/A 26039SN/A---------- Begin Simulation Statistics ---------- 39322Sandreas.hansson@arm.comsim_seconds 0.000016 # Number of seconds simulated 49322Sandreas.hansson@arm.comsim_ticks 16437500 # Number of ticks simulated 59322Sandreas.hansson@arm.comfinal_tick 16437500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79322Sandreas.hansson@arm.comhost_inst_rate 79981 # Simulator instruction rate (inst/s) 89322Sandreas.hansson@arm.comhost_op_rate 79951 # Simulator op (including micro ops) rate (op/s) 99322Sandreas.hansson@arm.comhost_tick_rate 254800448 # Simulator tick rate (ticks/s) 109322Sandreas.hansson@arm.comhost_mem_usage 217976 # Number of bytes of host memory used 119322Sandreas.hansson@arm.comhost_seconds 0.06 # Real time elapsed on the host 129150SAli.Saidi@ARM.comsim_insts 5156 # Number of instructions simulated 139150SAli.Saidi@ARM.comsim_ops 5156 # Number of ops (including micro ops) simulated 149150SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.inst 21696 # Number of bytes read from this memory 159096Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory 169150SAli.Saidi@ARM.comsystem.physmem.bytes_read::total 30720 # Number of bytes read from this memory 179150SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::cpu.inst 21696 # Number of instructions bytes read from this memory 189150SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::total 21696 # Number of instructions bytes read from this memory 199150SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.inst 339 # Number of read requests responded to by this memory 209096Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory 219150SAli.Saidi@ARM.comsystem.physmem.num_reads::total 480 # Number of read requests responded to by this memory 229322Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 1319908745 # Total read bandwidth from this memory (bytes/s) 239322Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 548988593 # Total read bandwidth from this memory (bytes/s) 249322Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1868897338 # Total read bandwidth from this memory (bytes/s) 259322Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 1319908745 # Instruction read bandwidth from this memory (bytes/s) 269322Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 1319908745 # Instruction read bandwidth from this memory (bytes/s) 279322Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 1319908745 # Total bandwidth to/from this memory (bytes/s) 289322Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 548988593 # Total bandwidth to/from this memory (bytes/s) 299322Sandreas.hansson@arm.comsystem.physmem.bw_total::total 1868897338 # Total bandwidth to/from this memory (bytes/s) 309312Sandreas.hansson@arm.comsystem.physmem.readReqs 480 # Total number of read requests seen 319312Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Total number of write requests seen 329312Sandreas.hansson@arm.comsystem.physmem.cpureqs 480 # Reqs generatd by CPU via cache - shady 339312Sandreas.hansson@arm.comsystem.physmem.bytesRead 30720 # Total number of bytes read from memory 349312Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to memory 359312Sandreas.hansson@arm.comsystem.physmem.bytesConsumedRd 30720 # bytesRead derated as per pkt->getSize() 369312Sandreas.hansson@arm.comsystem.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 379312Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 389312Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 399312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::0 64 # Track reads on a per bank basis 409312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::1 30 # Track reads on a per bank basis 419312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::2 23 # Track reads on a per bank basis 429312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::3 54 # Track reads on a per bank basis 439312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::4 6 # Track reads on a per bank basis 449312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::5 39 # Track reads on a per bank basis 459312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis 469312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::7 20 # Track reads on a per bank basis 479312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::8 40 # Track reads on a per bank basis 489312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::9 18 # Track reads on a per bank basis 499312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::10 15 # Track reads on a per bank basis 509312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::11 17 # Track reads on a per bank basis 519312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::12 40 # Track reads on a per bank basis 529312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::13 52 # Track reads on a per bank basis 539312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::14 32 # Track reads on a per bank basis 549312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::15 30 # Track reads on a per bank basis 559312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 569312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 579312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 589312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 599312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 609312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 619312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 629312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 639312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 649312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 659312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 669312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 679312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 689312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 699312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 709312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 719312Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 729312Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 739322Sandreas.hansson@arm.comsystem.physmem.totGap 16357500 # Total gap between requests 749312Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Categorize read packet sizes 759312Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Categorize read packet sizes 769312Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Categorize read packet sizes 779312Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Categorize read packet sizes 789312Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Categorize read packet sizes 799312Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Categorize read packet sizes 809312Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 480 # Categorize read packet sizes 819312Sandreas.hansson@arm.comsystem.physmem.readPktSize::7 0 # Categorize read packet sizes 829312Sandreas.hansson@arm.comsystem.physmem.readPktSize::8 0 # Categorize read packet sizes 839312Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # categorize write packet sizes 849312Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # categorize write packet sizes 859312Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # categorize write packet sizes 869312Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # categorize write packet sizes 879312Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # categorize write packet sizes 889312Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # categorize write packet sizes 899312Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # categorize write packet sizes 909312Sandreas.hansson@arm.comsystem.physmem.writePktSize::7 0 # categorize write packet sizes 919312Sandreas.hansson@arm.comsystem.physmem.writePktSize::8 0 # categorize write packet sizes 929312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::0 0 # categorize neither packet sizes 939312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::1 0 # categorize neither packet sizes 949312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::2 0 # categorize neither packet sizes 959312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::3 0 # categorize neither packet sizes 969312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::4 0 # categorize neither packet sizes 979312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::5 0 # categorize neither packet sizes 989312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::6 0 # categorize neither packet sizes 999312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::7 0 # categorize neither packet sizes 1009312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::8 0 # categorize neither packet sizes 1019322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 255 # What read queue length does an incoming req see 1029312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 148 # What read queue length does an incoming req see 1039322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see 1049322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see 1059322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 1069322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1579312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1589312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1599312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1609312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1619312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1629312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1639312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1649312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1659312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 1669312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 1679322Sandreas.hansson@arm.comsystem.physmem.totQLat 2266480 # Total cycles spent in queuing delays 1689322Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 12950480 # Sum of mem lat for all requests 1699312Sandreas.hansson@arm.comsystem.physmem.totBusLat 1920000 # Total cycles spent in databus access 1709322Sandreas.hansson@arm.comsystem.physmem.totBankLat 8764000 # Total cycles spent in bank access 1719322Sandreas.hansson@arm.comsystem.physmem.avgQLat 4721.83 # Average queueing delay per request 1729322Sandreas.hansson@arm.comsystem.physmem.avgBankLat 18258.33 # Average bank access latency per request 1739312Sandreas.hansson@arm.comsystem.physmem.avgBusLat 4000.00 # Average bus latency per request 1749322Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 26980.17 # Average memory access latency 1759322Sandreas.hansson@arm.comsystem.physmem.avgRdBW 1868.90 # Average achieved read bandwidth in MB/s 1769312Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 1779322Sandreas.hansson@arm.comsystem.physmem.avgConsumedRdBW 1868.90 # Average consumed read bandwidth in MB/s 1789312Sandreas.hansson@arm.comsystem.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 1799312Sandreas.hansson@arm.comsystem.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 1809322Sandreas.hansson@arm.comsystem.physmem.busUtil 11.68 # Data bus utilization in percentage 1819322Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 0.79 # Average read queue length over time 1829312Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length over time 1839322Sandreas.hansson@arm.comsystem.physmem.readRowHits 378 # Number of row buffer hits during reads 1849312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 1859322Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 78.75 # Row buffer hit rate for reads 1869312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 1879322Sandreas.hansson@arm.comsystem.physmem.avgGap 34078.12 # Average gap between requests 1888428SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 1898428SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 1908428SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 1918428SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 1928428SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 1938428SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 1946039SN/Asystem.cpu.dtb.hits 0 # DTB hits 1956039SN/Asystem.cpu.dtb.misses 0 # DTB misses 1968428SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 1978428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 1988428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 1998428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 2008428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 2018428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 2028428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 2038428SN/Asystem.cpu.itb.hits 0 # DTB hits 2048428SN/Asystem.cpu.itb.misses 0 # DTB misses 2058428SN/Asystem.cpu.itb.accesses 0 # DTB accesses 2068428SN/Asystem.cpu.workload.num_syscalls 8 # Number of system calls 2079322Sandreas.hansson@arm.comsystem.cpu.numCycles 32876 # number of cpu cycles simulated 2088428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2098428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 2109322Sandreas.hansson@arm.comsystem.cpu.BPredUnit.lookups 2145 # Number of BP lookups 2119322Sandreas.hansson@arm.comsystem.cpu.BPredUnit.condPredicted 1420 # Number of conditional branches predicted 2129322Sandreas.hansson@arm.comsystem.cpu.BPredUnit.condIncorrect 444 # Number of conditional branches incorrect 2139322Sandreas.hansson@arm.comsystem.cpu.BPredUnit.BTBLookups 1692 # Number of BTB lookups 2149322Sandreas.hansson@arm.comsystem.cpu.BPredUnit.BTBHits 498 # Number of BTB hits 2158428SN/Asystem.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 2169322Sandreas.hansson@arm.comsystem.cpu.BPredUnit.usedRAS 270 # Number of times the RAS was used to get a target. 2179322Sandreas.hansson@arm.comsystem.cpu.BPredUnit.RASInCorrect 68 # Number of incorrect RAS predictions. 2189322Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 8858 # Number of cycles fetch is stalled on an Icache miss 2199322Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 13016 # Number of instructions fetch has processed 2209322Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 2145 # Number of branches that fetch encountered 2219322Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 768 # Number of branches that fetch has predicted taken 2229322Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 3241 # Number of cycles fetch has run and was not squashing or blocked 2239322Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 1374 # Number of cycles fetch has spent squashing 2249322Sandreas.hansson@arm.comsystem.cpu.fetch.BlockedCycles 897 # Number of cycles fetch has spent blocked 2258464SN/Asystem.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 2269322Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps 2279322Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 2015 # Number of cache lines fetched 2289322Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 287 # Number of outstanding Icache misses that were squashed 2299322Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 14043 # Number of instructions fetched each cycle (Total) 2309322Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 0.926867 # Number of instructions fetched each cycle (Total) 2319322Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 2.227706 # Number of instructions fetched each cycle (Total) 2326291SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 2339322Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 10802 76.92% 76.92% # Number of instructions fetched each cycle (Total) 2349322Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 1358 9.67% 86.59% # Number of instructions fetched each cycle (Total) 2359322Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 113 0.80% 87.40% # Number of instructions fetched each cycle (Total) 2369322Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 147 1.05% 88.44% # Number of instructions fetched each cycle (Total) 2379322Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 305 2.17% 90.61% # Number of instructions fetched each cycle (Total) 2389322Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 111 0.79% 91.40% # Number of instructions fetched each cycle (Total) 2399322Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 157 1.12% 92.52% # Number of instructions fetched each cycle (Total) 2409322Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 126 0.90% 93.42% # Number of instructions fetched each cycle (Total) 2419322Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 924 6.58% 100.00% # Number of instructions fetched each cycle (Total) 2426291SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 2436291SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 2446291SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 2459322Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 14043 # Number of instructions fetched each cycle (Total) 2469322Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.065245 # Number of branch fetches per cycle 2479322Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.395912 # Number of inst fetches per cycle 2489322Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 8962 # Number of cycles decode is idle 2499322Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 1117 # Number of cycles decode is blocked 2509322Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 3062 # Number of cycles decode is running 2519322Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 44 # Number of cycles decode is unblocking 2529322Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 858 # Number of cycles decode is squashing 2539322Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 165 # Number of times decode resolved a branch 2549322Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 46 # Number of times decode detected a branch misprediction 2559322Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 12081 # Number of instructions handled by decode 2569150SAli.Saidi@ARM.comsystem.cpu.decode.SquashedInsts 178 # Number of squashed instructions handled by decode 2579322Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 858 # Number of cycles rename is squashing 2589322Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 9149 # Number of cycles rename is idle 2599322Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 246 # Number of cycles rename is blocking 2609322Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 762 # count of cycles rename stalled for serializing inst 2619322Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 2921 # Number of cycles rename is running 2629322Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 107 # Number of cycles rename is unblocking 2639322Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 11564 # Number of instructions processed by rename 2649322Sandreas.hansson@arm.comsystem.cpu.rename.LSQFullEvents 95 # Number of times rename has blocked due to LSQ full 2659322Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 7026 # Number of destination operands rename has renamed 2669322Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 13727 # Number of register rename lookups that rename has made 2679322Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 13723 # Number of integer rename lookups 2688554SN/Asystem.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups 2699150SAli.Saidi@ARM.comsystem.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed 2709322Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 3628 # Number of HB maps that are undone due to squashing 2719322Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 17 # count of serializing insts renamed 2729322Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed 2739322Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 273 # count of insts added to the skid buffer 2749322Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 2438 # Number of loads inserted to the mem dependence unit. 2759322Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 1184 # Number of stores inserted to the mem dependence unit. 2768428SN/Asystem.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 2778428SN/Asystem.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. 2789322Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 9022 # Number of instructions added to the IQ (excludes non-spec) 2799322Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ 2809322Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 8202 # Number of instructions issued 2819322Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 45 # Number of squashed instructions issued 2829322Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 3390 # Number of squashed instructions iterated over during squash; mainly for profiling 2839322Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 1898 # Number of squashed operands that are examined and possibly removed from graph 2849322Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed 2859322Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 14043 # Number of insts issued each cycle 2869322Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.584063 # Number of insts issued each cycle 2879322Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.245002 # Number of insts issued each cycle 2888428SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 2899322Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 10483 74.65% 74.65% # Number of insts issued each cycle 2909322Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 1421 10.12% 84.77% # Number of insts issued each cycle 2919322Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 877 6.25% 91.01% # Number of insts issued each cycle 2929322Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 557 3.97% 94.98% # Number of insts issued each cycle 2939322Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 353 2.51% 97.49% # Number of insts issued each cycle 2949322Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 225 1.60% 99.10% # Number of insts issued each cycle 2959322Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 84 0.60% 99.69% # Number of insts issued each cycle 2969322Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 29 0.21% 99.90% # Number of insts issued each cycle 2979285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle 2988428SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 2998428SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 3008428SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 3019322Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 14043 # Number of insts issued each cycle 3028428SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 3039322Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 3 1.96% 1.96% # attempts to use FU when none available 3049322Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 1.96% # attempts to use FU when none available 3059322Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 1.96% # attempts to use FU when none available 3069322Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 1.96% # attempts to use FU when none available 3079322Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 1.96% # attempts to use FU when none available 3089322Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 1.96% # attempts to use FU when none available 3099322Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 1.96% # attempts to use FU when none available 3109322Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 1.96% # attempts to use FU when none available 3119322Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.96% # attempts to use FU when none available 3129322Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 1.96% # attempts to use FU when none available 3139322Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.96% # attempts to use FU when none available 3149322Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 1.96% # attempts to use FU when none available 3159322Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 1.96% # attempts to use FU when none available 3169322Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 1.96% # attempts to use FU when none available 3179322Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 1.96% # attempts to use FU when none available 3189322Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 1.96% # attempts to use FU when none available 3199322Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.96% # attempts to use FU when none available 3209322Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 1.96% # attempts to use FU when none available 3219322Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.96% # attempts to use FU when none available 3229322Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.96% # attempts to use FU when none available 3239322Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.96% # attempts to use FU when none available 3249322Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.96% # attempts to use FU when none available 3259322Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.96% # attempts to use FU when none available 3269322Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.96% # attempts to use FU when none available 3279322Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.96% # attempts to use FU when none available 3289322Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.96% # attempts to use FU when none available 3299322Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.96% # attempts to use FU when none available 3309322Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.96% # attempts to use FU when none available 3319322Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.96% # attempts to use FU when none available 3329322Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 97 63.40% 65.36% # attempts to use FU when none available 3339322Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 53 34.64% 100.00% # attempts to use FU when none available 3348428SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 3358428SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 3368241SN/Asystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 3379322Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 4842 59.03% 59.03% # Type of FU issued 3389322Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 5 0.06% 59.10% # Type of FU issued 3399322Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.12% # Type of FU issued 3409322Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.14% # Type of FU issued 3419322Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.14% # Type of FU issued 3429322Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.14% # Type of FU issued 3439322Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.14% # Type of FU issued 3449322Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.14% # Type of FU issued 3459322Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.14% # Type of FU issued 3469322Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.14% # Type of FU issued 3479322Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.14% # Type of FU issued 3489322Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.14% # Type of FU issued 3499322Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.14% # Type of FU issued 3509322Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.14% # Type of FU issued 3519322Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.14% # Type of FU issued 3529322Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.14% # Type of FU issued 3539322Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.14% # Type of FU issued 3549322Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.14% # Type of FU issued 3559322Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.14% # Type of FU issued 3569322Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.14% # Type of FU issued 3579322Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.14% # Type of FU issued 3589322Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.14% # Type of FU issued 3599322Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.14% # Type of FU issued 3609322Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.14% # Type of FU issued 3619322Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.14% # Type of FU issued 3629322Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.14% # Type of FU issued 3639322Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.14% # Type of FU issued 3649322Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.14% # Type of FU issued 3659322Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.14% # Type of FU issued 3669322Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 2249 27.42% 86.56% # Type of FU issued 3679322Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 1102 13.44% 100.00% # Type of FU issued 3688241SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 3698241SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 3709322Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 8202 # Type of FU issued 3719322Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.249483 # Inst issue rate 3729322Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 153 # FU busy when requested 3739322Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.018654 # FU busy rate (busy events/executed inst) 3749322Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 30641 # Number of integer instruction queue reads 3759322Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 12433 # Number of integer instruction queue writes 3769322Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 7364 # Number of integer instruction queue wakeup accesses 3778428SN/Asystem.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads 3788428SN/Asystem.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 3798428SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses 3809322Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 8353 # Number of integer alu accesses 3818428SN/Asystem.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses 3829312Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores 3838428SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 3849322Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1275 # Number of loads squashed 3859322Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed 3869322Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations 3879322Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 259 # Number of stores squashed 3888428SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 3898428SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 3908428SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 3919322Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 38 # Number of times an access to memory failed due to the cache being blocked 3928428SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 3939322Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 858 # Number of cycles IEW is squashing 3949322Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 190 # Number of cycles IEW is blocking 3959285Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking 3969322Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 10500 # Number of instructions dispatched to IQ 3979312Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 111 # Number of squashed instructions skipped by dispatch 3989322Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 2438 # Number of dispatched load instructions 3999322Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 1184 # Number of dispatched store instructions 4009322Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions 4018844SAli.Saidi@ARM.comsystem.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall 4029322Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 4039322Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations 4049322Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly 4059322Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 363 # Number of branches that were predicted not taken incorrectly 4069322Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 471 # Number of branch mispredicts detected at execute 4079322Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 7830 # Number of executed instructions 4089322Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 2115 # Number of load instructions executed 4099322Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 372 # Number of squashed instructions skipped in execute 4108428SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 4119322Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 1465 # number of nop insts executed 4129322Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 3191 # number of memory reference insts executed 4139322Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 1342 # Number of branches executed 4149322Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 1076 # Number of stores executed 4159322Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.238168 # Inst execution rate 4169322Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 7455 # cumulative count of insts sent to commit 4179322Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 7366 # cumulative count of insts written-back 4189322Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 2870 # num instructions producing a value 4199322Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 4099 # num instructions consuming a value 4208428SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 4219322Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.224054 # insts written-back per cycle 4229322Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.700171 # average fanout of values written-back 4238428SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 4249322Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 4679 # The number of squashed insts skipped by commit 4258428SN/Asystem.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards 4269322Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 399 # The number of times a branch was mispredicted 4279322Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 13185 # Number of insts commited each cycle 4289322Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.440880 # Number of insts commited each cycle 4299322Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.228954 # Number of insts commited each cycle 4308428SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 4319322Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 10802 81.93% 81.93% # Number of insts commited each cycle 4329322Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 977 7.41% 89.34% # Number of insts commited each cycle 4339322Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 629 4.77% 94.11% # Number of insts commited each cycle 4349322Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 318 2.41% 96.52% # Number of insts commited each cycle 4359322Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 150 1.14% 97.66% # Number of insts commited each cycle 4369322Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 86 0.65% 98.31% # Number of insts commited each cycle 4379322Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 74 0.56% 98.87% # Number of insts commited each cycle 4389322Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 42 0.32% 99.19% # Number of insts commited each cycle 4399322Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 107 0.81% 100.00% # Number of insts commited each cycle 4408428SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 4418428SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 4428428SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 4439322Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 13185 # Number of insts commited each cycle 4449150SAli.Saidi@ARM.comsystem.cpu.commit.committedInsts 5813 # Number of instructions committed 4459150SAli.Saidi@ARM.comsystem.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed 4468428SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 4479150SAli.Saidi@ARM.comsystem.cpu.commit.refs 2088 # Number of memory references committed 4489150SAli.Saidi@ARM.comsystem.cpu.commit.loads 1163 # Number of loads committed 4498428SN/Asystem.cpu.commit.membars 0 # Number of memory barriers committed 4509150SAli.Saidi@ARM.comsystem.cpu.commit.branches 915 # Number of branches committed 4518428SN/Asystem.cpu.commit.fp_insts 2 # Number of committed floating point instructions. 4529150SAli.Saidi@ARM.comsystem.cpu.commit.int_insts 5111 # Number of committed integer instructions. 4538428SN/Asystem.cpu.commit.function_calls 87 # Number of function calls committed. 4549322Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 107 # number cycles where commit BW limit reached 4558428SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 4569322Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 23557 # The number of ROB reads 4579322Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 21850 # The number of ROB writes 4589322Sandreas.hansson@arm.comsystem.cpu.timesIdled 285 # Number of times that the entire CPU went into an idle state and unscheduled itself 4599322Sandreas.hansson@arm.comsystem.cpu.idleCycles 18833 # Total number of cycles that the CPU has spent unscheduled due to idling 4609150SAli.Saidi@ARM.comsystem.cpu.committedInsts 5156 # Number of Instructions Simulated 4619150SAli.Saidi@ARM.comsystem.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated 4629150SAli.Saidi@ARM.comsystem.cpu.committedInsts_total 5156 # Number of Instructions Simulated 4639322Sandreas.hansson@arm.comsystem.cpu.cpi 6.376261 # CPI: Cycles Per Instruction 4649322Sandreas.hansson@arm.comsystem.cpu.cpi_total 6.376261 # CPI: Total CPI of All Threads 4659322Sandreas.hansson@arm.comsystem.cpu.ipc 0.156832 # IPC: Instructions Per Cycle 4669322Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.156832 # IPC: Total IPC of All Threads 4679322Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 10643 # number of integer regfile reads 4689322Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 5150 # number of integer regfile writes 4698428SN/Asystem.cpu.fp_regfile_reads 3 # number of floating regfile reads 4708428SN/Asystem.cpu.fp_regfile_writes 1 # number of floating regfile writes 4719322Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 154 # number of misc regfile reads 4729079SAli.Saidi@ARM.comsystem.cpu.icache.replacements 17 # number of replacements 4739322Sandreas.hansson@arm.comsystem.cpu.icache.tagsinuse 164.359097 # Cycle average of tags in use 4749322Sandreas.hansson@arm.comsystem.cpu.icache.total_refs 1560 # Total number of references to valid blocks. 4759150SAli.Saidi@ARM.comsystem.cpu.icache.sampled_refs 342 # Sample count of references to valid blocks. 4769322Sandreas.hansson@arm.comsystem.cpu.icache.avg_refs 4.561404 # Average number of references to valid blocks. 4778428SN/Asystem.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 4789322Sandreas.hansson@arm.comsystem.cpu.icache.occ_blocks::cpu.inst 164.359097 # Average occupied blocks per requestor 4799322Sandreas.hansson@arm.comsystem.cpu.icache.occ_percent::cpu.inst 0.080253 # Average percentage of cache occupancy 4809322Sandreas.hansson@arm.comsystem.cpu.icache.occ_percent::total 0.080253 # Average percentage of cache occupancy 4819322Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1560 # number of ReadReq hits 4829322Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 1560 # number of ReadReq hits 4839322Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 1560 # number of demand (read+write) hits 4849322Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 1560 # number of demand (read+write) hits 4859322Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 1560 # number of overall hits 4869322Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 1560 # number of overall hits 4879322Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 455 # number of ReadReq misses 4889322Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 455 # number of ReadReq misses 4899322Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 455 # number of demand (read+write) misses 4909322Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 455 # number of demand (read+write) misses 4919322Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 455 # number of overall misses 4929322Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 455 # number of overall misses 4939322Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 21541500 # number of ReadReq miss cycles 4949322Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 21541500 # number of ReadReq miss cycles 4959322Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 21541500 # number of demand (read+write) miss cycles 4969322Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 21541500 # number of demand (read+write) miss cycles 4979322Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 21541500 # number of overall miss cycles 4989322Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 21541500 # number of overall miss cycles 4999322Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 2015 # number of ReadReq accesses(hits+misses) 5009322Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 2015 # number of ReadReq accesses(hits+misses) 5019322Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 2015 # number of demand (read+write) accesses 5029322Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 2015 # number of demand (read+write) accesses 5039322Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 2015 # number of overall (read+write) accesses 5049322Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 2015 # number of overall (read+write) accesses 5059322Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.225806 # miss rate for ReadReq accesses 5069322Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.225806 # miss rate for ReadReq accesses 5079322Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.225806 # miss rate for demand accesses 5089322Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.225806 # miss rate for demand accesses 5099322Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.225806 # miss rate for overall accesses 5109322Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.225806 # miss rate for overall accesses 5119322Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47343.956044 # average ReadReq miss latency 5129322Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 47343.956044 # average ReadReq miss latency 5139322Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 47343.956044 # average overall miss latency 5149322Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 47343.956044 # average overall miss latency 5159322Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 47343.956044 # average overall miss latency 5169322Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 47343.956044 # average overall miss latency 5179322Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 5 # number of cycles access was blocked 5188428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5199322Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked 5208428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 5219322Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked 5228983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5238428SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 5248428SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 5259322Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 113 # number of ReadReq MSHR hits 5269322Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 113 # number of ReadReq MSHR hits 5279322Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 113 # number of demand (read+write) MSHR hits 5289322Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits 5299322Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 113 # number of overall MSHR hits 5309322Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 113 # number of overall MSHR hits 5319150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 342 # number of ReadReq MSHR misses 5329150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::total 342 # number of ReadReq MSHR misses 5339150SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 342 # number of demand (read+write) MSHR misses 5349150SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::total 342 # number of demand (read+write) MSHR misses 5359150SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 342 # number of overall MSHR misses 5369150SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::total 342 # number of overall MSHR misses 5379322Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17063000 # number of ReadReq MSHR miss cycles 5389322Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 17063000 # number of ReadReq MSHR miss cycles 5399322Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 17063000 # number of demand (read+write) MSHR miss cycles 5409322Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 17063000 # number of demand (read+write) MSHR miss cycles 5419322Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 17063000 # number of overall MSHR miss cycles 5429322Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 17063000 # number of overall MSHR miss cycles 5439322Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.169727 # mshr miss rate for ReadReq accesses 5449322Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.169727 # mshr miss rate for ReadReq accesses 5459322Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.169727 # mshr miss rate for demand accesses 5469322Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.169727 # mshr miss rate for demand accesses 5479322Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.169727 # mshr miss rate for overall accesses 5489322Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.169727 # mshr miss rate for overall accesses 5499322Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49891.812865 # average ReadReq mshr miss latency 5509322Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49891.812865 # average ReadReq mshr miss latency 5519322Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49891.812865 # average overall mshr miss latency 5529322Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 49891.812865 # average overall mshr miss latency 5539322Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49891.812865 # average overall mshr miss latency 5549322Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 49891.812865 # average overall mshr miss latency 5558428SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 5568428SN/Asystem.cpu.dcache.replacements 0 # number of replacements 5579322Sandreas.hansson@arm.comsystem.cpu.dcache.tagsinuse 91.458224 # Cycle average of tags in use 5589322Sandreas.hansson@arm.comsystem.cpu.dcache.total_refs 2418 # Total number of references to valid blocks. 5599096Sandreas.hansson@arm.comsystem.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. 5609322Sandreas.hansson@arm.comsystem.cpu.dcache.avg_refs 17.148936 # Average number of references to valid blocks. 5618428SN/Asystem.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 5629322Sandreas.hansson@arm.comsystem.cpu.dcache.occ_blocks::cpu.data 91.458224 # Average occupied blocks per requestor 5639322Sandreas.hansson@arm.comsystem.cpu.dcache.occ_percent::cpu.data 0.022329 # Average percentage of cache occupancy 5649322Sandreas.hansson@arm.comsystem.cpu.dcache.occ_percent::total 0.022329 # Average percentage of cache occupancy 5659322Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1846 # number of ReadReq hits 5669322Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 1846 # number of ReadReq hits 5679322Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits 5689322Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 572 # number of WriteReq hits 5699322Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 2418 # number of demand (read+write) hits 5709322Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 2418 # number of demand (read+write) hits 5719322Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 2418 # number of overall hits 5729322Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 2418 # number of overall hits 5739285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 149 # number of ReadReq misses 5749285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 149 # number of ReadReq misses 5759322Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 353 # number of WriteReq misses 5769322Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 353 # number of WriteReq misses 5779322Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses 5789322Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses 5799322Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses 5809322Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 502 # number of overall misses 5819322Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 8305500 # number of ReadReq miss cycles 5829322Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 8305500 # number of ReadReq miss cycles 5839322Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 15423499 # number of WriteReq miss cycles 5849322Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 15423499 # number of WriteReq miss cycles 5859322Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 23728999 # number of demand (read+write) miss cycles 5869322Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 23728999 # number of demand (read+write) miss cycles 5879322Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 23728999 # number of overall miss cycles 5889322Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 23728999 # number of overall miss cycles 5899322Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1995 # number of ReadReq accesses(hits+misses) 5909322Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 1995 # number of ReadReq accesses(hits+misses) 5918835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 5928835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 5939322Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 2920 # number of demand (read+write) accesses 5949322Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 2920 # number of demand (read+write) accesses 5959322Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 2920 # number of overall (read+write) accesses 5969322Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 2920 # number of overall (read+write) accesses 5979322Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074687 # miss rate for ReadReq accesses 5989322Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.074687 # miss rate for ReadReq accesses 5999322Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381622 # miss rate for WriteReq accesses 6009322Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.381622 # miss rate for WriteReq accesses 6019322Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.171918 # miss rate for demand accesses 6029322Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.171918 # miss rate for demand accesses 6039322Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.171918 # miss rate for overall accesses 6049322Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.171918 # miss rate for overall accesses 6059322Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55741.610738 # average ReadReq miss latency 6069322Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 55741.610738 # average ReadReq miss latency 6079322Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43692.631728 # average WriteReq miss latency 6089322Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 43692.631728 # average WriteReq miss latency 6099322Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 47268.922311 # average overall miss latency 6109322Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 47268.922311 # average overall miss latency 6119322Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 47268.922311 # average overall miss latency 6129322Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 47268.922311 # average overall miss latency 6139322Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 489 # number of cycles access was blocked 6148428SN/Asystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6159322Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked 6168428SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 6179322Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 44.454545 # average number of cycles each access was blocked 6188983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6198428SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 6208428SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 6219285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits 6229285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits 6239322Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 302 # number of WriteReq MSHR hits 6249322Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 302 # number of WriteReq MSHR hits 6259322Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 361 # number of demand (read+write) MSHR hits 6269322Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 361 # number of demand (read+write) MSHR hits 6279322Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 361 # number of overall MSHR hits 6289322Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 361 # number of overall MSHR hits 6299096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses 6309096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses 6318835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses 6328835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses 6339096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 6349096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses 6359096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 6369096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses 6379322Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5420000 # number of ReadReq MSHR miss cycles 6389322Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 5420000 # number of ReadReq MSHR miss cycles 6399322Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2754499 # number of WriteReq MSHR miss cycles 6409322Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 2754499 # number of WriteReq MSHR miss cycles 6419322Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 8174499 # number of demand (read+write) MSHR miss cycles 6429322Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 8174499 # number of demand (read+write) MSHR miss cycles 6439322Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 8174499 # number of overall MSHR miss cycles 6449322Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 8174499 # number of overall MSHR miss cycles 6459322Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045113 # mshr miss rate for ReadReq accesses 6469322Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045113 # mshr miss rate for ReadReq accesses 6478835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses 6489055Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses 6499322Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048288 # mshr miss rate for demand accesses 6509322Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.048288 # mshr miss rate for demand accesses 6519322Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048288 # mshr miss rate for overall accesses 6529322Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.048288 # mshr miss rate for overall accesses 6539322Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60222.222222 # average ReadReq mshr miss latency 6549322Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60222.222222 # average ReadReq mshr miss latency 6559322Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54009.784314 # average WriteReq mshr miss latency 6569322Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54009.784314 # average WriteReq mshr miss latency 6579322Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57975.170213 # average overall mshr miss latency 6589322Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 57975.170213 # average overall mshr miss latency 6599322Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57975.170213 # average overall mshr miss latency 6609322Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 57975.170213 # average overall mshr miss latency 6618428SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 6628428SN/Asystem.cpu.l2cache.replacements 0 # number of replacements 6639322Sandreas.hansson@arm.comsystem.cpu.l2cache.tagsinuse 224.543944 # Cycle average of tags in use 6648428SN/Asystem.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. 6659150SAli.Saidi@ARM.comsystem.cpu.l2cache.sampled_refs 429 # Sample count of references to valid blocks. 6669150SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_refs 0.006993 # Average number of references to valid blocks. 6678428SN/Asystem.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 6689322Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.inst 166.808951 # Average occupied blocks per requestor 6699322Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.data 57.734994 # Average occupied blocks per requestor 6709322Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.inst 0.005091 # Average percentage of cache occupancy 6719322Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.data 0.001762 # Average percentage of cache occupancy 6729322Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::total 0.006853 # Average percentage of cache occupancy 6738835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits 6748835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits 6758835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 6768835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 6778835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 6788835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 3 # number of overall hits 6799150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 339 # number of ReadReq misses 6809096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 90 # number of ReadReq misses 6819150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::total 429 # number of ReadReq misses 6828835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses 6838835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses 6849150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.inst 339 # number of demand (read+write) misses 6859096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 141 # number of demand (read+write) misses 6869150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::total 480 # number of demand (read+write) misses 6879150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.inst 339 # number of overall misses 6889096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses 6899150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::total 480 # number of overall misses 6909322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16691000 # number of ReadReq miss cycles 6919322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 5327000 # number of ReadReq miss cycles 6929322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 22018000 # number of ReadReq miss cycles 6939322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2702500 # number of ReadExReq miss cycles 6949322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 2702500 # number of ReadExReq miss cycles 6959322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 16691000 # number of demand (read+write) miss cycles 6969322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 8029500 # number of demand (read+write) miss cycles 6979322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 24720500 # number of demand (read+write) miss cycles 6989322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 16691000 # number of overall miss cycles 6999322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 8029500 # number of overall miss cycles 7009322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 24720500 # number of overall miss cycles 7019150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 342 # number of ReadReq accesses(hits+misses) 7029096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 90 # number of ReadReq accesses(hits+misses) 7039150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::total 432 # number of ReadReq accesses(hits+misses) 7048835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) 7058835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) 7069150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.inst 342 # number of demand (read+write) accesses 7079096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses 7089150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::total 483 # number of demand (read+write) accesses 7099150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.inst 342 # number of overall (read+write) accesses 7109096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses 7119150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::total 483 # number of overall (read+write) accesses 7129150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991228 # miss rate for ReadReq accesses 7138835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 7149150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.993056 # miss rate for ReadReq accesses 7158835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 7169055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 7179150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.991228 # miss rate for demand accesses 7188835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 7199150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::total 0.993789 # miss rate for demand accesses 7209150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.991228 # miss rate for overall accesses 7218835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 7229150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::total 0.993789 # miss rate for overall accesses 7239322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49235.988201 # average ReadReq miss latency 7249322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59188.888889 # average ReadReq miss latency 7259322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 51324.009324 # average ReadReq miss latency 7269322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52990.196078 # average ReadExReq miss latency 7279322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 52990.196078 # average ReadExReq miss latency 7289322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49235.988201 # average overall miss latency 7299322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 56946.808511 # average overall miss latency 7309322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 51501.041667 # average overall miss latency 7319322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49235.988201 # average overall miss latency 7329322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 56946.808511 # average overall miss latency 7339322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 51501.041667 # average overall miss latency 7348428SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 7358428SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 7368428SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 7378428SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 7388983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 7398983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 7408428SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 7418428SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 7429150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 339 # number of ReadReq MSHR misses 7439096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses 7449150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 429 # number of ReadReq MSHR misses 7458835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses 7468835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses 7479150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 339 # number of demand (read+write) MSHR misses 7489096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 7499150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::total 480 # number of demand (read+write) MSHR misses 7509150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 339 # number of overall MSHR misses 7519096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 7529150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::total 480 # number of overall MSHR misses 7539322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12421544 # number of ReadReq MSHR miss cycles 7549322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4218076 # number of ReadReq MSHR miss cycles 7559322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 16639620 # number of ReadReq MSHR miss cycles 7569322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2071054 # number of ReadExReq MSHR miss cycles 7579322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2071054 # number of ReadExReq MSHR miss cycles 7589322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12421544 # number of demand (read+write) MSHR miss cycles 7599322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6289130 # number of demand (read+write) MSHR miss cycles 7609322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 18710674 # number of demand (read+write) MSHR miss cycles 7619322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12421544 # number of overall MSHR miss cycles 7629322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6289130 # number of overall MSHR miss cycles 7639322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 18710674 # number of overall MSHR miss cycles 7649150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for ReadReq accesses 7658835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 7669150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993056 # mshr miss rate for ReadReq accesses 7678835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 7689055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 7699150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for demand accesses 7708835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 7719150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.993789 # mshr miss rate for demand accesses 7729150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for overall accesses 7738835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 7749150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.993789 # mshr miss rate for overall accesses 7759322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36641.722714 # average ReadReq mshr miss latency 7769322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46867.511111 # average ReadReq mshr miss latency 7779322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38786.993007 # average ReadReq mshr miss latency 7789322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40608.901961 # average ReadExReq mshr miss latency 7799322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40608.901961 # average ReadExReq mshr miss latency 7809322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36641.722714 # average overall mshr miss latency 7819322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44603.758865 # average overall mshr miss latency 7829322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 38980.570833 # average overall mshr miss latency 7839322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36641.722714 # average overall mshr miss latency 7849322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44603.758865 # average overall mshr miss latency 7859322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 38980.570833 # average overall mshr miss latency 7868428SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 7876039SN/A 7886039SN/A---------- End Simulation Statistics ---------- 789