stats.txt revision 9285
16039SN/A 26039SN/A---------- Begin Simulation Statistics ---------- 39096Sandreas.hansson@arm.comsim_seconds 0.000013 # Number of seconds simulated 49285Sandreas.hansson@arm.comsim_ticks 12603500 # Number of ticks simulated 59285Sandreas.hansson@arm.comfinal_tick 12603500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79285Sandreas.hansson@arm.comhost_inst_rate 49943 # Simulator instruction rate (inst/s) 89285Sandreas.hansson@arm.comhost_op_rate 49935 # Simulator op (including micro ops) rate (op/s) 99285Sandreas.hansson@arm.comhost_tick_rate 122043566 # Simulator tick rate (ticks/s) 109285Sandreas.hansson@arm.comhost_mem_usage 220512 # Number of bytes of host memory used 119096Sandreas.hansson@arm.comhost_seconds 0.10 # Real time elapsed on the host 129150SAli.Saidi@ARM.comsim_insts 5156 # Number of instructions simulated 139150SAli.Saidi@ARM.comsim_ops 5156 # Number of ops (including micro ops) simulated 149150SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.inst 21696 # Number of bytes read from this memory 159096Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory 169150SAli.Saidi@ARM.comsystem.physmem.bytes_read::total 30720 # Number of bytes read from this memory 179150SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::cpu.inst 21696 # Number of instructions bytes read from this memory 189150SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::total 21696 # Number of instructions bytes read from this memory 199150SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.inst 339 # Number of read requests responded to by this memory 209096Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory 219150SAli.Saidi@ARM.comsystem.physmem.num_reads::total 480 # Number of read requests responded to by this memory 229285Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 1721426588 # Total read bandwidth from this memory (bytes/s) 239285Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 715991590 # Total read bandwidth from this memory (bytes/s) 249285Sandreas.hansson@arm.comsystem.physmem.bw_read::total 2437418177 # Total read bandwidth from this memory (bytes/s) 259285Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 1721426588 # Instruction read bandwidth from this memory (bytes/s) 269285Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 1721426588 # Instruction read bandwidth from this memory (bytes/s) 279285Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 1721426588 # Total bandwidth to/from this memory (bytes/s) 289285Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 715991590 # Total bandwidth to/from this memory (bytes/s) 299285Sandreas.hansson@arm.comsystem.physmem.bw_total::total 2437418177 # Total bandwidth to/from this memory (bytes/s) 308428SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 318428SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 328428SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 338428SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 348428SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 358428SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 366039SN/Asystem.cpu.dtb.hits 0 # DTB hits 376039SN/Asystem.cpu.dtb.misses 0 # DTB misses 388428SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 398428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 408428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 418428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 428428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 438428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 448428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 458428SN/Asystem.cpu.itb.hits 0 # DTB hits 468428SN/Asystem.cpu.itb.misses 0 # DTB misses 478428SN/Asystem.cpu.itb.accesses 0 # DTB accesses 488428SN/Asystem.cpu.workload.num_syscalls 8 # Number of system calls 499285Sandreas.hansson@arm.comsystem.cpu.numCycles 25208 # number of cpu cycles simulated 508428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 518428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 529285Sandreas.hansson@arm.comsystem.cpu.BPredUnit.lookups 2076 # Number of BP lookups 539285Sandreas.hansson@arm.comsystem.cpu.BPredUnit.condPredicted 1377 # Number of conditional branches predicted 549150SAli.Saidi@ARM.comsystem.cpu.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect 559285Sandreas.hansson@arm.comsystem.cpu.BPredUnit.BTBLookups 1640 # Number of BTB lookups 569285Sandreas.hansson@arm.comsystem.cpu.BPredUnit.BTBHits 471 # Number of BTB hits 578428SN/Asystem.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 589285Sandreas.hansson@arm.comsystem.cpu.BPredUnit.usedRAS 262 # Number of times the RAS was used to get a target. 599096Sandreas.hansson@arm.comsystem.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. 609285Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 8496 # Number of cycles fetch is stalled on an Icache miss 619285Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 12782 # Number of instructions fetch has processed 629285Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 2076 # Number of branches that fetch encountered 639285Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 733 # Number of branches that fetch has predicted taken 649285Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 3147 # Number of cycles fetch has run and was not squashing or blocked 659285Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 1298 # Number of cycles fetch has spent squashing 669285Sandreas.hansson@arm.comsystem.cpu.fetch.BlockedCycles 705 # Number of cycles fetch has spent blocked 678464SN/Asystem.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 689079SAli.Saidi@ARM.comsystem.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps 699285Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 1923 # Number of cache lines fetched 709285Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 260 # Number of outstanding Icache misses that were squashed 719285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 13341 # Number of instructions fetched each cycle (Total) 729285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 0.958099 # Number of instructions fetched each cycle (Total) 739285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 2.266693 # Number of instructions fetched each cycle (Total) 746291SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 759285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 10194 76.41% 76.41% # Number of instructions fetched each cycle (Total) 769285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 1306 9.79% 86.20% # Number of instructions fetched each cycle (Total) 779285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 106 0.79% 86.99% # Number of instructions fetched each cycle (Total) 789285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 141 1.06% 88.05% # Number of instructions fetched each cycle (Total) 799285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 294 2.20% 90.26% # Number of instructions fetched each cycle (Total) 809285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 100 0.75% 91.01% # Number of instructions fetched each cycle (Total) 819285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 154 1.15% 92.16% # Number of instructions fetched each cycle (Total) 829285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 127 0.95% 93.11% # Number of instructions fetched each cycle (Total) 839285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 919 6.89% 100.00% # Number of instructions fetched each cycle (Total) 846291SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 856291SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 866291SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 879285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 13341 # Number of instructions fetched each cycle (Total) 889285Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.082355 # Number of branch fetches per cycle 899285Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.507061 # Number of inst fetches per cycle 909285Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 8622 # Number of cycles decode is idle 919285Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 899 # Number of cycles decode is blocked 929285Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 2969 # Number of cycles decode is running 939285Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 47 # Number of cycles decode is unblocking 949285Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 804 # Number of cycles decode is squashing 959285Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 145 # Number of times decode resolved a branch 969150SAli.Saidi@ARM.comsystem.cpu.decode.BranchMispred 46 # Number of times decode detected a branch misprediction 979285Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 11860 # Number of instructions handled by decode 989150SAli.Saidi@ARM.comsystem.cpu.decode.SquashedInsts 178 # Number of squashed instructions handled by decode 999285Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 804 # Number of cycles rename is squashing 1009285Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 8807 # Number of cycles rename is idle 1019285Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 246 # Number of cycles rename is blocking 1029285Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 544 # count of cycles rename stalled for serializing inst 1039285Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 2833 # Number of cycles rename is running 1049285Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 107 # Number of cycles rename is unblocking 1059285Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 11360 # Number of instructions processed by rename 1069285Sandreas.hansson@arm.comsystem.cpu.rename.LSQFullEvents 96 # Number of times rename has blocked due to LSQ full 1079285Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 6940 # Number of destination operands rename has renamed 1089285Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 13521 # Number of register rename lookups that rename has made 1099285Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 13517 # Number of integer rename lookups 1108554SN/Asystem.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups 1119150SAli.Saidi@ARM.comsystem.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed 1129285Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 3542 # Number of HB maps that are undone due to squashing 1139285Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 17 # count of serializing insts renamed 1149285Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed 1159285Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 277 # count of insts added to the skid buffer 1169285Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 2388 # Number of loads inserted to the mem dependence unit. 1179285Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 1175 # Number of stores inserted to the mem dependence unit. 1188428SN/Asystem.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 1198428SN/Asystem.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. 1209285Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 8869 # Number of instructions added to the IQ (excludes non-spec) 1219285Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ 1229285Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 8060 # Number of instructions issued 1239285Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 44 # Number of squashed instructions issued 1249285Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 3246 # Number of squashed instructions iterated over during squash; mainly for profiling 1259285Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 1840 # Number of squashed operands that are examined and possibly removed from graph 1269285Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed 1279285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 13341 # Number of insts issued each cycle 1289285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.604153 # Number of insts issued each cycle 1299285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.265993 # Number of insts issued each cycle 1308428SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1319285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 9853 73.86% 73.86% # Number of insts issued each cycle 1329285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 1401 10.50% 84.36% # Number of insts issued each cycle 1339285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 847 6.35% 90.71% # Number of insts issued each cycle 1349285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 533 4.00% 94.70% # Number of insts issued each cycle 1359285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 353 2.65% 97.35% # Number of insts issued each cycle 1369285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 227 1.70% 99.05% # Number of insts issued each cycle 1379285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 84 0.63% 99.68% # Number of insts issued each cycle 1389285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 29 0.22% 99.90% # Number of insts issued each cycle 1399285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle 1408428SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1418428SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1428428SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1439285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 13341 # Number of insts issued each cycle 1448428SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1459096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 3 1.97% 1.97% # attempts to use FU when none available 1469096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 1.97% # attempts to use FU when none available 1479096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 1.97% # attempts to use FU when none available 1489096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 1.97% # attempts to use FU when none available 1499096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 1.97% # attempts to use FU when none available 1509096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 1.97% # attempts to use FU when none available 1519096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 1.97% # attempts to use FU when none available 1529096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 1.97% # attempts to use FU when none available 1539096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.97% # attempts to use FU when none available 1549096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 1.97% # attempts to use FU when none available 1559096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.97% # attempts to use FU when none available 1569096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 1.97% # attempts to use FU when none available 1579096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 1.97% # attempts to use FU when none available 1589096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 1.97% # attempts to use FU when none available 1599096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 1.97% # attempts to use FU when none available 1609096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 1.97% # attempts to use FU when none available 1619096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.97% # attempts to use FU when none available 1629096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 1.97% # attempts to use FU when none available 1639096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.97% # attempts to use FU when none available 1649096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.97% # attempts to use FU when none available 1659096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.97% # attempts to use FU when none available 1669096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.97% # attempts to use FU when none available 1679096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.97% # attempts to use FU when none available 1689096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.97% # attempts to use FU when none available 1699096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.97% # attempts to use FU when none available 1709096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.97% # attempts to use FU when none available 1719096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.97% # attempts to use FU when none available 1729096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.97% # attempts to use FU when none available 1739096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.97% # attempts to use FU when none available 1749096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 97 63.82% 65.79% # attempts to use FU when none available 1759079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::MemWrite 52 34.21% 100.00% # attempts to use FU when none available 1768428SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1778428SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1788241SN/Asystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 1799285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 4766 59.13% 59.13% # Type of FU issued 1809285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 5 0.06% 59.19% # Type of FU issued 1819285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.22% # Type of FU issued 1829285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.24% # Type of FU issued 1839285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.24% # Type of FU issued 1849285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.24% # Type of FU issued 1859285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.24% # Type of FU issued 1869285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.24% # Type of FU issued 1879285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.24% # Type of FU issued 1889285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.24% # Type of FU issued 1899285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.24% # Type of FU issued 1909285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.24% # Type of FU issued 1919285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.24% # Type of FU issued 1929285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.24% # Type of FU issued 1939285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.24% # Type of FU issued 1949285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.24% # Type of FU issued 1959285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.24% # Type of FU issued 1969285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.24% # Type of FU issued 1979285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.24% # Type of FU issued 1989285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.24% # Type of FU issued 1999285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.24% # Type of FU issued 2009285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.24% # Type of FU issued 2019285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.24% # Type of FU issued 2029285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.24% # Type of FU issued 2039285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.24% # Type of FU issued 2049285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.24% # Type of FU issued 2059285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.24% # Type of FU issued 2069285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.24% # Type of FU issued 2079285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.24% # Type of FU issued 2089285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 2195 27.23% 86.48% # Type of FU issued 2099285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 1090 13.52% 100.00% # Type of FU issued 2108241SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2118241SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 2129285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 8060 # Type of FU issued 2139285Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.319740 # Inst issue rate 2148844SAli.Saidi@ARM.comsystem.cpu.iq.fu_busy_cnt 152 # FU busy when requested 2159285Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.018859 # FU busy rate (busy events/executed inst) 2169285Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 29653 # Number of integer instruction queue reads 2179285Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 12136 # Number of integer instruction queue writes 2189285Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 7261 # Number of integer instruction queue wakeup accesses 2198428SN/Asystem.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads 2208428SN/Asystem.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 2218428SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses 2229285Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 8210 # Number of integer alu accesses 2238428SN/Asystem.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses 2249096Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores 2258428SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2269285Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1225 # Number of loads squashed 2279096Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed 2289150SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations 2299285Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 250 # Number of stores squashed 2308428SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2318428SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2328428SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 2338428SN/Asystem.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 2348428SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2359285Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 804 # Number of cycles IEW is squashing 2369285Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 170 # Number of cycles IEW is blocking 2379285Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking 2389285Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 10299 # Number of instructions dispatched to IQ 2399285Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch 2409285Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 2388 # Number of dispatched load instructions 2419285Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 1175 # Number of dispatched store instructions 2429285Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions 2438844SAli.Saidi@ARM.comsystem.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall 2449079SAli.Saidi@ARM.comsystem.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall 2459150SAli.Saidi@ARM.comsystem.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations 2469285Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 105 # Number of branches that were predicted taken incorrectly 2479150SAli.Saidi@ARM.comsystem.cpu.iew.predictedNotTakenIncorrect 360 # Number of branches that were predicted not taken incorrectly 2489285Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 465 # Number of branch mispredicts detected at execute 2499285Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 7692 # Number of executed instructions 2509285Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 2065 # Number of load instructions executed 2519285Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 368 # Number of squashed instructions skipped in execute 2528428SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 2539285Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 1417 # number of nop insts executed 2549285Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 3127 # number of memory reference insts executed 2559285Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 1305 # Number of branches executed 2569150SAli.Saidi@ARM.comsystem.cpu.iew.exec_stores 1062 # Number of stores executed 2579285Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.305141 # Inst execution rate 2589285Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 7351 # cumulative count of insts sent to commit 2599285Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 7263 # cumulative count of insts written-back 2609285Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 2827 # num instructions producing a value 2619285Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 4035 # num instructions consuming a value 2628428SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 2639285Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.288123 # insts written-back per cycle 2649285Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.700620 # average fanout of values written-back 2658428SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 2669285Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 4478 # The number of squashed insts skipped by commit 2678428SN/Asystem.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards 2689150SAli.Saidi@ARM.comsystem.cpu.commit.branchMispredicts 395 # The number of times a branch was mispredicted 2699285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 12537 # Number of insts commited each cycle 2709285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.463668 # Number of insts commited each cycle 2719285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.253066 # Number of insts commited each cycle 2728428SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2739285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 10143 80.90% 80.90% # Number of insts commited each cycle 2749285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 988 7.88% 88.79% # Number of insts commited each cycle 2759285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 634 5.06% 93.84% # Number of insts commited each cycle 2769285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 313 2.50% 96.34% # Number of insts commited each cycle 2779285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 148 1.18% 97.52% # Number of insts commited each cycle 2789285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 91 0.73% 98.25% # Number of insts commited each cycle 2799285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 75 0.60% 98.84% # Number of insts commited each cycle 2809285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 39 0.31% 99.15% # Number of insts commited each cycle 2819285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 106 0.85% 100.00% # Number of insts commited each cycle 2828428SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2838428SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2848428SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 2859285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 12537 # Number of insts commited each cycle 2869150SAli.Saidi@ARM.comsystem.cpu.commit.committedInsts 5813 # Number of instructions committed 2879150SAli.Saidi@ARM.comsystem.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed 2888428SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 2899150SAli.Saidi@ARM.comsystem.cpu.commit.refs 2088 # Number of memory references committed 2909150SAli.Saidi@ARM.comsystem.cpu.commit.loads 1163 # Number of loads committed 2918428SN/Asystem.cpu.commit.membars 0 # Number of memory barriers committed 2929150SAli.Saidi@ARM.comsystem.cpu.commit.branches 915 # Number of branches committed 2938428SN/Asystem.cpu.commit.fp_insts 2 # Number of committed floating point instructions. 2949150SAli.Saidi@ARM.comsystem.cpu.commit.int_insts 5111 # Number of committed integer instructions. 2958428SN/Asystem.cpu.commit.function_calls 87 # Number of function calls committed. 2969096Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached 2978428SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 2989285Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 22709 # The number of ROB reads 2999285Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 21393 # The number of ROB writes 3009150SAli.Saidi@ARM.comsystem.cpu.timesIdled 269 # Number of times that the entire CPU went into an idle state and unscheduled itself 3019285Sandreas.hansson@arm.comsystem.cpu.idleCycles 11867 # Total number of cycles that the CPU has spent unscheduled due to idling 3029150SAli.Saidi@ARM.comsystem.cpu.committedInsts 5156 # Number of Instructions Simulated 3039150SAli.Saidi@ARM.comsystem.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated 3049150SAli.Saidi@ARM.comsystem.cpu.committedInsts_total 5156 # Number of Instructions Simulated 3059285Sandreas.hansson@arm.comsystem.cpu.cpi 4.889061 # CPI: Cycles Per Instruction 3069285Sandreas.hansson@arm.comsystem.cpu.cpi_total 4.889061 # CPI: Total CPI of All Threads 3079285Sandreas.hansson@arm.comsystem.cpu.ipc 0.204538 # IPC: Instructions Per Cycle 3089285Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.204538 # IPC: Total IPC of All Threads 3099285Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 10482 # number of integer regfile reads 3109285Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 5097 # number of integer regfile writes 3118428SN/Asystem.cpu.fp_regfile_reads 3 # number of floating regfile reads 3128428SN/Asystem.cpu.fp_regfile_writes 1 # number of floating regfile writes 3139285Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 151 # number of misc regfile reads 3149079SAli.Saidi@ARM.comsystem.cpu.icache.replacements 17 # number of replacements 3159285Sandreas.hansson@arm.comsystem.cpu.icache.tagsinuse 161.691170 # Cycle average of tags in use 3169285Sandreas.hansson@arm.comsystem.cpu.icache.total_refs 1486 # Total number of references to valid blocks. 3179150SAli.Saidi@ARM.comsystem.cpu.icache.sampled_refs 342 # Sample count of references to valid blocks. 3189285Sandreas.hansson@arm.comsystem.cpu.icache.avg_refs 4.345029 # Average number of references to valid blocks. 3198428SN/Asystem.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 3209285Sandreas.hansson@arm.comsystem.cpu.icache.occ_blocks::cpu.inst 161.691170 # Average occupied blocks per requestor 3219285Sandreas.hansson@arm.comsystem.cpu.icache.occ_percent::cpu.inst 0.078951 # Average percentage of cache occupancy 3229285Sandreas.hansson@arm.comsystem.cpu.icache.occ_percent::total 0.078951 # Average percentage of cache occupancy 3239285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1486 # number of ReadReq hits 3249285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 1486 # number of ReadReq hits 3259285Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 1486 # number of demand (read+write) hits 3269285Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 1486 # number of demand (read+write) hits 3279285Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 1486 # number of overall hits 3289285Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 1486 # number of overall hits 3299285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses 3309285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses 3319285Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses 3329285Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses 3339285Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses 3349285Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 437 # number of overall misses 3359285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 15633000 # number of ReadReq miss cycles 3369285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 15633000 # number of ReadReq miss cycles 3379285Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 15633000 # number of demand (read+write) miss cycles 3389285Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 15633000 # number of demand (read+write) miss cycles 3399285Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 15633000 # number of overall miss cycles 3409285Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 15633000 # number of overall miss cycles 3419285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 1923 # number of ReadReq accesses(hits+misses) 3429285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 1923 # number of ReadReq accesses(hits+misses) 3439285Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 1923 # number of demand (read+write) accesses 3449285Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 1923 # number of demand (read+write) accesses 3459285Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 1923 # number of overall (read+write) accesses 3469285Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 1923 # number of overall (read+write) accesses 3479285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.227249 # miss rate for ReadReq accesses 3489285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.227249 # miss rate for ReadReq accesses 3499285Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.227249 # miss rate for demand accesses 3509285Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.227249 # miss rate for demand accesses 3519285Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.227249 # miss rate for overall accesses 3529285Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.227249 # miss rate for overall accesses 3539285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35773.455378 # average ReadReq miss latency 3549285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 35773.455378 # average ReadReq miss latency 3559285Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 35773.455378 # average overall miss latency 3569285Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 35773.455378 # average overall miss latency 3579285Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 35773.455378 # average overall miss latency 3589285Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 35773.455378 # average overall miss latency 3598428SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3608428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3618428SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 3628428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 3638983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3648983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3658428SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 3668428SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 3679285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 95 # number of ReadReq MSHR hits 3689285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 95 # number of ReadReq MSHR hits 3699285Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 95 # number of demand (read+write) MSHR hits 3709285Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 95 # number of demand (read+write) MSHR hits 3719285Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 95 # number of overall MSHR hits 3729285Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 95 # number of overall MSHR hits 3739150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 342 # number of ReadReq MSHR misses 3749150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::total 342 # number of ReadReq MSHR misses 3759150SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 342 # number of demand (read+write) MSHR misses 3769150SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::total 342 # number of demand (read+write) MSHR misses 3779150SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 342 # number of overall MSHR misses 3789150SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::total 342 # number of overall MSHR misses 3799285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12431000 # number of ReadReq MSHR miss cycles 3809285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 12431000 # number of ReadReq MSHR miss cycles 3819285Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 12431000 # number of demand (read+write) MSHR miss cycles 3829285Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 12431000 # number of demand (read+write) MSHR miss cycles 3839285Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 12431000 # number of overall MSHR miss cycles 3849285Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 12431000 # number of overall MSHR miss cycles 3859285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.177847 # mshr miss rate for ReadReq accesses 3869285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.177847 # mshr miss rate for ReadReq accesses 3879285Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.177847 # mshr miss rate for demand accesses 3889285Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.177847 # mshr miss rate for demand accesses 3899285Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.177847 # mshr miss rate for overall accesses 3909285Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.177847 # mshr miss rate for overall accesses 3919285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36347.953216 # average ReadReq mshr miss latency 3929285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36347.953216 # average ReadReq mshr miss latency 3939285Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36347.953216 # average overall mshr miss latency 3949285Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 36347.953216 # average overall mshr miss latency 3959285Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36347.953216 # average overall mshr miss latency 3969285Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 36347.953216 # average overall mshr miss latency 3978428SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 3988428SN/Asystem.cpu.dcache.replacements 0 # number of replacements 3999285Sandreas.hansson@arm.comsystem.cpu.dcache.tagsinuse 90.751581 # Cycle average of tags in use 4009285Sandreas.hansson@arm.comsystem.cpu.dcache.total_refs 2409 # Total number of references to valid blocks. 4019096Sandreas.hansson@arm.comsystem.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. 4029285Sandreas.hansson@arm.comsystem.cpu.dcache.avg_refs 17.085106 # Average number of references to valid blocks. 4038428SN/Asystem.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 4049285Sandreas.hansson@arm.comsystem.cpu.dcache.occ_blocks::cpu.data 90.751581 # Average occupied blocks per requestor 4059285Sandreas.hansson@arm.comsystem.cpu.dcache.occ_percent::cpu.data 0.022156 # Average percentage of cache occupancy 4069285Sandreas.hansson@arm.comsystem.cpu.dcache.occ_percent::total 0.022156 # Average percentage of cache occupancy 4079285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1833 # number of ReadReq hits 4089285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 1833 # number of ReadReq hits 4099285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 576 # number of WriteReq hits 4109285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 576 # number of WriteReq hits 4119285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 2409 # number of demand (read+write) hits 4129285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 2409 # number of demand (read+write) hits 4139285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 2409 # number of overall hits 4149285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 2409 # number of overall hits 4159285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 149 # number of ReadReq misses 4169285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 149 # number of ReadReq misses 4179285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 349 # number of WriteReq misses 4189285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 349 # number of WriteReq misses 4199285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses 4209285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses 4219285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses 4229285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 498 # number of overall misses 4239285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 5432500 # number of ReadReq miss cycles 4249285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 5432500 # number of ReadReq miss cycles 4259285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 11660000 # number of WriteReq miss cycles 4269285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 11660000 # number of WriteReq miss cycles 4279285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 17092500 # number of demand (read+write) miss cycles 4289285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 17092500 # number of demand (read+write) miss cycles 4299285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 17092500 # number of overall miss cycles 4309285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 17092500 # number of overall miss cycles 4319285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1982 # number of ReadReq accesses(hits+misses) 4329285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 1982 # number of ReadReq accesses(hits+misses) 4338835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 4348835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 4359285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 2907 # number of demand (read+write) accesses 4369285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 2907 # number of demand (read+write) accesses 4379285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 2907 # number of overall (read+write) accesses 4389285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 2907 # number of overall (read+write) accesses 4399285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075177 # miss rate for ReadReq accesses 4409285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.075177 # miss rate for ReadReq accesses 4419285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.377297 # miss rate for WriteReq accesses 4429285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.377297 # miss rate for WriteReq accesses 4439285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.171311 # miss rate for demand accesses 4449285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.171311 # miss rate for demand accesses 4459285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.171311 # miss rate for overall accesses 4469285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.171311 # miss rate for overall accesses 4479285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36459.731544 # average ReadReq miss latency 4489285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 36459.731544 # average ReadReq miss latency 4499285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33409.742120 # average WriteReq miss latency 4509285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 33409.742120 # average WriteReq miss latency 4519285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 34322.289157 # average overall miss latency 4529285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 34322.289157 # average overall miss latency 4539285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 34322.289157 # average overall miss latency 4549285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 34322.289157 # average overall miss latency 4558428SN/Asystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4568428SN/Asystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4578428SN/Asystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 4588428SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 4598983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 4608983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 4618428SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 4628428SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 4639285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits 4649285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits 4659285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 298 # number of WriteReq MSHR hits 4669285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 298 # number of WriteReq MSHR hits 4679285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 357 # number of demand (read+write) MSHR hits 4689285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 357 # number of demand (read+write) MSHR hits 4699285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 357 # number of overall MSHR hits 4709285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 357 # number of overall MSHR hits 4719096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses 4729096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses 4738835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses 4748835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses 4759096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 4769096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses 4779096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 4789096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses 4799285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3834500 # number of ReadReq MSHR miss cycles 4809285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 3834500 # number of ReadReq MSHR miss cycles 4819285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2072000 # number of WriteReq MSHR miss cycles 4829285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 2072000 # number of WriteReq MSHR miss cycles 4839285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 5906500 # number of demand (read+write) MSHR miss cycles 4849285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 5906500 # number of demand (read+write) MSHR miss cycles 4859285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 5906500 # number of overall MSHR miss cycles 4869285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 5906500 # number of overall MSHR miss cycles 4879285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045409 # mshr miss rate for ReadReq accesses 4889285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045409 # mshr miss rate for ReadReq accesses 4898835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses 4909055Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses 4919285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048504 # mshr miss rate for demand accesses 4929285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.048504 # mshr miss rate for demand accesses 4939285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048504 # mshr miss rate for overall accesses 4949285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.048504 # mshr miss rate for overall accesses 4959285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 42605.555556 # average ReadReq mshr miss latency 4969285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 42605.555556 # average ReadReq mshr miss latency 4979285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40627.450980 # average WriteReq mshr miss latency 4989285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40627.450980 # average WriteReq mshr miss latency 4999285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 41890.070922 # average overall mshr miss latency 5009285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 41890.070922 # average overall mshr miss latency 5019285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 41890.070922 # average overall mshr miss latency 5029285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 41890.070922 # average overall mshr miss latency 5038428SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 5048428SN/Asystem.cpu.l2cache.replacements 0 # number of replacements 5059285Sandreas.hansson@arm.comsystem.cpu.l2cache.tagsinuse 220.970580 # Cycle average of tags in use 5068428SN/Asystem.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. 5079150SAli.Saidi@ARM.comsystem.cpu.l2cache.sampled_refs 429 # Sample count of references to valid blocks. 5089150SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_refs 0.006993 # Average number of references to valid blocks. 5098428SN/Asystem.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 5109285Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.inst 163.825301 # Average occupied blocks per requestor 5119285Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.data 57.145280 # Average occupied blocks per requestor 5129285Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.inst 0.005000 # Average percentage of cache occupancy 5139285Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.data 0.001744 # Average percentage of cache occupancy 5149285Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::total 0.006743 # Average percentage of cache occupancy 5158835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits 5168835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits 5178835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 5188835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 5198835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 5208835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 3 # number of overall hits 5219150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 339 # number of ReadReq misses 5229096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 90 # number of ReadReq misses 5239150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::total 429 # number of ReadReq misses 5248835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses 5258835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses 5269150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.inst 339 # number of demand (read+write) misses 5279096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 141 # number of demand (read+write) misses 5289150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::total 480 # number of demand (read+write) misses 5299150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.inst 339 # number of overall misses 5309096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses 5319150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::total 480 # number of overall misses 5329285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12084000 # number of ReadReq miss cycles 5339285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 3740000 # number of ReadReq miss cycles 5349285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 15824000 # number of ReadReq miss cycles 5359285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2020500 # number of ReadExReq miss cycles 5369285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 2020500 # number of ReadExReq miss cycles 5379285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 12084000 # number of demand (read+write) miss cycles 5389285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 5760500 # number of demand (read+write) miss cycles 5399285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 17844500 # number of demand (read+write) miss cycles 5409285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 12084000 # number of overall miss cycles 5419285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 5760500 # number of overall miss cycles 5429285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 17844500 # number of overall miss cycles 5439150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 342 # number of ReadReq accesses(hits+misses) 5449096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 90 # number of ReadReq accesses(hits+misses) 5459150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::total 432 # number of ReadReq accesses(hits+misses) 5468835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) 5478835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) 5489150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.inst 342 # number of demand (read+write) accesses 5499096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses 5509150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::total 483 # number of demand (read+write) accesses 5519150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.inst 342 # number of overall (read+write) accesses 5529096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses 5539150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::total 483 # number of overall (read+write) accesses 5549150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991228 # miss rate for ReadReq accesses 5558835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 5569150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.993056 # miss rate for ReadReq accesses 5578835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 5589055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 5599150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.991228 # miss rate for demand accesses 5608835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 5619150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::total 0.993789 # miss rate for demand accesses 5629150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.991228 # miss rate for overall accesses 5638835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 5649150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::total 0.993789 # miss rate for overall accesses 5659285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35646.017699 # average ReadReq miss latency 5669285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 41555.555556 # average ReadReq miss latency 5679285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 36885.780886 # average ReadReq miss latency 5689285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39617.647059 # average ReadExReq miss latency 5699285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 39617.647059 # average ReadExReq miss latency 5709285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35646.017699 # average overall miss latency 5719285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 40854.609929 # average overall miss latency 5729285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 37176.041667 # average overall miss latency 5739285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35646.017699 # average overall miss latency 5749285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 40854.609929 # average overall miss latency 5759285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 37176.041667 # average overall miss latency 5768428SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5778428SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5788428SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 5798428SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 5808983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5818983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5828428SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 5838428SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 5849150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 339 # number of ReadReq MSHR misses 5859096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses 5869150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 429 # number of ReadReq MSHR misses 5878835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses 5888835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses 5899150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 339 # number of demand (read+write) MSHR misses 5909096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 5919150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::total 480 # number of demand (read+write) MSHR misses 5929150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 339 # number of overall MSHR misses 5939096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 5949150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::total 480 # number of overall MSHR misses 5959285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11000500 # number of ReadReq MSHR miss cycles 5969285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3465500 # number of ReadReq MSHR miss cycles 5979285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 14466000 # number of ReadReq MSHR miss cycles 5989285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1861500 # number of ReadExReq MSHR miss cycles 5999285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1861500 # number of ReadExReq MSHR miss cycles 6009285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11000500 # number of demand (read+write) MSHR miss cycles 6019285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5327000 # number of demand (read+write) MSHR miss cycles 6029285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 16327500 # number of demand (read+write) MSHR miss cycles 6039285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11000500 # number of overall MSHR miss cycles 6049285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5327000 # number of overall MSHR miss cycles 6059285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 16327500 # number of overall MSHR miss cycles 6069150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for ReadReq accesses 6078835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 6089150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993056 # mshr miss rate for ReadReq accesses 6098835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 6109055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 6119150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for demand accesses 6128835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 6139150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.993789 # mshr miss rate for demand accesses 6149150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for overall accesses 6158835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 6169150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.993789 # mshr miss rate for overall accesses 6179285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32449.852507 # average ReadReq mshr miss latency 6189285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38505.555556 # average ReadReq mshr miss latency 6199285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33720.279720 # average ReadReq mshr miss latency 6209285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36500 # average ReadExReq mshr miss latency 6219285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36500 # average ReadExReq mshr miss latency 6229285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32449.852507 # average overall mshr miss latency 6239285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37780.141844 # average overall mshr miss latency 6249285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 34015.625000 # average overall mshr miss latency 6259285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32449.852507 # average overall mshr miss latency 6269285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37780.141844 # average overall mshr miss latency 6279285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 34015.625000 # average overall mshr miss latency 6288428SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 6296039SN/A 6306039SN/A---------- End Simulation Statistics ---------- 631