stats.txt revision 9150
16039SN/A 26039SN/A---------- Begin Simulation Statistics ---------- 39096Sandreas.hansson@arm.comsim_seconds 0.000013 # Number of seconds simulated 49150SAli.Saidi@ARM.comsim_ticks 12925500 # Number of ticks simulated 59150SAli.Saidi@ARM.comfinal_tick 12925500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79150SAli.Saidi@ARM.comhost_inst_rate 52967 # Simulator instruction rate (inst/s) 89150SAli.Saidi@ARM.comhost_op_rate 52957 # Simulator op (including micro ops) rate (op/s) 99150SAli.Saidi@ARM.comhost_tick_rate 132735366 # Simulator tick rate (ticks/s) 109150SAli.Saidi@ARM.comhost_mem_usage 224404 # Number of bytes of host memory used 119096Sandreas.hansson@arm.comhost_seconds 0.10 # Real time elapsed on the host 129150SAli.Saidi@ARM.comsim_insts 5156 # Number of instructions simulated 139150SAli.Saidi@ARM.comsim_ops 5156 # Number of ops (including micro ops) simulated 149150SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.inst 21696 # Number of bytes read from this memory 159096Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory 169150SAli.Saidi@ARM.comsystem.physmem.bytes_read::total 30720 # Number of bytes read from this memory 179150SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::cpu.inst 21696 # Number of instructions bytes read from this memory 189150SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::total 21696 # Number of instructions bytes read from this memory 199150SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.inst 339 # Number of read requests responded to by this memory 209096Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory 219150SAli.Saidi@ARM.comsystem.physmem.num_reads::total 480 # Number of read requests responded to by this memory 229150SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.inst 1678542416 # Total read bandwidth from this memory (bytes/s) 239150SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.data 698154810 # Total read bandwidth from this memory (bytes/s) 249150SAli.Saidi@ARM.comsystem.physmem.bw_read::total 2376697226 # Total read bandwidth from this memory (bytes/s) 259150SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::cpu.inst 1678542416 # Instruction read bandwidth from this memory (bytes/s) 269150SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::total 1678542416 # Instruction read bandwidth from this memory (bytes/s) 279150SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.inst 1678542416 # Total bandwidth to/from this memory (bytes/s) 289150SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.data 698154810 # Total bandwidth to/from this memory (bytes/s) 299150SAli.Saidi@ARM.comsystem.physmem.bw_total::total 2376697226 # Total bandwidth to/from this memory (bytes/s) 308428SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 318428SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 328428SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 338428SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 348428SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 358428SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 366039SN/Asystem.cpu.dtb.hits 0 # DTB hits 376039SN/Asystem.cpu.dtb.misses 0 # DTB misses 388428SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 398428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 408428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 418428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 428428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 438428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 448428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 458428SN/Asystem.cpu.itb.hits 0 # DTB hits 468428SN/Asystem.cpu.itb.misses 0 # DTB misses 478428SN/Asystem.cpu.itb.accesses 0 # DTB accesses 488428SN/Asystem.cpu.workload.num_syscalls 8 # Number of system calls 499150SAli.Saidi@ARM.comsystem.cpu.numCycles 25852 # number of cpu cycles simulated 508428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 518428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 529150SAli.Saidi@ARM.comsystem.cpu.BPredUnit.lookups 2052 # Number of BP lookups 539150SAli.Saidi@ARM.comsystem.cpu.BPredUnit.condPredicted 1365 # Number of conditional branches predicted 549150SAli.Saidi@ARM.comsystem.cpu.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect 559150SAli.Saidi@ARM.comsystem.cpu.BPredUnit.BTBLookups 1625 # Number of BTB lookups 569150SAli.Saidi@ARM.comsystem.cpu.BPredUnit.BTBHits 468 # Number of BTB hits 578428SN/Asystem.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 589150SAli.Saidi@ARM.comsystem.cpu.BPredUnit.usedRAS 254 # Number of times the RAS was used to get a target. 599096Sandreas.hansson@arm.comsystem.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. 609150SAli.Saidi@ARM.comsystem.cpu.fetch.icacheStallCycles 8806 # Number of cycles fetch is stalled on an Icache miss 619150SAli.Saidi@ARM.comsystem.cpu.fetch.Insts 12660 # Number of instructions fetch has processed 629150SAli.Saidi@ARM.comsystem.cpu.fetch.Branches 2052 # Number of branches that fetch encountered 639150SAli.Saidi@ARM.comsystem.cpu.fetch.predictedBranches 722 # Number of branches that fetch has predicted taken 649150SAli.Saidi@ARM.comsystem.cpu.fetch.Cycles 3113 # Number of cycles fetch has run and was not squashing or blocked 659150SAli.Saidi@ARM.comsystem.cpu.fetch.SquashCycles 1287 # Number of cycles fetch has spent squashing 669150SAli.Saidi@ARM.comsystem.cpu.fetch.BlockedCycles 809 # Number of cycles fetch has spent blocked 678464SN/Asystem.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 689079SAli.Saidi@ARM.comsystem.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps 699150SAli.Saidi@ARM.comsystem.cpu.fetch.CacheLines 1908 # Number of cache lines fetched 709150SAli.Saidi@ARM.comsystem.cpu.fetch.IcacheSquashes 272 # Number of outstanding Icache misses that were squashed 719150SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::samples 13710 # Number of instructions fetched each cycle (Total) 729150SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::mean 0.923414 # Number of instructions fetched each cycle (Total) 739150SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::stdev 2.233238 # Number of instructions fetched each cycle (Total) 746291SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 759150SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::0 10597 77.29% 77.29% # Number of instructions fetched each cycle (Total) 769150SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::1 1289 9.40% 86.70% # Number of instructions fetched each cycle (Total) 779150SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::2 106 0.77% 87.47% # Number of instructions fetched each cycle (Total) 789150SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::3 138 1.01% 88.48% # Number of instructions fetched each cycle (Total) 799150SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::4 293 2.14% 90.61% # Number of instructions fetched each cycle (Total) 809150SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::5 99 0.72% 91.33% # Number of instructions fetched each cycle (Total) 819150SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::6 151 1.10% 92.44% # Number of instructions fetched each cycle (Total) 829150SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::7 124 0.90% 93.34% # Number of instructions fetched each cycle (Total) 839150SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::8 913 6.66% 100.00% # Number of instructions fetched each cycle (Total) 846291SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 856291SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 866291SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 879150SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::total 13710 # Number of instructions fetched each cycle (Total) 889150SAli.Saidi@ARM.comsystem.cpu.fetch.branchRate 0.079375 # Number of branch fetches per cycle 899150SAli.Saidi@ARM.comsystem.cpu.fetch.rate 0.489711 # Number of inst fetches per cycle 909150SAli.Saidi@ARM.comsystem.cpu.decode.IdleCycles 8966 # Number of cycles decode is idle 919150SAli.Saidi@ARM.comsystem.cpu.decode.BlockedCycles 966 # Number of cycles decode is blocked 929150SAli.Saidi@ARM.comsystem.cpu.decode.RunCycles 2934 # Number of cycles decode is running 939096Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 51 # Number of cycles decode is unblocking 949150SAli.Saidi@ARM.comsystem.cpu.decode.SquashCycles 793 # Number of cycles decode is squashing 959150SAli.Saidi@ARM.comsystem.cpu.decode.BranchResolved 143 # Number of times decode resolved a branch 969150SAli.Saidi@ARM.comsystem.cpu.decode.BranchMispred 46 # Number of times decode detected a branch misprediction 979150SAli.Saidi@ARM.comsystem.cpu.decode.DecodedInsts 11758 # Number of instructions handled by decode 989150SAli.Saidi@ARM.comsystem.cpu.decode.SquashedInsts 178 # Number of squashed instructions handled by decode 999150SAli.Saidi@ARM.comsystem.cpu.rename.SquashCycles 793 # Number of cycles rename is squashing 1009150SAli.Saidi@ARM.comsystem.cpu.rename.IdleCycles 9155 # Number of cycles rename is idle 1019150SAli.Saidi@ARM.comsystem.cpu.rename.BlockCycles 277 # Number of cycles rename is blocking 1029096Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 540 # count of cycles rename stalled for serializing inst 1039150SAli.Saidi@ARM.comsystem.cpu.rename.RunCycles 2801 # Number of cycles rename is running 1049150SAli.Saidi@ARM.comsystem.cpu.rename.UnblockCycles 144 # Number of cycles rename is unblocking 1059150SAli.Saidi@ARM.comsystem.cpu.rename.RenamedInsts 11265 # Number of instructions processed by rename 1069096Sandreas.hansson@arm.comsystem.cpu.rename.LSQFullEvents 129 # Number of times rename has blocked due to LSQ full 1079150SAli.Saidi@ARM.comsystem.cpu.rename.RenamedOperands 6879 # Number of destination operands rename has renamed 1089150SAli.Saidi@ARM.comsystem.cpu.rename.RenameLookups 13414 # Number of register rename lookups that rename has made 1099150SAli.Saidi@ARM.comsystem.cpu.rename.int_rename_lookups 13410 # Number of integer rename lookups 1108554SN/Asystem.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups 1119150SAli.Saidi@ARM.comsystem.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed 1129150SAli.Saidi@ARM.comsystem.cpu.rename.UndoneMaps 3481 # Number of HB maps that are undone due to squashing 1139096Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 16 # count of serializing insts renamed 1149096Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed 1159150SAli.Saidi@ARM.comsystem.cpu.rename.skidInsts 314 # count of insts added to the skid buffer 1169150SAli.Saidi@ARM.comsystem.cpu.memDep0.insertedLoads 2372 # Number of loads inserted to the mem dependence unit. 1179150SAli.Saidi@ARM.comsystem.cpu.memDep0.insertedStores 1172 # Number of stores inserted to the mem dependence unit. 1188428SN/Asystem.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 1198428SN/Asystem.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. 1209150SAli.Saidi@ARM.comsystem.cpu.iq.iqInstsAdded 8819 # Number of instructions added to the IQ (excludes non-spec) 1219096Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ 1229150SAli.Saidi@ARM.comsystem.cpu.iq.iqInstsIssued 8008 # Number of instructions issued 1239150SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedInstsIssued 47 # Number of squashed instructions issued 1249150SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedInstsExamined 3225 # Number of squashed instructions iterated over during squash; mainly for profiling 1259150SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedOperandsExamined 1836 # Number of squashed operands that are examined and possibly removed from graph 1269096Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed 1279150SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::samples 13710 # Number of insts issued each cycle 1289150SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::mean 0.584099 # Number of insts issued each cycle 1299150SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::stdev 1.244040 # Number of insts issued each cycle 1308428SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1319150SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::0 10210 74.47% 74.47% # Number of insts issued each cycle 1329150SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::1 1436 10.47% 84.95% # Number of insts issued each cycle 1339150SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::2 842 6.14% 91.09% # Number of insts issued each cycle 1349150SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::3 525 3.83% 94.92% # Number of insts issued each cycle 1359150SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::4 351 2.56% 97.48% # Number of insts issued each cycle 1369150SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::5 220 1.60% 99.08% # Number of insts issued each cycle 1379150SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::6 85 0.62% 99.70% # Number of insts issued each cycle 1389150SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::7 29 0.21% 99.91% # Number of insts issued each cycle 1399150SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle 1408428SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1418428SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1428428SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1439150SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::total 13710 # Number of insts issued each cycle 1448428SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1459096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 3 1.97% 1.97% # attempts to use FU when none available 1469096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 1.97% # attempts to use FU when none available 1479096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 1.97% # attempts to use FU when none available 1489096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 1.97% # attempts to use FU when none available 1499096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 1.97% # attempts to use FU when none available 1509096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 1.97% # attempts to use FU when none available 1519096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 1.97% # attempts to use FU when none available 1529096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 1.97% # attempts to use FU when none available 1539096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.97% # attempts to use FU when none available 1549096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 1.97% # attempts to use FU when none available 1559096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.97% # attempts to use FU when none available 1569096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 1.97% # attempts to use FU when none available 1579096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 1.97% # attempts to use FU when none available 1589096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 1.97% # attempts to use FU when none available 1599096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 1.97% # attempts to use FU when none available 1609096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 1.97% # attempts to use FU when none available 1619096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.97% # attempts to use FU when none available 1629096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 1.97% # attempts to use FU when none available 1639096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.97% # attempts to use FU when none available 1649096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.97% # attempts to use FU when none available 1659096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.97% # attempts to use FU when none available 1669096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.97% # attempts to use FU when none available 1679096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.97% # attempts to use FU when none available 1689096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.97% # attempts to use FU when none available 1699096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.97% # attempts to use FU when none available 1709096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.97% # attempts to use FU when none available 1719096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.97% # attempts to use FU when none available 1729096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.97% # attempts to use FU when none available 1739096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.97% # attempts to use FU when none available 1749096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 97 63.82% 65.79% # attempts to use FU when none available 1759079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::MemWrite 52 34.21% 100.00% # attempts to use FU when none available 1768428SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1778428SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1788241SN/Asystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 1799150SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntAlu 4734 59.12% 59.12% # Type of FU issued 1809150SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntMult 5 0.06% 59.18% # Type of FU issued 1819150SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.20% # Type of FU issued 1829150SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.23% # Type of FU issued 1839150SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.23% # Type of FU issued 1849150SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.23% # Type of FU issued 1859150SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.23% # Type of FU issued 1869150SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.23% # Type of FU issued 1879150SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.23% # Type of FU issued 1889150SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.23% # Type of FU issued 1899150SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.23% # Type of FU issued 1909150SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.23% # Type of FU issued 1919150SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.23% # Type of FU issued 1929150SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.23% # Type of FU issued 1939150SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.23% # Type of FU issued 1949150SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.23% # Type of FU issued 1959150SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.23% # Type of FU issued 1969150SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.23% # Type of FU issued 1979150SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.23% # Type of FU issued 1989150SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.23% # Type of FU issued 1999150SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.23% # Type of FU issued 2009150SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.23% # Type of FU issued 2019150SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.23% # Type of FU issued 2029150SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.23% # Type of FU issued 2039150SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.23% # Type of FU issued 2049150SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.23% # Type of FU issued 2059150SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.23% # Type of FU issued 2069150SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.23% # Type of FU issued 2079150SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.23% # Type of FU issued 2089150SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::MemRead 2177 27.19% 86.41% # Type of FU issued 2099150SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::MemWrite 1088 13.59% 100.00% # Type of FU issued 2108241SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2118241SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 2129150SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::total 8008 # Type of FU issued 2139150SAli.Saidi@ARM.comsystem.cpu.iq.rate 0.309763 # Inst issue rate 2148844SAli.Saidi@ARM.comsystem.cpu.iq.fu_busy_cnt 152 # FU busy when requested 2159150SAli.Saidi@ARM.comsystem.cpu.iq.fu_busy_rate 0.018981 # FU busy rate (busy events/executed inst) 2169150SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_reads 29921 # Number of integer instruction queue reads 2179150SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_writes 12064 # Number of integer instruction queue writes 2189150SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 7226 # Number of integer instruction queue wakeup accesses 2198428SN/Asystem.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads 2208428SN/Asystem.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 2218428SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses 2229150SAli.Saidi@ARM.comsystem.cpu.iq.int_alu_accesses 8158 # Number of integer alu accesses 2238428SN/Asystem.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses 2249096Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores 2258428SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2269150SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.squashedLoads 1209 # Number of loads squashed 2279096Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed 2289150SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations 2299150SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.squashedStores 247 # Number of stores squashed 2308428SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2318428SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2328428SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 2338428SN/Asystem.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 2348428SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2359150SAli.Saidi@ARM.comsystem.cpu.iew.iewSquashCycles 793 # Number of cycles IEW is squashing 2369150SAli.Saidi@ARM.comsystem.cpu.iew.iewBlockCycles 141 # Number of cycles IEW is blocking 2379096Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking 2389150SAli.Saidi@ARM.comsystem.cpu.iew.iewDispatchedInsts 10240 # Number of instructions dispatched to IQ 2399150SAli.Saidi@ARM.comsystem.cpu.iew.iewDispSquashedInsts 94 # Number of squashed instructions skipped by dispatch 2409150SAli.Saidi@ARM.comsystem.cpu.iew.iewDispLoadInsts 2372 # Number of dispatched load instructions 2419150SAli.Saidi@ARM.comsystem.cpu.iew.iewDispStoreInsts 1172 # Number of dispatched store instructions 2429096Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions 2438844SAli.Saidi@ARM.comsystem.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall 2449079SAli.Saidi@ARM.comsystem.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall 2459150SAli.Saidi@ARM.comsystem.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations 2469150SAli.Saidi@ARM.comsystem.cpu.iew.predictedTakenIncorrect 103 # Number of branches that were predicted taken incorrectly 2479150SAli.Saidi@ARM.comsystem.cpu.iew.predictedNotTakenIncorrect 360 # Number of branches that were predicted not taken incorrectly 2489150SAli.Saidi@ARM.comsystem.cpu.iew.branchMispredicts 463 # Number of branch mispredicts detected at execute 2499150SAli.Saidi@ARM.comsystem.cpu.iew.iewExecutedInsts 7665 # Number of executed instructions 2509150SAli.Saidi@ARM.comsystem.cpu.iew.iewExecLoadInsts 2061 # Number of load instructions executed 2519150SAli.Saidi@ARM.comsystem.cpu.iew.iewExecSquashedInsts 343 # Number of squashed instructions skipped in execute 2528428SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 2539150SAli.Saidi@ARM.comsystem.cpu.iew.exec_nop 1409 # number of nop insts executed 2549150SAli.Saidi@ARM.comsystem.cpu.iew.exec_refs 3123 # number of memory reference insts executed 2559150SAli.Saidi@ARM.comsystem.cpu.iew.exec_branches 1292 # Number of branches executed 2569150SAli.Saidi@ARM.comsystem.cpu.iew.exec_stores 1062 # Number of stores executed 2579150SAli.Saidi@ARM.comsystem.cpu.iew.exec_rate 0.296495 # Inst execution rate 2589150SAli.Saidi@ARM.comsystem.cpu.iew.wb_sent 7314 # cumulative count of insts sent to commit 2599150SAli.Saidi@ARM.comsystem.cpu.iew.wb_count 7228 # cumulative count of insts written-back 2609150SAli.Saidi@ARM.comsystem.cpu.iew.wb_producers 2794 # num instructions producing a value 2619150SAli.Saidi@ARM.comsystem.cpu.iew.wb_consumers 3985 # num instructions consuming a value 2628428SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 2639150SAli.Saidi@ARM.comsystem.cpu.iew.wb_rate 0.279592 # insts written-back per cycle 2649150SAli.Saidi@ARM.comsystem.cpu.iew.wb_fanout 0.701129 # average fanout of values written-back 2658428SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 2669150SAli.Saidi@ARM.comsystem.cpu.commit.commitCommittedInsts 5813 # The number of committed instructions 2679150SAli.Saidi@ARM.comsystem.cpu.commit.commitCommittedOps 5813 # The number of committed instructions 2689150SAli.Saidi@ARM.comsystem.cpu.commit.commitSquashedInsts 4420 # The number of squashed insts skipped by commit 2698428SN/Asystem.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards 2709150SAli.Saidi@ARM.comsystem.cpu.commit.branchMispredicts 395 # The number of times a branch was mispredicted 2719150SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::samples 12917 # Number of insts commited each cycle 2729150SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::mean 0.450027 # Number of insts commited each cycle 2739150SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::stdev 1.233846 # Number of insts commited each cycle 2748428SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2759150SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::0 10496 81.26% 81.26% # Number of insts commited each cycle 2769150SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::1 1026 7.94% 89.20% # Number of insts commited each cycle 2779150SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::2 636 4.92% 94.12% # Number of insts commited each cycle 2789150SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::3 301 2.33% 96.45% # Number of insts commited each cycle 2799150SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::4 148 1.15% 97.60% # Number of insts commited each cycle 2809150SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::5 90 0.70% 98.30% # Number of insts commited each cycle 2819150SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::6 76 0.59% 98.89% # Number of insts commited each cycle 2829150SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::7 38 0.29% 99.18% # Number of insts commited each cycle 2839150SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::8 106 0.82% 100.00% # Number of insts commited each cycle 2848428SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2858428SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2868428SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 2879150SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::total 12917 # Number of insts commited each cycle 2889150SAli.Saidi@ARM.comsystem.cpu.commit.committedInsts 5813 # Number of instructions committed 2899150SAli.Saidi@ARM.comsystem.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed 2908428SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 2919150SAli.Saidi@ARM.comsystem.cpu.commit.refs 2088 # Number of memory references committed 2929150SAli.Saidi@ARM.comsystem.cpu.commit.loads 1163 # Number of loads committed 2938428SN/Asystem.cpu.commit.membars 0 # Number of memory barriers committed 2949150SAli.Saidi@ARM.comsystem.cpu.commit.branches 915 # Number of branches committed 2958428SN/Asystem.cpu.commit.fp_insts 2 # Number of committed floating point instructions. 2969150SAli.Saidi@ARM.comsystem.cpu.commit.int_insts 5111 # Number of committed integer instructions. 2978428SN/Asystem.cpu.commit.function_calls 87 # Number of function calls committed. 2989096Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached 2998428SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 3009150SAli.Saidi@ARM.comsystem.cpu.rob.rob_reads 23031 # The number of ROB reads 3019150SAli.Saidi@ARM.comsystem.cpu.rob.rob_writes 21266 # The number of ROB writes 3029150SAli.Saidi@ARM.comsystem.cpu.timesIdled 269 # Number of times that the entire CPU went into an idle state and unscheduled itself 3039150SAli.Saidi@ARM.comsystem.cpu.idleCycles 12142 # Total number of cycles that the CPU has spent unscheduled due to idling 3049150SAli.Saidi@ARM.comsystem.cpu.committedInsts 5156 # Number of Instructions Simulated 3059150SAli.Saidi@ARM.comsystem.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated 3069150SAli.Saidi@ARM.comsystem.cpu.committedInsts_total 5156 # Number of Instructions Simulated 3079150SAli.Saidi@ARM.comsystem.cpu.cpi 5.013964 # CPI: Cycles Per Instruction 3089150SAli.Saidi@ARM.comsystem.cpu.cpi_total 5.013964 # CPI: Total CPI of All Threads 3099150SAli.Saidi@ARM.comsystem.cpu.ipc 0.199443 # IPC: Instructions Per Cycle 3109150SAli.Saidi@ARM.comsystem.cpu.ipc_total 0.199443 # IPC: Total IPC of All Threads 3119150SAli.Saidi@ARM.comsystem.cpu.int_regfile_reads 10440 # number of integer regfile reads 3129150SAli.Saidi@ARM.comsystem.cpu.int_regfile_writes 5074 # number of integer regfile writes 3138428SN/Asystem.cpu.fp_regfile_reads 3 # number of floating regfile reads 3148428SN/Asystem.cpu.fp_regfile_writes 1 # number of floating regfile writes 3159150SAli.Saidi@ARM.comsystem.cpu.misc_regfile_reads 150 # number of misc regfile reads 3169079SAli.Saidi@ARM.comsystem.cpu.icache.replacements 17 # number of replacements 3179150SAli.Saidi@ARM.comsystem.cpu.icache.tagsinuse 161.949608 # Cycle average of tags in use 3189150SAli.Saidi@ARM.comsystem.cpu.icache.total_refs 1474 # Total number of references to valid blocks. 3199150SAli.Saidi@ARM.comsystem.cpu.icache.sampled_refs 342 # Sample count of references to valid blocks. 3209150SAli.Saidi@ARM.comsystem.cpu.icache.avg_refs 4.309942 # Average number of references to valid blocks. 3218428SN/Asystem.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 3229150SAli.Saidi@ARM.comsystem.cpu.icache.occ_blocks::cpu.inst 161.949608 # Average occupied blocks per requestor 3239150SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::cpu.inst 0.079077 # Average percentage of cache occupancy 3249150SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::total 0.079077 # Average percentage of cache occupancy 3259150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1474 # number of ReadReq hits 3269150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::total 1474 # number of ReadReq hits 3279150SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::cpu.inst 1474 # number of demand (read+write) hits 3289150SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::total 1474 # number of demand (read+write) hits 3299150SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::cpu.inst 1474 # number of overall hits 3309150SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::total 1474 # number of overall hits 3319150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::cpu.inst 434 # number of ReadReq misses 3329150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::total 434 # number of ReadReq misses 3339150SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::cpu.inst 434 # number of demand (read+write) misses 3349150SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::total 434 # number of demand (read+write) misses 3359150SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::cpu.inst 434 # number of overall misses 3369150SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::total 434 # number of overall misses 3379150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 15909000 # number of ReadReq miss cycles 3389150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_latency::total 15909000 # number of ReadReq miss cycles 3399150SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_latency::cpu.inst 15909000 # number of demand (read+write) miss cycles 3409150SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_latency::total 15909000 # number of demand (read+write) miss cycles 3419150SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_latency::cpu.inst 15909000 # number of overall miss cycles 3429150SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_latency::total 15909000 # number of overall miss cycles 3439150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 1908 # number of ReadReq accesses(hits+misses) 3449150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::total 1908 # number of ReadReq accesses(hits+misses) 3459150SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::cpu.inst 1908 # number of demand (read+write) accesses 3469150SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::total 1908 # number of demand (read+write) accesses 3479150SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::cpu.inst 1908 # number of overall (read+write) accesses 3489150SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::total 1908 # number of overall (read+write) accesses 3499150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.227463 # miss rate for ReadReq accesses 3509150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::total 0.227463 # miss rate for ReadReq accesses 3519150SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.227463 # miss rate for demand accesses 3529150SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::total 0.227463 # miss rate for demand accesses 3539150SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.227463 # miss rate for overall accesses 3549150SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::total 0.227463 # miss rate for overall accesses 3559150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36656.682028 # average ReadReq miss latency 3569150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 36656.682028 # average ReadReq miss latency 3579150SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 36656.682028 # average overall miss latency 3589150SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_miss_latency::total 36656.682028 # average overall miss latency 3599150SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 36656.682028 # average overall miss latency 3609150SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_miss_latency::total 36656.682028 # average overall miss latency 3618428SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3628428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3638428SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 3648428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 3658983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3668983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3678428SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 3688428SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 3699150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 92 # number of ReadReq MSHR hits 3709150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits 3719150SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 92 # number of demand (read+write) MSHR hits 3729150SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_hits::total 92 # number of demand (read+write) MSHR hits 3739150SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 92 # number of overall MSHR hits 3749150SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_hits::total 92 # number of overall MSHR hits 3759150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 342 # number of ReadReq MSHR misses 3769150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::total 342 # number of ReadReq MSHR misses 3779150SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 342 # number of demand (read+write) MSHR misses 3789150SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::total 342 # number of demand (read+write) MSHR misses 3799150SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 342 # number of overall MSHR misses 3809150SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::total 342 # number of overall MSHR misses 3819150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12417500 # number of ReadReq MSHR miss cycles 3829150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 12417500 # number of ReadReq MSHR miss cycles 3839150SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 12417500 # number of demand (read+write) MSHR miss cycles 3849150SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::total 12417500 # number of demand (read+write) MSHR miss cycles 3859150SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 12417500 # number of overall MSHR miss cycles 3869150SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::total 12417500 # number of overall MSHR miss cycles 3879150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.179245 # mshr miss rate for ReadReq accesses 3889150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.179245 # mshr miss rate for ReadReq accesses 3899150SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.179245 # mshr miss rate for demand accesses 3909150SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.179245 # mshr miss rate for demand accesses 3919150SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.179245 # mshr miss rate for overall accesses 3929150SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.179245 # mshr miss rate for overall accesses 3939150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36308.479532 # average ReadReq mshr miss latency 3949150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36308.479532 # average ReadReq mshr miss latency 3959150SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36308.479532 # average overall mshr miss latency 3969150SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 36308.479532 # average overall mshr miss latency 3979150SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36308.479532 # average overall mshr miss latency 3989150SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 36308.479532 # average overall mshr miss latency 3998428SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 4008428SN/Asystem.cpu.dcache.replacements 0 # number of replacements 4019150SAli.Saidi@ARM.comsystem.cpu.dcache.tagsinuse 90.879080 # Cycle average of tags in use 4029150SAli.Saidi@ARM.comsystem.cpu.dcache.total_refs 2407 # Total number of references to valid blocks. 4039096Sandreas.hansson@arm.comsystem.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. 4049150SAli.Saidi@ARM.comsystem.cpu.dcache.avg_refs 17.070922 # Average number of references to valid blocks. 4058428SN/Asystem.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 4069150SAli.Saidi@ARM.comsystem.cpu.dcache.occ_blocks::cpu.data 90.879080 # Average occupied blocks per requestor 4079150SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::cpu.data 0.022187 # Average percentage of cache occupancy 4089150SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::total 0.022187 # Average percentage of cache occupancy 4099150SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1830 # number of ReadReq hits 4109150SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_hits::total 1830 # number of ReadReq hits 4119150SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::cpu.data 577 # number of WriteReq hits 4129150SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::total 577 # number of WriteReq hits 4139150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_hits::cpu.data 2407 # number of demand (read+write) hits 4149150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_hits::total 2407 # number of demand (read+write) hits 4159150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_hits::cpu.data 2407 # number of overall hits 4169150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_hits::total 2407 # number of overall hits 4179096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 148 # number of ReadReq misses 4189096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 148 # number of ReadReq misses 4199150SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::cpu.data 348 # number of WriteReq misses 4209150SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::total 348 # number of WriteReq misses 4219150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::cpu.data 496 # number of demand (read+write) misses 4229150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::total 496 # number of demand (read+write) misses 4239150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::cpu.data 496 # number of overall misses 4249150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::total 496 # number of overall misses 4259150SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 5699000 # number of ReadReq miss cycles 4269150SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_latency::total 5699000 # number of ReadReq miss cycles 4279150SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 13075000 # number of WriteReq miss cycles 4289150SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_latency::total 13075000 # number of WriteReq miss cycles 4299150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_latency::cpu.data 18774000 # number of demand (read+write) miss cycles 4309150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_latency::total 18774000 # number of demand (read+write) miss cycles 4319150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_latency::cpu.data 18774000 # number of overall miss cycles 4329150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_latency::total 18774000 # number of overall miss cycles 4339150SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1978 # number of ReadReq accesses(hits+misses) 4349150SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_accesses::total 1978 # number of ReadReq accesses(hits+misses) 4358835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 4368835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 4379150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_accesses::cpu.data 2903 # number of demand (read+write) accesses 4389150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_accesses::total 2903 # number of demand (read+write) accesses 4399150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_accesses::cpu.data 2903 # number of overall (read+write) accesses 4409150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_accesses::total 2903 # number of overall (read+write) accesses 4419150SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074823 # miss rate for ReadReq accesses 4429150SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.074823 # miss rate for ReadReq accesses 4439150SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.376216 # miss rate for WriteReq accesses 4449150SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.376216 # miss rate for WriteReq accesses 4459150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.170858 # miss rate for demand accesses 4469150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::total 0.170858 # miss rate for demand accesses 4479150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.170858 # miss rate for overall accesses 4489150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_rate::total 0.170858 # miss rate for overall accesses 4499150SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38506.756757 # average ReadReq miss latency 4509150SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 38506.756757 # average ReadReq miss latency 4519150SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37571.839080 # average WriteReq miss latency 4529150SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 37571.839080 # average WriteReq miss latency 4539150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 37850.806452 # average overall miss latency 4549150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_miss_latency::total 37850.806452 # average overall miss latency 4559150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 37850.806452 # average overall miss latency 4569150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_miss_latency::total 37850.806452 # average overall miss latency 4578428SN/Asystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4588428SN/Asystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4598428SN/Asystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 4608428SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 4618983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 4628983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 4638428SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 4648428SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 4659096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits 4669096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits 4679150SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 297 # number of WriteReq MSHR hits 4689150SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_hits::total 297 # number of WriteReq MSHR hits 4699150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 355 # number of demand (read+write) MSHR hits 4709150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_hits::total 355 # number of demand (read+write) MSHR hits 4719150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 355 # number of overall MSHR hits 4729150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_hits::total 355 # number of overall MSHR hits 4739096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses 4749096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses 4758835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses 4768835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses 4779096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 4789096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses 4799096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 4809096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses 4819150SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3832000 # number of ReadReq MSHR miss cycles 4829150SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 3832000 # number of ReadReq MSHR miss cycles 4839096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2081000 # number of WriteReq MSHR miss cycles 4849096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 2081000 # number of WriteReq MSHR miss cycles 4859150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 5913000 # number of demand (read+write) MSHR miss cycles 4869150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_latency::total 5913000 # number of demand (read+write) MSHR miss cycles 4879150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 5913000 # number of overall MSHR miss cycles 4889150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_latency::total 5913000 # number of overall MSHR miss cycles 4899150SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045501 # mshr miss rate for ReadReq accesses 4909150SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045501 # mshr miss rate for ReadReq accesses 4918835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses 4929055Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses 4939150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048570 # mshr miss rate for demand accesses 4949150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.048570 # mshr miss rate for demand accesses 4959150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048570 # mshr miss rate for overall accesses 4969150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.048570 # mshr miss rate for overall accesses 4979150SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 42577.777778 # average ReadReq mshr miss latency 4989150SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 42577.777778 # average ReadReq mshr miss latency 4999096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40803.921569 # average WriteReq mshr miss latency 5009096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40803.921569 # average WriteReq mshr miss latency 5019150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 41936.170213 # average overall mshr miss latency 5029150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 41936.170213 # average overall mshr miss latency 5039150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 41936.170213 # average overall mshr miss latency 5049150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 41936.170213 # average overall mshr miss latency 5058428SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 5068428SN/Asystem.cpu.l2cache.replacements 0 # number of replacements 5079150SAli.Saidi@ARM.comsystem.cpu.l2cache.tagsinuse 221.306774 # Cycle average of tags in use 5088428SN/Asystem.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. 5099150SAli.Saidi@ARM.comsystem.cpu.l2cache.sampled_refs 429 # Sample count of references to valid blocks. 5109150SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_refs 0.006993 # Average number of references to valid blocks. 5118428SN/Asystem.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 5129150SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_blocks::cpu.inst 164.083724 # Average occupied blocks per requestor 5139150SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_blocks::cpu.data 57.223050 # Average occupied blocks per requestor 5149150SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::cpu.inst 0.005007 # Average percentage of cache occupancy 5159150SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::cpu.data 0.001746 # Average percentage of cache occupancy 5169150SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::total 0.006754 # Average percentage of cache occupancy 5178835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits 5188835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits 5198835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 5208835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 5218835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 5228835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 3 # number of overall hits 5239150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 339 # number of ReadReq misses 5249096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 90 # number of ReadReq misses 5259150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::total 429 # number of ReadReq misses 5268835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses 5278835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses 5289150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.inst 339 # number of demand (read+write) misses 5299096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 141 # number of demand (read+write) misses 5309150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::total 480 # number of demand (read+write) misses 5319150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.inst 339 # number of overall misses 5329096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses 5339150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::total 480 # number of overall misses 5349150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12053000 # number of ReadReq miss cycles 5359150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 3723500 # number of ReadReq miss cycles 5369150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::total 15776500 # number of ReadReq miss cycles 5379096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1998000 # number of ReadExReq miss cycles 5389096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 1998000 # number of ReadExReq miss cycles 5399150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 12053000 # number of demand (read+write) miss cycles 5409150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 5721500 # number of demand (read+write) miss cycles 5419150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::total 17774500 # number of demand (read+write) miss cycles 5429150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 12053000 # number of overall miss cycles 5439150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 5721500 # number of overall miss cycles 5449150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::total 17774500 # number of overall miss cycles 5459150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 342 # number of ReadReq accesses(hits+misses) 5469096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 90 # number of ReadReq accesses(hits+misses) 5479150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::total 432 # number of ReadReq accesses(hits+misses) 5488835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) 5498835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) 5509150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.inst 342 # number of demand (read+write) accesses 5519096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses 5529150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::total 483 # number of demand (read+write) accesses 5539150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.inst 342 # number of overall (read+write) accesses 5549096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses 5559150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::total 483 # number of overall (read+write) accesses 5569150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991228 # miss rate for ReadReq accesses 5578835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 5589150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.993056 # miss rate for ReadReq accesses 5598835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 5609055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 5619150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.991228 # miss rate for demand accesses 5628835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 5639150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::total 0.993789 # miss rate for demand accesses 5649150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.991228 # miss rate for overall accesses 5658835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 5669150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::total 0.993789 # miss rate for overall accesses 5679150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35554.572271 # average ReadReq miss latency 5689150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 41372.222222 # average ReadReq miss latency 5699150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 36775.058275 # average ReadReq miss latency 5709096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39176.470588 # average ReadExReq miss latency 5719096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 39176.470588 # average ReadExReq miss latency 5729150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35554.572271 # average overall miss latency 5739150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 40578.014184 # average overall miss latency 5749150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::total 37030.208333 # average overall miss latency 5759150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35554.572271 # average overall miss latency 5769150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 40578.014184 # average overall miss latency 5779150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::total 37030.208333 # average overall miss latency 5788428SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5798428SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5808428SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 5818428SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 5828983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5838983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5848428SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 5858428SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 5869150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 339 # number of ReadReq MSHR misses 5879096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses 5889150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 429 # number of ReadReq MSHR misses 5898835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses 5908835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses 5919150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 339 # number of demand (read+write) MSHR misses 5929096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 5939150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::total 480 # number of demand (read+write) MSHR misses 5949150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 339 # number of overall MSHR misses 5959096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 5969150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::total 480 # number of overall MSHR misses 5979150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10969500 # number of ReadReq MSHR miss cycles 5989150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3448000 # number of ReadReq MSHR miss cycles 5999150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 14417500 # number of ReadReq MSHR miss cycles 6009096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1839500 # number of ReadExReq MSHR miss cycles 6019096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1839500 # number of ReadExReq MSHR miss cycles 6029150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10969500 # number of demand (read+write) MSHR miss cycles 6039150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5287500 # number of demand (read+write) MSHR miss cycles 6049150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 16257000 # number of demand (read+write) MSHR miss cycles 6059150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10969500 # number of overall MSHR miss cycles 6069150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5287500 # number of overall MSHR miss cycles 6079150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 16257000 # number of overall MSHR miss cycles 6089150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for ReadReq accesses 6098835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 6109150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993056 # mshr miss rate for ReadReq accesses 6118835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 6129055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 6139150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for demand accesses 6148835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 6159150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.993789 # mshr miss rate for demand accesses 6169150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for overall accesses 6178835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 6189150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.993789 # mshr miss rate for overall accesses 6199150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32358.407080 # average ReadReq mshr miss latency 6209150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38311.111111 # average ReadReq mshr miss latency 6219150SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33607.226107 # average ReadReq mshr miss latency 6229096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36068.627451 # average ReadExReq mshr miss latency 6239096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36068.627451 # average ReadExReq mshr miss latency 6249150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32358.407080 # average overall mshr miss latency 6259150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37500 # average overall mshr miss latency 6269150SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 33868.750000 # average overall mshr miss latency 6279150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32358.407080 # average overall mshr miss latency 6289150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37500 # average overall mshr miss latency 6299150SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 33868.750000 # average overall mshr miss latency 6308428SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 6316039SN/A 6326039SN/A---------- End Simulation Statistics ---------- 633