stats.txt revision 9096
16039SN/A 26039SN/A---------- Begin Simulation Statistics ---------- 39096Sandreas.hansson@arm.comsim_seconds 0.000013 # Number of seconds simulated 49096Sandreas.hansson@arm.comsim_ticks 13016500 # Number of ticks simulated 59096Sandreas.hansson@arm.comfinal_tick 13016500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79096Sandreas.hansson@arm.comhost_inst_rate 54505 # Simulator instruction rate (inst/s) 89096Sandreas.hansson@arm.comhost_op_rate 54495 # Simulator op (including micro ops) rate (op/s) 99096Sandreas.hansson@arm.comhost_tick_rate 137205108 # Simulator tick rate (ticks/s) 109096Sandreas.hansson@arm.comhost_mem_usage 220060 # Number of bytes of host memory used 119096Sandreas.hansson@arm.comhost_seconds 0.10 # Real time elapsed on the host 128428SN/Asim_insts 5169 # Number of instructions simulated 138835SAli.Saidi@ARM.comsim_ops 5169 # Number of ops (including micro ops) simulated 149096Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 21760 # Number of bytes read from this memory 159096Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory 169079SAli.Saidi@ARM.comsystem.physmem.bytes_read::total 30784 # Number of bytes read from this memory 179096Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 21760 # Number of instructions bytes read from this memory 189096Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 21760 # Number of instructions bytes read from this memory 199096Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 340 # Number of read requests responded to by this memory 209096Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory 219079SAli.Saidi@ARM.comsystem.physmem.num_reads::total 481 # Number of read requests responded to by this memory 229096Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 1671724350 # Total read bandwidth from this memory (bytes/s) 239096Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 693273922 # Total read bandwidth from this memory (bytes/s) 249096Sandreas.hansson@arm.comsystem.physmem.bw_read::total 2364998271 # Total read bandwidth from this memory (bytes/s) 259096Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 1671724350 # Instruction read bandwidth from this memory (bytes/s) 269096Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 1671724350 # Instruction read bandwidth from this memory (bytes/s) 279096Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 1671724350 # Total bandwidth to/from this memory (bytes/s) 289096Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 693273922 # Total bandwidth to/from this memory (bytes/s) 299096Sandreas.hansson@arm.comsystem.physmem.bw_total::total 2364998271 # Total bandwidth to/from this memory (bytes/s) 308428SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 318428SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 328428SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 338428SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 348428SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 358428SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 366039SN/Asystem.cpu.dtb.hits 0 # DTB hits 376039SN/Asystem.cpu.dtb.misses 0 # DTB misses 388428SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 398428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 408428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 418428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 428428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 438428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 448428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 458428SN/Asystem.cpu.itb.hits 0 # DTB hits 468428SN/Asystem.cpu.itb.misses 0 # DTB misses 478428SN/Asystem.cpu.itb.accesses 0 # DTB accesses 488428SN/Asystem.cpu.workload.num_syscalls 8 # Number of system calls 499096Sandreas.hansson@arm.comsystem.cpu.numCycles 26034 # number of cpu cycles simulated 508428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 518428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 529096Sandreas.hansson@arm.comsystem.cpu.BPredUnit.lookups 2148 # Number of BP lookups 539096Sandreas.hansson@arm.comsystem.cpu.BPredUnit.condPredicted 1448 # Number of conditional branches predicted 549096Sandreas.hansson@arm.comsystem.cpu.BPredUnit.condIncorrect 450 # Number of conditional branches incorrect 559096Sandreas.hansson@arm.comsystem.cpu.BPredUnit.BTBLookups 1662 # Number of BTB lookups 569096Sandreas.hansson@arm.comsystem.cpu.BPredUnit.BTBHits 462 # Number of BTB hits 578428SN/Asystem.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 589096Sandreas.hansson@arm.comsystem.cpu.BPredUnit.usedRAS 263 # Number of times the RAS was used to get a target. 599096Sandreas.hansson@arm.comsystem.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. 609096Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 8866 # Number of cycles fetch is stalled on an Icache miss 619096Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 13061 # Number of instructions fetch has processed 629096Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 2148 # Number of branches that fetch encountered 639096Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 725 # Number of branches that fetch has predicted taken 649096Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 3176 # Number of cycles fetch has run and was not squashing or blocked 659096Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 1340 # Number of cycles fetch has spent squashing 669096Sandreas.hansson@arm.comsystem.cpu.fetch.BlockedCycles 826 # Number of cycles fetch has spent blocked 678464SN/Asystem.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 689079SAli.Saidi@ARM.comsystem.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps 699096Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 1948 # Number of cache lines fetched 709096Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 270 # Number of outstanding Icache misses that were squashed 719096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 13893 # Number of instructions fetched each cycle (Total) 729096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 0.940114 # Number of instructions fetched each cycle (Total) 739096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 2.257377 # Number of instructions fetched each cycle (Total) 746291SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 759096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 10717 77.14% 77.14% # Number of instructions fetched each cycle (Total) 769096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 1298 9.34% 86.48% # Number of instructions fetched each cycle (Total) 779096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 110 0.79% 87.27% # Number of instructions fetched each cycle (Total) 789096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 134 0.96% 88.24% # Number of instructions fetched each cycle (Total) 799096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 300 2.16% 90.40% # Number of instructions fetched each cycle (Total) 809096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 103 0.74% 91.14% # Number of instructions fetched each cycle (Total) 819096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 148 1.07% 92.20% # Number of instructions fetched each cycle (Total) 829096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 126 0.91% 93.11% # Number of instructions fetched each cycle (Total) 839096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 957 6.89% 100.00% # Number of instructions fetched each cycle (Total) 846291SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 856291SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 866291SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 879096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 13893 # Number of instructions fetched each cycle (Total) 889096Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.082507 # Number of branch fetches per cycle 899096Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.501690 # Number of inst fetches per cycle 909096Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 9037 # Number of cycles decode is idle 919096Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 974 # Number of cycles decode is blocked 929096Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 2996 # Number of cycles decode is running 939096Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 51 # Number of cycles decode is unblocking 949096Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 835 # Number of cycles decode is squashing 959096Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 145 # Number of times decode resolved a branch 969096Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 47 # Number of times decode detected a branch misprediction 979096Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 12168 # Number of instructions handled by decode 989079SAli.Saidi@ARM.comsystem.cpu.decode.SquashedInsts 188 # Number of squashed instructions handled by decode 999096Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 835 # Number of cycles rename is squashing 1009096Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 9227 # Number of cycles rename is idle 1019096Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 288 # Number of cycles rename is blocking 1029096Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 540 # count of cycles rename stalled for serializing inst 1039096Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 2860 # Number of cycles rename is running 1049096Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 143 # Number of cycles rename is unblocking 1059096Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 11638 # Number of instructions processed by rename 1069096Sandreas.hansson@arm.comsystem.cpu.rename.LSQFullEvents 129 # Number of times rename has blocked due to LSQ full 1079096Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 7046 # Number of destination operands rename has renamed 1089096Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 13805 # Number of register rename lookups that rename has made 1099096Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 13801 # Number of integer rename lookups 1108554SN/Asystem.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups 1118428SN/Asystem.cpu.rename.CommittedMaps 3410 # Number of HB maps that are committed 1129096Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 3636 # Number of HB maps that are undone due to squashing 1139096Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 16 # count of serializing insts renamed 1149096Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed 1159096Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 308 # count of insts added to the skid buffer 1169096Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 2447 # Number of loads inserted to the mem dependence unit. 1179079SAli.Saidi@ARM.comsystem.cpu.memDep0.insertedStores 1180 # Number of stores inserted to the mem dependence unit. 1188428SN/Asystem.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 1198428SN/Asystem.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. 1209096Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 9050 # Number of instructions added to the IQ (excludes non-spec) 1219096Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ 1229096Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 8137 # Number of instructions issued 1239096Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 46 # Number of squashed instructions issued 1249096Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 3435 # Number of squashed instructions iterated over during squash; mainly for profiling 1259096Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 1984 # Number of squashed operands that are examined and possibly removed from graph 1269096Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed 1279096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 13893 # Number of insts issued each cycle 1289096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.585691 # Number of insts issued each cycle 1299096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.249798 # Number of insts issued each cycle 1308428SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1319096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 10352 74.51% 74.51% # Number of insts issued each cycle 1329096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 1446 10.41% 84.92% # Number of insts issued each cycle 1339096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 850 6.12% 91.04% # Number of insts issued each cycle 1349096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 537 3.87% 94.90% # Number of insts issued each cycle 1359096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 350 2.52% 97.42% # Number of insts issued each cycle 1369096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 226 1.63% 99.05% # Number of insts issued each cycle 1379096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 89 0.64% 99.69% # Number of insts issued each cycle 1389096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 28 0.20% 99.89% # Number of insts issued each cycle 1399096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 15 0.11% 100.00% # Number of insts issued each cycle 1408428SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1418428SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1428428SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1439096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 13893 # Number of insts issued each cycle 1448428SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1459096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 3 1.97% 1.97% # attempts to use FU when none available 1469096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 1.97% # attempts to use FU when none available 1479096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 1.97% # attempts to use FU when none available 1489096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 1.97% # attempts to use FU when none available 1499096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 1.97% # attempts to use FU when none available 1509096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 1.97% # attempts to use FU when none available 1519096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 1.97% # attempts to use FU when none available 1529096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 1.97% # attempts to use FU when none available 1539096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.97% # attempts to use FU when none available 1549096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 1.97% # attempts to use FU when none available 1559096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.97% # attempts to use FU when none available 1569096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 1.97% # attempts to use FU when none available 1579096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 1.97% # attempts to use FU when none available 1589096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 1.97% # attempts to use FU when none available 1599096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 1.97% # attempts to use FU when none available 1609096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 1.97% # attempts to use FU when none available 1619096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.97% # attempts to use FU when none available 1629096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 1.97% # attempts to use FU when none available 1639096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.97% # attempts to use FU when none available 1649096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.97% # attempts to use FU when none available 1659096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.97% # attempts to use FU when none available 1669096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.97% # attempts to use FU when none available 1679096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.97% # attempts to use FU when none available 1689096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.97% # attempts to use FU when none available 1699096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.97% # attempts to use FU when none available 1709096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.97% # attempts to use FU when none available 1719096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.97% # attempts to use FU when none available 1729096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.97% # attempts to use FU when none available 1739096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.97% # attempts to use FU when none available 1749096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 97 63.82% 65.79% # attempts to use FU when none available 1759079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::MemWrite 52 34.21% 100.00% # attempts to use FU when none available 1768428SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1778428SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1788241SN/Asystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 1799096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 4825 59.30% 59.30% # Type of FU issued 1809096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 5 0.06% 59.36% # Type of FU issued 1819096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.38% # Type of FU issued 1829096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.41% # Type of FU issued 1839096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.41% # Type of FU issued 1849096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.41% # Type of FU issued 1859096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.41% # Type of FU issued 1869096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.41% # Type of FU issued 1879096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.41% # Type of FU issued 1889096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.41% # Type of FU issued 1899096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.41% # Type of FU issued 1909096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.41% # Type of FU issued 1919096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.41% # Type of FU issued 1929096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.41% # Type of FU issued 1939096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.41% # Type of FU issued 1949096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.41% # Type of FU issued 1959096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.41% # Type of FU issued 1969096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.41% # Type of FU issued 1979096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.41% # Type of FU issued 1989096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.41% # Type of FU issued 1999096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.41% # Type of FU issued 2009096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.41% # Type of FU issued 2019096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.41% # Type of FU issued 2029096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.41% # Type of FU issued 2039096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.41% # Type of FU issued 2049096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.41% # Type of FU issued 2059096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.41% # Type of FU issued 2069096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.41% # Type of FU issued 2079096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.41% # Type of FU issued 2089096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 2212 27.18% 86.59% # Type of FU issued 2099096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 1091 13.41% 100.00% # Type of FU issued 2108241SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2118241SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 2129096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 8137 # Type of FU issued 2139096Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.312553 # Inst issue rate 2148844SAli.Saidi@ARM.comsystem.cpu.iq.fu_busy_cnt 152 # FU busy when requested 2159096Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.018680 # FU busy rate (busy events/executed inst) 2169096Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 30361 # Number of integer instruction queue reads 2179096Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 12504 # Number of integer instruction queue writes 2189096Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 7339 # Number of integer instruction queue wakeup accesses 2198428SN/Asystem.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads 2208428SN/Asystem.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 2218428SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses 2229096Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 8287 # Number of integer alu accesses 2238428SN/Asystem.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses 2249096Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores 2258428SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2269096Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1283 # Number of loads squashed 2279096Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed 2289096Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 9 # Number of memory ordering violations 2299079SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.squashedStores 255 # Number of stores squashed 2308428SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2318428SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2328428SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 2338428SN/Asystem.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 2348428SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2359096Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 835 # Number of cycles IEW is squashing 2369096Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 148 # Number of cycles IEW is blocking 2379096Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking 2389096Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 10551 # Number of instructions dispatched to IQ 2399096Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 78 # Number of squashed instructions skipped by dispatch 2409096Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 2447 # Number of dispatched load instructions 2419079SAli.Saidi@ARM.comsystem.cpu.iew.iewDispStoreInsts 1180 # Number of dispatched store instructions 2429096Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions 2438844SAli.Saidi@ARM.comsystem.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall 2449079SAli.Saidi@ARM.comsystem.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall 2459096Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 9 # Number of memory order violations 2469096Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly 2479096Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 378 # Number of branches that were predicted not taken incorrectly 2489096Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 479 # Number of branch mispredicts detected at execute 2499096Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 7784 # Number of executed instructions 2509096Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 2096 # Number of load instructions executed 2519096Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 353 # Number of squashed instructions skipped in execute 2528428SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 2539096Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 1489 # number of nop insts executed 2549096Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 3163 # number of memory reference insts executed 2559096Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 1325 # Number of branches executed 2569096Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 1067 # Number of stores executed 2579096Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.298994 # Inst execution rate 2589096Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 7431 # cumulative count of insts sent to commit 2599096Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 7341 # cumulative count of insts written-back 2609096Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 2840 # num instructions producing a value 2619096Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 4066 # num instructions consuming a value 2628428SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 2639096Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.281977 # insts written-back per cycle 2649096Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.698475 # average fanout of values written-back 2658428SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 2668428SN/Asystem.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions 2678835SAli.Saidi@ARM.comsystem.cpu.commit.commitCommittedOps 5826 # The number of committed instructions 2689096Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 4721 # The number of squashed insts skipped by commit 2698428SN/Asystem.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards 2709096Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 404 # The number of times a branch was mispredicted 2719096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 13058 # Number of insts commited each cycle 2729096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.446163 # Number of insts commited each cycle 2739096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.225344 # Number of insts commited each cycle 2748428SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2759096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 10619 81.32% 81.32% # Number of insts commited each cycle 2769096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 1036 7.93% 89.26% # Number of insts commited each cycle 2779096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 643 4.92% 94.18% # Number of insts commited each cycle 2789096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 305 2.34% 96.52% # Number of insts commited each cycle 2799096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 154 1.18% 97.69% # Number of insts commited each cycle 2809096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 84 0.64% 98.34% # Number of insts commited each cycle 2819096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 72 0.55% 98.89% # Number of insts commited each cycle 2829096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 39 0.30% 99.19% # Number of insts commited each cycle 2839096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 106 0.81% 100.00% # Number of insts commited each cycle 2848428SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2858428SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2868428SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 2879096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 13058 # Number of insts commited each cycle 2888835SAli.Saidi@ARM.comsystem.cpu.commit.committedInsts 5826 # Number of instructions committed 2898835SAli.Saidi@ARM.comsystem.cpu.commit.committedOps 5826 # Number of ops (including micro ops) committed 2908428SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 2918428SN/Asystem.cpu.commit.refs 2089 # Number of memory references committed 2928428SN/Asystem.cpu.commit.loads 1164 # Number of loads committed 2938428SN/Asystem.cpu.commit.membars 0 # Number of memory barriers committed 2948428SN/Asystem.cpu.commit.branches 916 # Number of branches committed 2958428SN/Asystem.cpu.commit.fp_insts 2 # Number of committed floating point instructions. 2968428SN/Asystem.cpu.commit.int_insts 5124 # Number of committed integer instructions. 2978428SN/Asystem.cpu.commit.function_calls 87 # Number of function calls committed. 2989096Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached 2998428SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 3009096Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 23486 # The number of ROB reads 3019096Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 21936 # The number of ROB writes 3029096Sandreas.hansson@arm.comsystem.cpu.timesIdled 270 # Number of times that the entire CPU went into an idle state and unscheduled itself 3039096Sandreas.hansson@arm.comsystem.cpu.idleCycles 12141 # Total number of cycles that the CPU has spent unscheduled due to idling 3048428SN/Asystem.cpu.committedInsts 5169 # Number of Instructions Simulated 3058835SAli.Saidi@ARM.comsystem.cpu.committedOps 5169 # Number of Ops (including micro ops) Simulated 3068428SN/Asystem.cpu.committedInsts_total 5169 # Number of Instructions Simulated 3079096Sandreas.hansson@arm.comsystem.cpu.cpi 5.036564 # CPI: Cycles Per Instruction 3089096Sandreas.hansson@arm.comsystem.cpu.cpi_total 5.036564 # CPI: Total CPI of All Threads 3099096Sandreas.hansson@arm.comsystem.cpu.ipc 0.198548 # IPC: Instructions Per Cycle 3109096Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.198548 # IPC: Total IPC of All Threads 3119096Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 10600 # number of integer regfile reads 3129096Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 5152 # number of integer regfile writes 3138428SN/Asystem.cpu.fp_regfile_reads 3 # number of floating regfile reads 3148428SN/Asystem.cpu.fp_regfile_writes 1 # number of floating regfile writes 3159096Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 155 # number of misc regfile reads 3169079SAli.Saidi@ARM.comsystem.cpu.icache.replacements 17 # number of replacements 3179096Sandreas.hansson@arm.comsystem.cpu.icache.tagsinuse 163.172601 # Cycle average of tags in use 3189096Sandreas.hansson@arm.comsystem.cpu.icache.total_refs 1511 # Total number of references to valid blocks. 3199096Sandreas.hansson@arm.comsystem.cpu.icache.sampled_refs 343 # Sample count of references to valid blocks. 3209096Sandreas.hansson@arm.comsystem.cpu.icache.avg_refs 4.405248 # Average number of references to valid blocks. 3218428SN/Asystem.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 3229096Sandreas.hansson@arm.comsystem.cpu.icache.occ_blocks::cpu.inst 163.172601 # Average occupied blocks per requestor 3239096Sandreas.hansson@arm.comsystem.cpu.icache.occ_percent::cpu.inst 0.079674 # Average percentage of cache occupancy 3249096Sandreas.hansson@arm.comsystem.cpu.icache.occ_percent::total 0.079674 # Average percentage of cache occupancy 3259096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1511 # number of ReadReq hits 3269096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 1511 # number of ReadReq hits 3279096Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 1511 # number of demand (read+write) hits 3289096Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 1511 # number of demand (read+write) hits 3299096Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 1511 # number of overall hits 3309096Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 1511 # number of overall hits 3319096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses 3329096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses 3339096Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses 3349096Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses 3359096Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses 3369096Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 437 # number of overall misses 3379096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 15987000 # number of ReadReq miss cycles 3389096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 15987000 # number of ReadReq miss cycles 3399096Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 15987000 # number of demand (read+write) miss cycles 3409096Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 15987000 # number of demand (read+write) miss cycles 3419096Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 15987000 # number of overall miss cycles 3429096Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 15987000 # number of overall miss cycles 3439096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 1948 # number of ReadReq accesses(hits+misses) 3449096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 1948 # number of ReadReq accesses(hits+misses) 3459096Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 1948 # number of demand (read+write) accesses 3469096Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 1948 # number of demand (read+write) accesses 3479096Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 1948 # number of overall (read+write) accesses 3489096Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 1948 # number of overall (read+write) accesses 3499096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.224333 # miss rate for ReadReq accesses 3509096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.224333 # miss rate for ReadReq accesses 3519096Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.224333 # miss rate for demand accesses 3529096Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.224333 # miss rate for demand accesses 3539096Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.224333 # miss rate for overall accesses 3549096Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.224333 # miss rate for overall accesses 3559096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36583.524027 # average ReadReq miss latency 3569096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 36583.524027 # average ReadReq miss latency 3579096Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 36583.524027 # average overall miss latency 3589096Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 36583.524027 # average overall miss latency 3599096Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 36583.524027 # average overall miss latency 3609096Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 36583.524027 # average overall miss latency 3618428SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3628428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3638428SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 3648428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 3658983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3668983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3678428SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 3688428SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 3699079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 94 # number of ReadReq MSHR hits 3709079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_hits::total 94 # number of ReadReq MSHR hits 3719079SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 94 # number of demand (read+write) MSHR hits 3729079SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits 3739079SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 94 # number of overall MSHR hits 3749079SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_hits::total 94 # number of overall MSHR hits 3759096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 343 # number of ReadReq MSHR misses 3769096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 343 # number of ReadReq MSHR misses 3779096Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 343 # number of demand (read+write) MSHR misses 3789096Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 343 # number of demand (read+write) MSHR misses 3799096Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 343 # number of overall MSHR misses 3809096Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 343 # number of overall MSHR misses 3819096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12452000 # number of ReadReq MSHR miss cycles 3829096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 12452000 # number of ReadReq MSHR miss cycles 3839096Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 12452000 # number of demand (read+write) MSHR miss cycles 3849096Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 12452000 # number of demand (read+write) MSHR miss cycles 3859096Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 12452000 # number of overall MSHR miss cycles 3869096Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 12452000 # number of overall MSHR miss cycles 3879096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.176078 # mshr miss rate for ReadReq accesses 3889096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.176078 # mshr miss rate for ReadReq accesses 3899096Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.176078 # mshr miss rate for demand accesses 3909096Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.176078 # mshr miss rate for demand accesses 3919096Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.176078 # mshr miss rate for overall accesses 3929096Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.176078 # mshr miss rate for overall accesses 3939096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36303.206997 # average ReadReq mshr miss latency 3949096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36303.206997 # average ReadReq mshr miss latency 3959096Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36303.206997 # average overall mshr miss latency 3969096Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 36303.206997 # average overall mshr miss latency 3979096Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36303.206997 # average overall mshr miss latency 3989096Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 36303.206997 # average overall mshr miss latency 3998428SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 4008428SN/Asystem.cpu.dcache.replacements 0 # number of replacements 4019096Sandreas.hansson@arm.comsystem.cpu.dcache.tagsinuse 91.140441 # Cycle average of tags in use 4029096Sandreas.hansson@arm.comsystem.cpu.dcache.total_refs 2441 # Total number of references to valid blocks. 4039096Sandreas.hansson@arm.comsystem.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. 4049096Sandreas.hansson@arm.comsystem.cpu.dcache.avg_refs 17.312057 # Average number of references to valid blocks. 4058428SN/Asystem.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 4069096Sandreas.hansson@arm.comsystem.cpu.dcache.occ_blocks::cpu.data 91.140441 # Average occupied blocks per requestor 4079096Sandreas.hansson@arm.comsystem.cpu.dcache.occ_percent::cpu.data 0.022251 # Average percentage of cache occupancy 4089096Sandreas.hansson@arm.comsystem.cpu.dcache.occ_percent::total 0.022251 # Average percentage of cache occupancy 4099096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1863 # number of ReadReq hits 4109096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 1863 # number of ReadReq hits 4119096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 578 # number of WriteReq hits 4129096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 578 # number of WriteReq hits 4139096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 2441 # number of demand (read+write) hits 4149096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 2441 # number of demand (read+write) hits 4159096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 2441 # number of overall hits 4169096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 2441 # number of overall hits 4179096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 148 # number of ReadReq misses 4189096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 148 # number of ReadReq misses 4199096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 347 # number of WriteReq misses 4209096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 347 # number of WriteReq misses 4219096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 495 # number of demand (read+write) misses 4229096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 495 # number of demand (read+write) misses 4239096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 495 # number of overall misses 4249096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 495 # number of overall misses 4259096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 5658500 # number of ReadReq miss cycles 4269096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 5658500 # number of ReadReq miss cycles 4279096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 13040000 # number of WriteReq miss cycles 4289096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 13040000 # number of WriteReq miss cycles 4299096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 18698500 # number of demand (read+write) miss cycles 4309096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 18698500 # number of demand (read+write) miss cycles 4319096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 18698500 # number of overall miss cycles 4329096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 18698500 # number of overall miss cycles 4339096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 2011 # number of ReadReq accesses(hits+misses) 4349096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 2011 # number of ReadReq accesses(hits+misses) 4358835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 4368835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 4379096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 2936 # number of demand (read+write) accesses 4389096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 2936 # number of demand (read+write) accesses 4399096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 2936 # number of overall (read+write) accesses 4409096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 2936 # number of overall (read+write) accesses 4419096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.073595 # miss rate for ReadReq accesses 4429096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.073595 # miss rate for ReadReq accesses 4439096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.375135 # miss rate for WriteReq accesses 4449096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.375135 # miss rate for WriteReq accesses 4459096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.168597 # miss rate for demand accesses 4469096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.168597 # miss rate for demand accesses 4479096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.168597 # miss rate for overall accesses 4489096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.168597 # miss rate for overall accesses 4499096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38233.108108 # average ReadReq miss latency 4509096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 38233.108108 # average ReadReq miss latency 4519096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37579.250720 # average WriteReq miss latency 4529096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 37579.250720 # average WriteReq miss latency 4539096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 37774.747475 # average overall miss latency 4549096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 37774.747475 # average overall miss latency 4559096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 37774.747475 # average overall miss latency 4569096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 37774.747475 # average overall miss latency 4578428SN/Asystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4588428SN/Asystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4598428SN/Asystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 4608428SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 4618983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 4628983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 4638428SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 4648428SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 4659096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits 4669096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits 4679096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 296 # number of WriteReq MSHR hits 4689096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 296 # number of WriteReq MSHR hits 4699096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 354 # number of demand (read+write) MSHR hits 4709096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 354 # number of demand (read+write) MSHR hits 4719096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 354 # number of overall MSHR hits 4729096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 354 # number of overall MSHR hits 4739096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses 4749096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses 4758835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses 4768835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses 4779096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 4789096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses 4799096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 4809096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses 4819096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3847000 # number of ReadReq MSHR miss cycles 4829096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 3847000 # number of ReadReq MSHR miss cycles 4839096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2081000 # number of WriteReq MSHR miss cycles 4849096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 2081000 # number of WriteReq MSHR miss cycles 4859096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 5928000 # number of demand (read+write) MSHR miss cycles 4869096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 5928000 # number of demand (read+write) MSHR miss cycles 4879096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 5928000 # number of overall MSHR miss cycles 4889096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 5928000 # number of overall MSHR miss cycles 4899096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044754 # mshr miss rate for ReadReq accesses 4909096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044754 # mshr miss rate for ReadReq accesses 4918835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses 4929055Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses 4939096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048025 # mshr miss rate for demand accesses 4949096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.048025 # mshr miss rate for demand accesses 4959096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048025 # mshr miss rate for overall accesses 4969096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.048025 # mshr miss rate for overall accesses 4979096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 42744.444444 # average ReadReq mshr miss latency 4989096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 42744.444444 # average ReadReq mshr miss latency 4999096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40803.921569 # average WriteReq mshr miss latency 5009096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40803.921569 # average WriteReq mshr miss latency 5019096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 42042.553191 # average overall mshr miss latency 5029096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 42042.553191 # average overall mshr miss latency 5039096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 42042.553191 # average overall mshr miss latency 5049096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 42042.553191 # average overall mshr miss latency 5058428SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 5068428SN/Asystem.cpu.l2cache.replacements 0 # number of replacements 5079096Sandreas.hansson@arm.comsystem.cpu.l2cache.tagsinuse 222.725864 # Cycle average of tags in use 5088428SN/Asystem.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. 5099079SAli.Saidi@ARM.comsystem.cpu.l2cache.sampled_refs 430 # Sample count of references to valid blocks. 5109079SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_refs 0.006977 # Average number of references to valid blocks. 5118428SN/Asystem.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 5129096Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.inst 165.335127 # Average occupied blocks per requestor 5139096Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.data 57.390737 # Average occupied blocks per requestor 5149096Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.inst 0.005046 # Average percentage of cache occupancy 5159096Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.data 0.001751 # Average percentage of cache occupancy 5169096Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::total 0.006797 # Average percentage of cache occupancy 5178835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits 5188835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits 5198835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 5208835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 5218835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 5228835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 3 # number of overall hits 5239096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 340 # number of ReadReq misses 5249096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 90 # number of ReadReq misses 5259079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::total 430 # number of ReadReq misses 5268835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses 5278835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses 5289096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 340 # number of demand (read+write) misses 5299096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 141 # number of demand (read+write) misses 5309079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::total 481 # number of demand (read+write) misses 5319096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 340 # number of overall misses 5329096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses 5339079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::total 481 # number of overall misses 5349096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12086500 # number of ReadReq miss cycles 5359096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 3738500 # number of ReadReq miss cycles 5369096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 15825000 # number of ReadReq miss cycles 5379096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1998000 # number of ReadExReq miss cycles 5389096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 1998000 # number of ReadExReq miss cycles 5399096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 12086500 # number of demand (read+write) miss cycles 5409096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 5736500 # number of demand (read+write) miss cycles 5419096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 17823000 # number of demand (read+write) miss cycles 5429096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 12086500 # number of overall miss cycles 5439096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 5736500 # number of overall miss cycles 5449096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 17823000 # number of overall miss cycles 5459096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 343 # number of ReadReq accesses(hits+misses) 5469096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 90 # number of ReadReq accesses(hits+misses) 5479079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::total 433 # number of ReadReq accesses(hits+misses) 5488835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) 5498835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) 5509096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 343 # number of demand (read+write) accesses 5519096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses 5529079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::total 484 # number of demand (read+write) accesses 5539096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 343 # number of overall (read+write) accesses 5549096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses 5559079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::total 484 # number of overall (read+write) accesses 5569096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991254 # miss rate for ReadReq accesses 5578835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 5589079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.993072 # miss rate for ReadReq accesses 5598835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 5609055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 5619096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.991254 # miss rate for demand accesses 5628835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 5639079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::total 0.993802 # miss rate for demand accesses 5649096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.991254 # miss rate for overall accesses 5658835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 5669079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::total 0.993802 # miss rate for overall accesses 5679096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35548.529412 # average ReadReq miss latency 5689096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 41538.888889 # average ReadReq miss latency 5699096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 36802.325581 # average ReadReq miss latency 5709096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39176.470588 # average ReadExReq miss latency 5719096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 39176.470588 # average ReadExReq miss latency 5729096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35548.529412 # average overall miss latency 5739096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 40684.397163 # average overall miss latency 5749096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 37054.054054 # average overall miss latency 5759096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35548.529412 # average overall miss latency 5769096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 40684.397163 # average overall miss latency 5779096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 37054.054054 # average overall miss latency 5788428SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5798428SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5808428SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 5818428SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 5828983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5838983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5848428SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 5858428SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 5869096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 340 # number of ReadReq MSHR misses 5879096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses 5889079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses 5898835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses 5908835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses 5919096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 340 # number of demand (read+write) MSHR misses 5929096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 5939079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::total 481 # number of demand (read+write) MSHR misses 5949096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 340 # number of overall MSHR misses 5959096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 5969079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::total 481 # number of overall MSHR misses 5979096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10999000 # number of ReadReq MSHR miss cycles 5989096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3463000 # number of ReadReq MSHR miss cycles 5999096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 14462000 # number of ReadReq MSHR miss cycles 6009096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1839500 # number of ReadExReq MSHR miss cycles 6019096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1839500 # number of ReadExReq MSHR miss cycles 6029096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10999000 # number of demand (read+write) MSHR miss cycles 6039096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5302500 # number of demand (read+write) MSHR miss cycles 6049096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 16301500 # number of demand (read+write) MSHR miss cycles 6059096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10999000 # number of overall MSHR miss cycles 6069096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5302500 # number of overall MSHR miss cycles 6079096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 16301500 # number of overall MSHR miss cycles 6089096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991254 # mshr miss rate for ReadReq accesses 6098835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 6109079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993072 # mshr miss rate for ReadReq accesses 6118835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 6129055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 6139096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991254 # mshr miss rate for demand accesses 6148835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 6159079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.993802 # mshr miss rate for demand accesses 6169096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991254 # mshr miss rate for overall accesses 6178835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 6189079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.993802 # mshr miss rate for overall accesses 6199096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32350 # average ReadReq mshr miss latency 6209096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38477.777778 # average ReadReq mshr miss latency 6219096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33632.558140 # average ReadReq mshr miss latency 6229096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36068.627451 # average ReadExReq mshr miss latency 6239096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36068.627451 # average ReadExReq mshr miss latency 6249096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32350 # average overall mshr miss latency 6259096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37606.382979 # average overall mshr miss latency 6269096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 33890.852391 # average overall mshr miss latency 6279096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32350 # average overall mshr miss latency 6289096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37606.382979 # average overall mshr miss latency 6299096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 33890.852391 # average overall mshr miss latency 6308428SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 6316039SN/A 6326039SN/A---------- End Simulation Statistics ---------- 633