stats.txt revision 9079
16039SN/A 26039SN/A---------- Begin Simulation Statistics ---------- 39079SAli.Saidi@ARM.comsim_seconds 0.000012 # Number of seconds simulated 49079SAli.Saidi@ARM.comsim_ticks 12478500 # Number of ticks simulated 59079SAli.Saidi@ARM.comfinal_tick 12478500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79079SAli.Saidi@ARM.comhost_inst_rate 84509 # Simulator instruction rate (inst/s) 89079SAli.Saidi@ARM.comhost_op_rate 84485 # Simulator op (including micro ops) rate (op/s) 99079SAli.Saidi@ARM.comhost_tick_rate 203899861 # Simulator tick rate (ticks/s) 109079SAli.Saidi@ARM.comhost_mem_usage 220092 # Number of bytes of host memory used 119079SAli.Saidi@ARM.comhost_seconds 0.06 # Real time elapsed on the host 128428SN/Asim_insts 5169 # Number of instructions simulated 138835SAli.Saidi@ARM.comsim_ops 5169 # Number of ops (including micro ops) simulated 149079SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.inst 21632 # Number of bytes read from this memory 159079SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.data 9152 # Number of bytes read from this memory 169079SAli.Saidi@ARM.comsystem.physmem.bytes_read::total 30784 # Number of bytes read from this memory 179079SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::cpu.inst 21632 # Number of instructions bytes read from this memory 189079SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::total 21632 # Number of instructions bytes read from this memory 199079SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.inst 338 # Number of read requests responded to by this memory 209079SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.data 143 # Number of read requests responded to by this memory 219079SAli.Saidi@ARM.comsystem.physmem.num_reads::total 481 # Number of read requests responded to by this memory 229079SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.inst 1733541692 # Total read bandwidth from this memory (bytes/s) 239079SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.data 733421485 # Total read bandwidth from this memory (bytes/s) 249079SAli.Saidi@ARM.comsystem.physmem.bw_read::total 2466963177 # Total read bandwidth from this memory (bytes/s) 259079SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::cpu.inst 1733541692 # Instruction read bandwidth from this memory (bytes/s) 269079SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::total 1733541692 # Instruction read bandwidth from this memory (bytes/s) 279079SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.inst 1733541692 # Total bandwidth to/from this memory (bytes/s) 289079SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.data 733421485 # Total bandwidth to/from this memory (bytes/s) 299079SAli.Saidi@ARM.comsystem.physmem.bw_total::total 2466963177 # Total bandwidth to/from this memory (bytes/s) 308428SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 318428SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 328428SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 338428SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 348428SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 358428SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 366039SN/Asystem.cpu.dtb.hits 0 # DTB hits 376039SN/Asystem.cpu.dtb.misses 0 # DTB misses 388428SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 398428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 408428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 418428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 428428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 438428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 448428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 458428SN/Asystem.cpu.itb.hits 0 # DTB hits 468428SN/Asystem.cpu.itb.misses 0 # DTB misses 478428SN/Asystem.cpu.itb.accesses 0 # DTB accesses 488428SN/Asystem.cpu.workload.num_syscalls 8 # Number of system calls 499079SAli.Saidi@ARM.comsystem.cpu.numCycles 24958 # number of cpu cycles simulated 508428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 518428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 529079SAli.Saidi@ARM.comsystem.cpu.BPredUnit.lookups 2172 # Number of BP lookups 539079SAli.Saidi@ARM.comsystem.cpu.BPredUnit.condPredicted 1452 # Number of conditional branches predicted 549079SAli.Saidi@ARM.comsystem.cpu.BPredUnit.condIncorrect 447 # Number of conditional branches incorrect 559079SAli.Saidi@ARM.comsystem.cpu.BPredUnit.BTBLookups 1660 # Number of BTB lookups 569079SAli.Saidi@ARM.comsystem.cpu.BPredUnit.BTBHits 457 # Number of BTB hits 578428SN/Asystem.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 589079SAli.Saidi@ARM.comsystem.cpu.BPredUnit.usedRAS 278 # Number of times the RAS was used to get a target. 599079SAli.Saidi@ARM.comsystem.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. 609079SAli.Saidi@ARM.comsystem.cpu.fetch.icacheStallCycles 8142 # Number of cycles fetch is stalled on an Icache miss 619079SAli.Saidi@ARM.comsystem.cpu.fetch.Insts 13207 # Number of instructions fetch has processed 629079SAli.Saidi@ARM.comsystem.cpu.fetch.Branches 2172 # Number of branches that fetch encountered 639079SAli.Saidi@ARM.comsystem.cpu.fetch.predictedBranches 735 # Number of branches that fetch has predicted taken 649079SAli.Saidi@ARM.comsystem.cpu.fetch.Cycles 3199 # Number of cycles fetch has run and was not squashing or blocked 659079SAli.Saidi@ARM.comsystem.cpu.fetch.SquashCycles 1325 # Number of cycles fetch has spent squashing 669079SAli.Saidi@ARM.comsystem.cpu.fetch.BlockedCycles 670 # Number of cycles fetch has spent blocked 678464SN/Asystem.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 689079SAli.Saidi@ARM.comsystem.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps 699079SAli.Saidi@ARM.comsystem.cpu.fetch.CacheLines 1938 # Number of cache lines fetched 709079SAli.Saidi@ARM.comsystem.cpu.fetch.IcacheSquashes 262 # Number of outstanding Icache misses that were squashed 719079SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::samples 13025 # Number of instructions fetched each cycle (Total) 729079SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::mean 1.013973 # Number of instructions fetched each cycle (Total) 739079SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::stdev 2.329859 # Number of instructions fetched each cycle (Total) 746291SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 759079SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::0 9826 75.44% 75.44% # Number of instructions fetched each cycle (Total) 769079SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::1 1298 9.97% 85.40% # Number of instructions fetched each cycle (Total) 779079SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::2 113 0.87% 86.27% # Number of instructions fetched each cycle (Total) 789079SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::3 139 1.07% 87.34% # Number of instructions fetched each cycle (Total) 799079SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::4 293 2.25% 89.59% # Number of instructions fetched each cycle (Total) 809079SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::5 102 0.78% 90.37% # Number of instructions fetched each cycle (Total) 819079SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::6 157 1.21% 91.58% # Number of instructions fetched each cycle (Total) 829079SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::7 134 1.03% 92.61% # Number of instructions fetched each cycle (Total) 839079SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::8 963 7.39% 100.00% # Number of instructions fetched each cycle (Total) 846291SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 856291SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 866291SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 879079SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::total 13025 # Number of instructions fetched each cycle (Total) 889079SAli.Saidi@ARM.comsystem.cpu.fetch.branchRate 0.087026 # Number of branch fetches per cycle 899079SAli.Saidi@ARM.comsystem.cpu.fetch.rate 0.529169 # Number of inst fetches per cycle 909079SAli.Saidi@ARM.comsystem.cpu.decode.IdleCycles 8327 # Number of cycles decode is idle 919079SAli.Saidi@ARM.comsystem.cpu.decode.BlockedCycles 818 # Number of cycles decode is blocked 929079SAli.Saidi@ARM.comsystem.cpu.decode.RunCycles 3014 # Number of cycles decode is running 939079SAli.Saidi@ARM.comsystem.cpu.decode.UnblockCycles 41 # Number of cycles decode is unblocking 949079SAli.Saidi@ARM.comsystem.cpu.decode.SquashCycles 825 # Number of cycles decode is squashing 959079SAli.Saidi@ARM.comsystem.cpu.decode.BranchResolved 136 # Number of times decode resolved a branch 969079SAli.Saidi@ARM.comsystem.cpu.decode.BranchMispred 46 # Number of times decode detected a branch misprediction 979079SAli.Saidi@ARM.comsystem.cpu.decode.DecodedInsts 12256 # Number of instructions handled by decode 989079SAli.Saidi@ARM.comsystem.cpu.decode.SquashedInsts 188 # Number of squashed instructions handled by decode 999079SAli.Saidi@ARM.comsystem.cpu.rename.SquashCycles 825 # Number of cycles rename is squashing 1009079SAli.Saidi@ARM.comsystem.cpu.rename.IdleCycles 8509 # Number of cycles rename is idle 1019079SAli.Saidi@ARM.comsystem.cpu.rename.BlockCycles 222 # Number of cycles rename is blocking 1029079SAli.Saidi@ARM.comsystem.cpu.rename.serializeStallCycles 499 # count of cycles rename stalled for serializing inst 1039079SAli.Saidi@ARM.comsystem.cpu.rename.RunCycles 2873 # Number of cycles rename is running 1049079SAli.Saidi@ARM.comsystem.cpu.rename.UnblockCycles 97 # Number of cycles rename is unblocking 1059079SAli.Saidi@ARM.comsystem.cpu.rename.RenamedInsts 11712 # Number of instructions processed by rename 1069079SAli.Saidi@ARM.comsystem.cpu.rename.LSQFullEvents 88 # Number of times rename has blocked due to LSQ full 1079079SAli.Saidi@ARM.comsystem.cpu.rename.RenamedOperands 7146 # Number of destination operands rename has renamed 1089079SAli.Saidi@ARM.comsystem.cpu.rename.RenameLookups 13901 # Number of register rename lookups that rename has made 1099079SAli.Saidi@ARM.comsystem.cpu.rename.int_rename_lookups 13897 # Number of integer rename lookups 1108554SN/Asystem.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups 1118428SN/Asystem.cpu.rename.CommittedMaps 3410 # Number of HB maps that are committed 1129079SAli.Saidi@ARM.comsystem.cpu.rename.UndoneMaps 3736 # Number of HB maps that are undone due to squashing 1139079SAli.Saidi@ARM.comsystem.cpu.rename.serializingInsts 18 # count of serializing insts renamed 1149079SAli.Saidi@ARM.comsystem.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed 1159079SAli.Saidi@ARM.comsystem.cpu.rename.skidInsts 266 # count of insts added to the skid buffer 1169079SAli.Saidi@ARM.comsystem.cpu.memDep0.insertedLoads 2476 # Number of loads inserted to the mem dependence unit. 1179079SAli.Saidi@ARM.comsystem.cpu.memDep0.insertedStores 1180 # Number of stores inserted to the mem dependence unit. 1188428SN/Asystem.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 1198428SN/Asystem.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. 1209079SAli.Saidi@ARM.comsystem.cpu.iq.iqInstsAdded 9032 # Number of instructions added to the IQ (excludes non-spec) 1218464SN/Asystem.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ 1229079SAli.Saidi@ARM.comsystem.cpu.iq.iqInstsIssued 8121 # Number of instructions issued 1239079SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedInstsIssued 52 # Number of squashed instructions issued 1249079SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedInstsExamined 3346 # Number of squashed instructions iterated over during squash; mainly for profiling 1259079SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedOperandsExamined 2009 # Number of squashed operands that are examined and possibly removed from graph 1268464SN/Asystem.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed 1279079SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::samples 13025 # Number of insts issued each cycle 1289079SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::mean 0.623493 # Number of insts issued each cycle 1299079SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::stdev 1.295831 # Number of insts issued each cycle 1308428SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1319079SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::0 9566 73.44% 73.44% # Number of insts issued each cycle 1329079SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::1 1360 10.44% 83.88% # Number of insts issued each cycle 1339079SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::2 840 6.45% 90.33% # Number of insts issued each cycle 1349079SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::3 535 4.11% 94.44% # Number of insts issued each cycle 1359079SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::4 357 2.74% 97.18% # Number of insts issued each cycle 1369079SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::5 221 1.70% 98.88% # Number of insts issued each cycle 1379079SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::6 96 0.74% 99.62% # Number of insts issued each cycle 1389079SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::7 33 0.25% 99.87% # Number of insts issued each cycle 1399079SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::8 17 0.13% 100.00% # Number of insts issued each cycle 1408428SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1418428SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1428428SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1439079SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::total 13025 # Number of insts issued each cycle 1448428SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1458844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntAlu 4 2.63% 2.63% # attempts to use FU when none available 1468844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available 1478844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available 1488844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available 1498844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available 1508844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available 1518844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available 1528844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available 1538844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available 1548844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available 1558844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available 1568844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available 1578844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available 1588844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available 1598844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available 1608844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available 1618844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available 1628844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available 1638844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available 1648844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available 1658844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available 1668844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available 1678844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available 1688844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available 1698844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available 1708844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available 1718844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available 1728844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available 1738844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available 1749079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::MemRead 96 63.16% 65.79% # attempts to use FU when none available 1759079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::MemWrite 52 34.21% 100.00% # attempts to use FU when none available 1768428SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1778428SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1788241SN/Asystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 1799079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntAlu 4783 58.90% 58.90% # Type of FU issued 1809079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntMult 4 0.05% 58.95% # Type of FU issued 1819079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntDiv 2 0.02% 58.97% # Type of FU issued 1829079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.00% # Type of FU issued 1839079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.00% # Type of FU issued 1849079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.00% # Type of FU issued 1859079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.00% # Type of FU issued 1869079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.00% # Type of FU issued 1879079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.00% # Type of FU issued 1889079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.00% # Type of FU issued 1899079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.00% # Type of FU issued 1909079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.00% # Type of FU issued 1919079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.00% # Type of FU issued 1929079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.00% # Type of FU issued 1939079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.00% # Type of FU issued 1949079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.00% # Type of FU issued 1959079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.00% # Type of FU issued 1969079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.00% # Type of FU issued 1979079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.00% # Type of FU issued 1989079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.00% # Type of FU issued 1999079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.00% # Type of FU issued 2009079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.00% # Type of FU issued 2019079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.00% # Type of FU issued 2029079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.00% # Type of FU issued 2039079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.00% # Type of FU issued 2049079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.00% # Type of FU issued 2059079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.00% # Type of FU issued 2069079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.00% # Type of FU issued 2079079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.00% # Type of FU issued 2089079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::MemRead 2243 27.62% 86.61% # Type of FU issued 2099079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::MemWrite 1087 13.39% 100.00% # Type of FU issued 2108241SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2118241SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 2129079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::total 8121 # Type of FU issued 2139079SAli.Saidi@ARM.comsystem.cpu.iq.rate 0.325387 # Inst issue rate 2148844SAli.Saidi@ARM.comsystem.cpu.iq.fu_busy_cnt 152 # FU busy when requested 2159079SAli.Saidi@ARM.comsystem.cpu.iq.fu_busy_rate 0.018717 # FU busy rate (busy events/executed inst) 2169079SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_reads 29467 # Number of integer instruction queue reads 2179079SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_writes 12396 # Number of integer instruction queue writes 2189079SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 7292 # Number of integer instruction queue wakeup accesses 2198428SN/Asystem.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads 2208428SN/Asystem.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 2218428SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses 2229079SAli.Saidi@ARM.comsystem.cpu.iq.int_alu_accesses 8271 # Number of integer alu accesses 2238428SN/Asystem.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses 2249079SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores 2258428SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2269079SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.squashedLoads 1312 # Number of loads squashed 2279079SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed 2288844SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations 2299079SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.squashedStores 255 # Number of stores squashed 2308428SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2318428SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2328428SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 2338428SN/Asystem.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 2348428SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2359079SAli.Saidi@ARM.comsystem.cpu.iew.iewSquashCycles 825 # Number of cycles IEW is squashing 2369079SAli.Saidi@ARM.comsystem.cpu.iew.iewBlockCycles 149 # Number of cycles IEW is blocking 2379079SAli.Saidi@ARM.comsystem.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking 2389079SAli.Saidi@ARM.comsystem.cpu.iew.iewDispatchedInsts 10514 # Number of instructions dispatched to IQ 2399079SAli.Saidi@ARM.comsystem.cpu.iew.iewDispSquashedInsts 112 # Number of squashed instructions skipped by dispatch 2409079SAli.Saidi@ARM.comsystem.cpu.iew.iewDispLoadInsts 2476 # Number of dispatched load instructions 2419079SAli.Saidi@ARM.comsystem.cpu.iew.iewDispStoreInsts 1180 # Number of dispatched store instructions 2428464SN/Asystem.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions 2438844SAli.Saidi@ARM.comsystem.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall 2449079SAli.Saidi@ARM.comsystem.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall 2458844SAli.Saidi@ARM.comsystem.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations 2469079SAli.Saidi@ARM.comsystem.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly 2479079SAli.Saidi@ARM.comsystem.cpu.iew.predictedNotTakenIncorrect 373 # Number of branches that were predicted not taken incorrectly 2489079SAli.Saidi@ARM.comsystem.cpu.iew.branchMispredicts 480 # Number of branch mispredicts detected at execute 2499079SAli.Saidi@ARM.comsystem.cpu.iew.iewExecutedInsts 7766 # Number of executed instructions 2509079SAli.Saidi@ARM.comsystem.cpu.iew.iewExecLoadInsts 2126 # Number of load instructions executed 2519079SAli.Saidi@ARM.comsystem.cpu.iew.iewExecSquashedInsts 355 # Number of squashed instructions skipped in execute 2528428SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 2539079SAli.Saidi@ARM.comsystem.cpu.iew.exec_nop 1469 # number of nop insts executed 2549079SAli.Saidi@ARM.comsystem.cpu.iew.exec_refs 3191 # number of memory reference insts executed 2559079SAli.Saidi@ARM.comsystem.cpu.iew.exec_branches 1304 # Number of branches executed 2569079SAli.Saidi@ARM.comsystem.cpu.iew.exec_stores 1065 # Number of stores executed 2579079SAli.Saidi@ARM.comsystem.cpu.iew.exec_rate 0.311163 # Inst execution rate 2589079SAli.Saidi@ARM.comsystem.cpu.iew.wb_sent 7392 # cumulative count of insts sent to commit 2599079SAli.Saidi@ARM.comsystem.cpu.iew.wb_count 7294 # cumulative count of insts written-back 2609079SAli.Saidi@ARM.comsystem.cpu.iew.wb_producers 2836 # num instructions producing a value 2619079SAli.Saidi@ARM.comsystem.cpu.iew.wb_consumers 4075 # num instructions consuming a value 2628428SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 2639079SAli.Saidi@ARM.comsystem.cpu.iew.wb_rate 0.292251 # insts written-back per cycle 2649079SAli.Saidi@ARM.comsystem.cpu.iew.wb_fanout 0.695951 # average fanout of values written-back 2658428SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 2668428SN/Asystem.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions 2678835SAli.Saidi@ARM.comsystem.cpu.commit.commitCommittedOps 5826 # The number of committed instructions 2689079SAli.Saidi@ARM.comsystem.cpu.commit.commitSquashedInsts 4683 # The number of squashed insts skipped by commit 2698428SN/Asystem.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards 2709079SAli.Saidi@ARM.comsystem.cpu.commit.branchMispredicts 402 # The number of times a branch was mispredicted 2719079SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::samples 12200 # Number of insts commited each cycle 2729079SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::mean 0.477541 # Number of insts commited each cycle 2739079SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::stdev 1.256570 # Number of insts commited each cycle 2748428SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2759079SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::0 9781 80.17% 80.17% # Number of insts commited each cycle 2769079SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::1 1000 8.20% 88.37% # Number of insts commited each cycle 2779079SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::2 629 5.16% 93.52% # Number of insts commited each cycle 2789079SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::3 333 2.73% 96.25% # Number of insts commited each cycle 2799079SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::4 158 1.30% 97.55% # Number of insts commited each cycle 2809079SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::5 93 0.76% 98.31% # Number of insts commited each cycle 2819079SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::6 67 0.55% 98.86% # Number of insts commited each cycle 2829079SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::7 42 0.34% 99.20% # Number of insts commited each cycle 2839079SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::8 97 0.80% 100.00% # Number of insts commited each cycle 2848428SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2858428SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2868428SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 2879079SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::total 12200 # Number of insts commited each cycle 2888835SAli.Saidi@ARM.comsystem.cpu.commit.committedInsts 5826 # Number of instructions committed 2898835SAli.Saidi@ARM.comsystem.cpu.commit.committedOps 5826 # Number of ops (including micro ops) committed 2908428SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 2918428SN/Asystem.cpu.commit.refs 2089 # Number of memory references committed 2928428SN/Asystem.cpu.commit.loads 1164 # Number of loads committed 2938428SN/Asystem.cpu.commit.membars 0 # Number of memory barriers committed 2948428SN/Asystem.cpu.commit.branches 916 # Number of branches committed 2958428SN/Asystem.cpu.commit.fp_insts 2 # Number of committed floating point instructions. 2968428SN/Asystem.cpu.commit.int_insts 5124 # Number of committed integer instructions. 2978428SN/Asystem.cpu.commit.function_calls 87 # Number of function calls committed. 2989079SAli.Saidi@ARM.comsystem.cpu.commit.bw_lim_events 97 # number cycles where commit BW limit reached 2998428SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 3009079SAli.Saidi@ARM.comsystem.cpu.rob.rob_reads 22599 # The number of ROB reads 3019079SAli.Saidi@ARM.comsystem.cpu.rob.rob_writes 21853 # The number of ROB writes 3029079SAli.Saidi@ARM.comsystem.cpu.timesIdled 249 # Number of times that the entire CPU went into an idle state and unscheduled itself 3039079SAli.Saidi@ARM.comsystem.cpu.idleCycles 11933 # Total number of cycles that the CPU has spent unscheduled due to idling 3048428SN/Asystem.cpu.committedInsts 5169 # Number of Instructions Simulated 3058835SAli.Saidi@ARM.comsystem.cpu.committedOps 5169 # Number of Ops (including micro ops) Simulated 3068428SN/Asystem.cpu.committedInsts_total 5169 # Number of Instructions Simulated 3079079SAli.Saidi@ARM.comsystem.cpu.cpi 4.828400 # CPI: Cycles Per Instruction 3089079SAli.Saidi@ARM.comsystem.cpu.cpi_total 4.828400 # CPI: Total CPI of All Threads 3099079SAli.Saidi@ARM.comsystem.cpu.ipc 0.207108 # IPC: Instructions Per Cycle 3109079SAli.Saidi@ARM.comsystem.cpu.ipc_total 0.207108 # IPC: Total IPC of All Threads 3119079SAli.Saidi@ARM.comsystem.cpu.int_regfile_reads 10560 # number of integer regfile reads 3129079SAli.Saidi@ARM.comsystem.cpu.int_regfile_writes 5130 # number of integer regfile writes 3138428SN/Asystem.cpu.fp_regfile_reads 3 # number of floating regfile reads 3148428SN/Asystem.cpu.fp_regfile_writes 1 # number of floating regfile writes 3159079SAli.Saidi@ARM.comsystem.cpu.misc_regfile_reads 150 # number of misc regfile reads 3169079SAli.Saidi@ARM.comsystem.cpu.icache.replacements 17 # number of replacements 3179079SAli.Saidi@ARM.comsystem.cpu.icache.tagsinuse 163.784522 # Cycle average of tags in use 3189079SAli.Saidi@ARM.comsystem.cpu.icache.total_refs 1503 # Total number of references to valid blocks. 3199079SAli.Saidi@ARM.comsystem.cpu.icache.sampled_refs 341 # Sample count of references to valid blocks. 3209079SAli.Saidi@ARM.comsystem.cpu.icache.avg_refs 4.407625 # Average number of references to valid blocks. 3218428SN/Asystem.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 3229079SAli.Saidi@ARM.comsystem.cpu.icache.occ_blocks::cpu.inst 163.784522 # Average occupied blocks per requestor 3239079SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::cpu.inst 0.079973 # Average percentage of cache occupancy 3249079SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::total 0.079973 # Average percentage of cache occupancy 3259079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1503 # number of ReadReq hits 3269079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::total 1503 # number of ReadReq hits 3279079SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::cpu.inst 1503 # number of demand (read+write) hits 3289079SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::total 1503 # number of demand (read+write) hits 3299079SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::cpu.inst 1503 # number of overall hits 3309079SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::total 1503 # number of overall hits 3319079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::cpu.inst 435 # number of ReadReq misses 3329079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::total 435 # number of ReadReq misses 3339079SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::cpu.inst 435 # number of demand (read+write) misses 3349079SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::total 435 # number of demand (read+write) misses 3359079SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::cpu.inst 435 # number of overall misses 3369079SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::total 435 # number of overall misses 3379079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 15599500 # number of ReadReq miss cycles 3389079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_latency::total 15599500 # number of ReadReq miss cycles 3399079SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_latency::cpu.inst 15599500 # number of demand (read+write) miss cycles 3409079SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_latency::total 15599500 # number of demand (read+write) miss cycles 3419079SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_latency::cpu.inst 15599500 # number of overall miss cycles 3429079SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_latency::total 15599500 # number of overall miss cycles 3439079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 1938 # number of ReadReq accesses(hits+misses) 3449079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::total 1938 # number of ReadReq accesses(hits+misses) 3459079SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::cpu.inst 1938 # number of demand (read+write) accesses 3469079SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::total 1938 # number of demand (read+write) accesses 3479079SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::cpu.inst 1938 # number of overall (read+write) accesses 3489079SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::total 1938 # number of overall (read+write) accesses 3499079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.224458 # miss rate for ReadReq accesses 3509079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::total 0.224458 # miss rate for ReadReq accesses 3519079SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.224458 # miss rate for demand accesses 3529079SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::total 0.224458 # miss rate for demand accesses 3539079SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.224458 # miss rate for overall accesses 3549079SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::total 0.224458 # miss rate for overall accesses 3559079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35860.919540 # average ReadReq miss latency 3569079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 35860.919540 # average ReadReq miss latency 3579079SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 35860.919540 # average overall miss latency 3589079SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_miss_latency::total 35860.919540 # average overall miss latency 3599079SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 35860.919540 # average overall miss latency 3609079SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_miss_latency::total 35860.919540 # average overall miss latency 3618428SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3628428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3638428SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 3648428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 3658983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3668983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3678428SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 3688428SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 3699079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 94 # number of ReadReq MSHR hits 3709079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_hits::total 94 # number of ReadReq MSHR hits 3719079SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 94 # number of demand (read+write) MSHR hits 3729079SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits 3739079SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 94 # number of overall MSHR hits 3749079SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_hits::total 94 # number of overall MSHR hits 3759079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 341 # number of ReadReq MSHR misses 3769079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::total 341 # number of ReadReq MSHR misses 3779079SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 341 # number of demand (read+write) MSHR misses 3789079SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::total 341 # number of demand (read+write) MSHR misses 3799079SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 341 # number of overall MSHR misses 3809079SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::total 341 # number of overall MSHR misses 3819079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11963500 # number of ReadReq MSHR miss cycles 3829079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 11963500 # number of ReadReq MSHR miss cycles 3839079SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 11963500 # number of demand (read+write) MSHR miss cycles 3849079SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::total 11963500 # number of demand (read+write) MSHR miss cycles 3859079SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 11963500 # number of overall MSHR miss cycles 3869079SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::total 11963500 # number of overall MSHR miss cycles 3879079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.175955 # mshr miss rate for ReadReq accesses 3889079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.175955 # mshr miss rate for ReadReq accesses 3899079SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.175955 # mshr miss rate for demand accesses 3909079SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.175955 # mshr miss rate for demand accesses 3919079SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.175955 # mshr miss rate for overall accesses 3929079SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.175955 # mshr miss rate for overall accesses 3939079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35083.577713 # average ReadReq mshr miss latency 3949079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35083.577713 # average ReadReq mshr miss latency 3959079SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35083.577713 # average overall mshr miss latency 3969079SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 35083.577713 # average overall mshr miss latency 3979079SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35083.577713 # average overall mshr miss latency 3989079SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 35083.577713 # average overall mshr miss latency 3998428SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 4008428SN/Asystem.cpu.dcache.replacements 0 # number of replacements 4019079SAli.Saidi@ARM.comsystem.cpu.dcache.tagsinuse 92.268506 # Cycle average of tags in use 4029079SAli.Saidi@ARM.comsystem.cpu.dcache.total_refs 2489 # Total number of references to valid blocks. 4039079SAli.Saidi@ARM.comsystem.cpu.dcache.sampled_refs 143 # Sample count of references to valid blocks. 4049079SAli.Saidi@ARM.comsystem.cpu.dcache.avg_refs 17.405594 # Average number of references to valid blocks. 4058428SN/Asystem.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 4069079SAli.Saidi@ARM.comsystem.cpu.dcache.occ_blocks::cpu.data 92.268506 # Average occupied blocks per requestor 4079079SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::cpu.data 0.022526 # Average percentage of cache occupancy 4089079SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::total 0.022526 # Average percentage of cache occupancy 4099079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1903 # number of ReadReq hits 4109079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_hits::total 1903 # number of ReadReq hits 4118844SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::cpu.data 586 # number of WriteReq hits 4128844SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::total 586 # number of WriteReq hits 4139079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_hits::cpu.data 2489 # number of demand (read+write) hits 4149079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_hits::total 2489 # number of demand (read+write) hits 4159079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_hits::cpu.data 2489 # number of overall hits 4169079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_hits::total 2489 # number of overall hits 4178835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::cpu.data 133 # number of ReadReq misses 4188835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::total 133 # number of ReadReq misses 4198844SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::cpu.data 339 # number of WriteReq misses 4208844SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::total 339 # number of WriteReq misses 4218844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::cpu.data 472 # number of demand (read+write) misses 4228844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::total 472 # number of demand (read+write) misses 4238844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::cpu.data 472 # number of overall misses 4248844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::total 472 # number of overall misses 4259079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 4784500 # number of ReadReq miss cycles 4269079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_latency::total 4784500 # number of ReadReq miss cycles 4279079SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 11421000 # number of WriteReq miss cycles 4289079SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_latency::total 11421000 # number of WriteReq miss cycles 4299079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_latency::cpu.data 16205500 # number of demand (read+write) miss cycles 4309079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_latency::total 16205500 # number of demand (read+write) miss cycles 4319079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_latency::cpu.data 16205500 # number of overall miss cycles 4329079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_latency::total 16205500 # number of overall miss cycles 4339079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 2036 # number of ReadReq accesses(hits+misses) 4349079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_accesses::total 2036 # number of ReadReq accesses(hits+misses) 4358835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 4368835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 4379079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_accesses::cpu.data 2961 # number of demand (read+write) accesses 4389079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_accesses::total 2961 # number of demand (read+write) accesses 4399079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_accesses::cpu.data 2961 # number of overall (read+write) accesses 4409079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_accesses::total 2961 # number of overall (read+write) accesses 4419079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065324 # miss rate for ReadReq accesses 4429079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.065324 # miss rate for ReadReq accesses 4438844SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.366486 # miss rate for WriteReq accesses 4449055Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_miss_rate::total 0.366486 # miss rate for WriteReq accesses 4459079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.159406 # miss rate for demand accesses 4469079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::total 0.159406 # miss rate for demand accesses 4479079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.159406 # miss rate for overall accesses 4489079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_rate::total 0.159406 # miss rate for overall accesses 4499079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35973.684211 # average ReadReq miss latency 4509079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 35973.684211 # average ReadReq miss latency 4519079SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33690.265487 # average WriteReq miss latency 4529079SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 33690.265487 # average WriteReq miss latency 4539079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 34333.686441 # average overall miss latency 4549079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_miss_latency::total 34333.686441 # average overall miss latency 4559079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 34333.686441 # average overall miss latency 4569079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_miss_latency::total 34333.686441 # average overall miss latency 4578428SN/Asystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4588428SN/Asystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4598428SN/Asystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 4608428SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 4618983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 4628983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 4638428SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 4648428SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 4659079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 41 # number of ReadReq MSHR hits 4669079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_hits::total 41 # number of ReadReq MSHR hits 4678844SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 288 # number of WriteReq MSHR hits 4688844SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_hits::total 288 # number of WriteReq MSHR hits 4699079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 329 # number of demand (read+write) MSHR hits 4709079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_hits::total 329 # number of demand (read+write) MSHR hits 4719079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 329 # number of overall MSHR hits 4729079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_hits::total 329 # number of overall MSHR hits 4739079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 92 # number of ReadReq MSHR misses 4749079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::total 92 # number of ReadReq MSHR misses 4758835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses 4768835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses 4779079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses 4789079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses 4799079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses 4809079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses 4819079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3306000 # number of ReadReq MSHR miss cycles 4829079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 3306000 # number of ReadReq MSHR miss cycles 4839079SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1845000 # number of WriteReq MSHR miss cycles 4849079SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 1845000 # number of WriteReq MSHR miss cycles 4859079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 5151000 # number of demand (read+write) MSHR miss cycles 4869079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_latency::total 5151000 # number of demand (read+write) MSHR miss cycles 4879079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 5151000 # number of overall MSHR miss cycles 4889079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_latency::total 5151000 # number of overall MSHR miss cycles 4899079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045187 # mshr miss rate for ReadReq accesses 4909079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045187 # mshr miss rate for ReadReq accesses 4918835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses 4929055Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses 4939079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048294 # mshr miss rate for demand accesses 4949079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.048294 # mshr miss rate for demand accesses 4959079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048294 # mshr miss rate for overall accesses 4969079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.048294 # mshr miss rate for overall accesses 4979079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35934.782609 # average ReadReq mshr miss latency 4989079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35934.782609 # average ReadReq mshr miss latency 4999079SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36176.470588 # average WriteReq mshr miss latency 5009079SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36176.470588 # average WriteReq mshr miss latency 5019079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36020.979021 # average overall mshr miss latency 5029079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 36020.979021 # average overall mshr miss latency 5039079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36020.979021 # average overall mshr miss latency 5049079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 36020.979021 # average overall mshr miss latency 5058428SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 5068428SN/Asystem.cpu.l2cache.replacements 0 # number of replacements 5079079SAli.Saidi@ARM.comsystem.cpu.l2cache.tagsinuse 224.190745 # Cycle average of tags in use 5088428SN/Asystem.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. 5099079SAli.Saidi@ARM.comsystem.cpu.l2cache.sampled_refs 430 # Sample count of references to valid blocks. 5109079SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_refs 0.006977 # Average number of references to valid blocks. 5118428SN/Asystem.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 5129079SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_blocks::cpu.inst 165.976213 # Average occupied blocks per requestor 5139079SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_blocks::cpu.data 58.214532 # Average occupied blocks per requestor 5149079SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::cpu.inst 0.005065 # Average percentage of cache occupancy 5159079SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::cpu.data 0.001777 # Average percentage of cache occupancy 5169079SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::total 0.006842 # Average percentage of cache occupancy 5178835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits 5188835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits 5198835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 5208835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 5218835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 5228835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 3 # number of overall hits 5239079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 338 # number of ReadReq misses 5249079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 92 # number of ReadReq misses 5259079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::total 430 # number of ReadReq misses 5268835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses 5278835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses 5289079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.inst 338 # number of demand (read+write) misses 5299079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.data 143 # number of demand (read+write) misses 5309079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::total 481 # number of demand (read+write) misses 5319079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.inst 338 # number of overall misses 5329079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.data 143 # number of overall misses 5339079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::total 481 # number of overall misses 5349079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11593500 # number of ReadReq miss cycles 5359079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 3178500 # number of ReadReq miss cycles 5369079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::total 14772000 # number of ReadReq miss cycles 5379079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1768500 # number of ReadExReq miss cycles 5389079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 1768500 # number of ReadExReq miss cycles 5399079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 11593500 # number of demand (read+write) miss cycles 5409079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 4947000 # number of demand (read+write) miss cycles 5419079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::total 16540500 # number of demand (read+write) miss cycles 5429079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 11593500 # number of overall miss cycles 5439079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 4947000 # number of overall miss cycles 5449079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::total 16540500 # number of overall miss cycles 5459079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 341 # number of ReadReq accesses(hits+misses) 5469079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 92 # number of ReadReq accesses(hits+misses) 5479079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::total 433 # number of ReadReq accesses(hits+misses) 5488835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) 5498835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) 5509079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.inst 341 # number of demand (read+write) accesses 5519079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.data 143 # number of demand (read+write) accesses 5529079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::total 484 # number of demand (read+write) accesses 5539079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.inst 341 # number of overall (read+write) accesses 5549079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.data 143 # number of overall (read+write) accesses 5559079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::total 484 # number of overall (read+write) accesses 5569079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991202 # miss rate for ReadReq accesses 5578835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 5589079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.993072 # miss rate for ReadReq accesses 5598835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 5609055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 5619079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.991202 # miss rate for demand accesses 5628835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 5639079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::total 0.993802 # miss rate for demand accesses 5649079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.991202 # miss rate for overall accesses 5658835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 5669079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::total 0.993802 # miss rate for overall accesses 5679079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34300.295858 # average ReadReq miss latency 5689079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34548.913043 # average ReadReq miss latency 5699079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 34353.488372 # average ReadReq miss latency 5709079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34676.470588 # average ReadExReq miss latency 5719079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 34676.470588 # average ReadExReq miss latency 5729079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34300.295858 # average overall miss latency 5739079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 34594.405594 # average overall miss latency 5749079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::total 34387.733888 # average overall miss latency 5759079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34300.295858 # average overall miss latency 5769079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 34594.405594 # average overall miss latency 5779079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::total 34387.733888 # average overall miss latency 5788428SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5798428SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5808428SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 5818428SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 5828983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5838983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5848428SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 5858428SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 5869079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses 5879079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 92 # number of ReadReq MSHR misses 5889079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses 5898835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses 5908835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses 5919079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses 5929079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses 5939079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::total 481 # number of demand (read+write) MSHR misses 5949079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses 5959079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses 5969079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::total 481 # number of overall MSHR misses 5979079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10498500 # number of ReadReq MSHR miss cycles 5989079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2890500 # number of ReadReq MSHR miss cycles 5999079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 13389000 # number of ReadReq MSHR miss cycles 6008844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1604000 # number of ReadExReq MSHR miss cycles 6018844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1604000 # number of ReadExReq MSHR miss cycles 6029079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10498500 # number of demand (read+write) MSHR miss cycles 6039079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4494500 # number of demand (read+write) MSHR miss cycles 6049079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 14993000 # number of demand (read+write) MSHR miss cycles 6059079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10498500 # number of overall MSHR miss cycles 6069079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4494500 # number of overall MSHR miss cycles 6079079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 14993000 # number of overall MSHR miss cycles 6089079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991202 # mshr miss rate for ReadReq accesses 6098835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 6109079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993072 # mshr miss rate for ReadReq accesses 6118835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 6129055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 6139079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991202 # mshr miss rate for demand accesses 6148835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 6159079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.993802 # mshr miss rate for demand accesses 6169079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991202 # mshr miss rate for overall accesses 6178835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 6189079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.993802 # mshr miss rate for overall accesses 6199079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31060.650888 # average ReadReq mshr miss latency 6209079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31418.478261 # average ReadReq mshr miss latency 6219079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31137.209302 # average ReadReq mshr miss latency 6228844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31450.980392 # average ReadExReq mshr miss latency 6239055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31450.980392 # average ReadExReq mshr miss latency 6249079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31060.650888 # average overall mshr miss latency 6259079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31430.069930 # average overall mshr miss latency 6269079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 31170.478170 # average overall mshr miss latency 6279079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31060.650888 # average overall mshr miss latency 6289079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31430.069930 # average overall mshr miss latency 6299079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 31170.478170 # average overall mshr miss latency 6308428SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 6316039SN/A 6326039SN/A---------- End Simulation Statistics ---------- 633