stats.txt revision 9055
16039SN/A 26039SN/A---------- Begin Simulation Statistics ---------- 38844SAli.Saidi@ARM.comsim_seconds 0.000013 # Number of seconds simulated 48844SAli.Saidi@ARM.comsim_ticks 12671500 # Number of ticks simulated 58844SAli.Saidi@ARM.comfinal_tick 12671500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79055Ssaidi@eecs.umich.eduhost_inst_rate 63611 # Simulator instruction rate (inst/s) 89055Ssaidi@eecs.umich.eduhost_op_rate 63597 # Simulator op (including micro ops) rate (op/s) 99055Ssaidi@eecs.umich.eduhost_tick_rate 155871053 # Simulator tick rate (ticks/s) 109055Ssaidi@eecs.umich.eduhost_mem_usage 216124 # Number of bytes of host memory used 119055Ssaidi@eecs.umich.eduhost_seconds 0.08 # Real time elapsed on the host 128428SN/Asim_insts 5169 # Number of instructions simulated 138835SAli.Saidi@ARM.comsim_ops 5169 # Number of ops (including micro ops) simulated 149055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu.inst 21824 # Number of bytes read from this memory 159055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory 169055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::total 30912 # Number of bytes read from this memory 179055Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::cpu.inst 21824 # Number of instructions bytes read from this memory 189055Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::total 21824 # Number of instructions bytes read from this memory 199055Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu.inst 341 # Number of read requests responded to by this memory 209055Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory 219055Ssaidi@eecs.umich.edusystem.physmem.num_reads::total 483 # Number of read requests responded to by this memory 229055Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu.inst 1722290179 # Total read bandwidth from this memory (bytes/s) 239055Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu.data 717200016 # Total read bandwidth from this memory (bytes/s) 249055Ssaidi@eecs.umich.edusystem.physmem.bw_read::total 2439490195 # Total read bandwidth from this memory (bytes/s) 259055Ssaidi@eecs.umich.edusystem.physmem.bw_inst_read::cpu.inst 1722290179 # Instruction read bandwidth from this memory (bytes/s) 269055Ssaidi@eecs.umich.edusystem.physmem.bw_inst_read::total 1722290179 # Instruction read bandwidth from this memory (bytes/s) 279055Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu.inst 1722290179 # Total bandwidth to/from this memory (bytes/s) 289055Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu.data 717200016 # Total bandwidth to/from this memory (bytes/s) 299055Ssaidi@eecs.umich.edusystem.physmem.bw_total::total 2439490195 # Total bandwidth to/from this memory (bytes/s) 308428SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 318428SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 328428SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 338428SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 348428SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 358428SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 366039SN/Asystem.cpu.dtb.hits 0 # DTB hits 376039SN/Asystem.cpu.dtb.misses 0 # DTB misses 388428SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 398428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 408428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 418428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 428428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 438428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 448428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 458428SN/Asystem.cpu.itb.hits 0 # DTB hits 468428SN/Asystem.cpu.itb.misses 0 # DTB misses 478428SN/Asystem.cpu.itb.accesses 0 # DTB accesses 488428SN/Asystem.cpu.workload.num_syscalls 8 # Number of system calls 498844SAli.Saidi@ARM.comsystem.cpu.numCycles 25344 # number of cpu cycles simulated 508428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 518428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 528844SAli.Saidi@ARM.comsystem.cpu.BPredUnit.lookups 2242 # Number of BP lookups 538844SAli.Saidi@ARM.comsystem.cpu.BPredUnit.condPredicted 1547 # Number of conditional branches predicted 548844SAli.Saidi@ARM.comsystem.cpu.BPredUnit.condIncorrect 477 # Number of conditional branches incorrect 558844SAli.Saidi@ARM.comsystem.cpu.BPredUnit.BTBLookups 1757 # Number of BTB lookups 568844SAli.Saidi@ARM.comsystem.cpu.BPredUnit.BTBHits 473 # Number of BTB hits 578428SN/Asystem.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 588844SAli.Saidi@ARM.comsystem.cpu.BPredUnit.usedRAS 271 # Number of times the RAS was used to get a target. 598844SAli.Saidi@ARM.comsystem.cpu.BPredUnit.RASInCorrect 92 # Number of incorrect RAS predictions. 608844SAli.Saidi@ARM.comsystem.cpu.fetch.icacheStallCycles 8296 # Number of cycles fetch is stalled on an Icache miss 618844SAli.Saidi@ARM.comsystem.cpu.fetch.Insts 13683 # Number of instructions fetch has processed 628844SAli.Saidi@ARM.comsystem.cpu.fetch.Branches 2242 # Number of branches that fetch encountered 638517SN/Asystem.cpu.fetch.predictedBranches 744 # Number of branches that fetch has predicted taken 648844SAli.Saidi@ARM.comsystem.cpu.fetch.Cycles 3324 # Number of cycles fetch has run and was not squashing or blocked 658844SAli.Saidi@ARM.comsystem.cpu.fetch.SquashCycles 1376 # Number of cycles fetch has spent squashing 668844SAli.Saidi@ARM.comsystem.cpu.fetch.BlockedCycles 663 # Number of cycles fetch has spent blocked 678464SN/Asystem.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 688844SAli.Saidi@ARM.comsystem.cpu.fetch.PendingTrapStallCycles 87 # Number of stall cycles due to pending traps 698844SAli.Saidi@ARM.comsystem.cpu.fetch.CacheLines 2039 # Number of cache lines fetched 708844SAli.Saidi@ARM.comsystem.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed 718844SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::samples 13263 # Number of instructions fetched each cycle (Total) 728844SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::mean 1.031667 # Number of instructions fetched each cycle (Total) 738844SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::stdev 2.344238 # Number of instructions fetched each cycle (Total) 746291SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 758844SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::0 9939 74.94% 74.94% # Number of instructions fetched each cycle (Total) 768844SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::1 1348 10.16% 85.10% # Number of instructions fetched each cycle (Total) 778844SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::2 128 0.97% 86.07% # Number of instructions fetched each cycle (Total) 788844SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::3 139 1.05% 87.11% # Number of instructions fetched each cycle (Total) 798844SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::4 303 2.28% 89.40% # Number of instructions fetched each cycle (Total) 808844SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::5 122 0.92% 90.32% # Number of instructions fetched each cycle (Total) 818844SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::6 146 1.10% 91.42% # Number of instructions fetched each cycle (Total) 828844SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::7 140 1.06% 92.48% # Number of instructions fetched each cycle (Total) 838844SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::8 998 7.52% 100.00% # Number of instructions fetched each cycle (Total) 846291SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 856291SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 866291SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 878844SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::total 13263 # Number of instructions fetched each cycle (Total) 888844SAli.Saidi@ARM.comsystem.cpu.fetch.branchRate 0.088463 # Number of branch fetches per cycle 898844SAli.Saidi@ARM.comsystem.cpu.fetch.rate 0.539891 # Number of inst fetches per cycle 908844SAli.Saidi@ARM.comsystem.cpu.decode.IdleCycles 8460 # Number of cycles decode is idle 918844SAli.Saidi@ARM.comsystem.cpu.decode.BlockedCycles 795 # Number of cycles decode is blocked 928844SAli.Saidi@ARM.comsystem.cpu.decode.RunCycles 3128 # Number of cycles decode is running 938844SAli.Saidi@ARM.comsystem.cpu.decode.UnblockCycles 40 # Number of cycles decode is unblocking 948844SAli.Saidi@ARM.comsystem.cpu.decode.SquashCycles 840 # Number of cycles decode is squashing 958844SAli.Saidi@ARM.comsystem.cpu.decode.BranchResolved 144 # Number of times decode resolved a branch 968844SAli.Saidi@ARM.comsystem.cpu.decode.BranchMispred 52 # Number of times decode detected a branch misprediction 978844SAli.Saidi@ARM.comsystem.cpu.decode.DecodedInsts 12579 # Number of instructions handled by decode 988844SAli.Saidi@ARM.comsystem.cpu.decode.SquashedInsts 215 # Number of squashed instructions handled by decode 998844SAli.Saidi@ARM.comsystem.cpu.rename.SquashCycles 840 # Number of cycles rename is squashing 1008844SAli.Saidi@ARM.comsystem.cpu.rename.IdleCycles 8664 # Number of cycles rename is idle 1018844SAli.Saidi@ARM.comsystem.cpu.rename.BlockCycles 204 # Number of cycles rename is blocking 1028844SAli.Saidi@ARM.comsystem.cpu.rename.serializeStallCycles 498 # count of cycles rename stalled for serializing inst 1038844SAli.Saidi@ARM.comsystem.cpu.rename.RunCycles 2966 # Number of cycles rename is running 1048844SAli.Saidi@ARM.comsystem.cpu.rename.UnblockCycles 91 # Number of cycles rename is unblocking 1058844SAli.Saidi@ARM.comsystem.cpu.rename.RenamedInsts 11935 # Number of instructions processed by rename 1068844SAli.Saidi@ARM.comsystem.cpu.rename.LSQFullEvents 82 # Number of times rename has blocked due to LSQ full 1078844SAli.Saidi@ARM.comsystem.cpu.rename.RenamedOperands 7222 # Number of destination operands rename has renamed 1088844SAli.Saidi@ARM.comsystem.cpu.rename.RenameLookups 14215 # Number of register rename lookups that rename has made 1098844SAli.Saidi@ARM.comsystem.cpu.rename.int_rename_lookups 14211 # Number of integer rename lookups 1108554SN/Asystem.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups 1118428SN/Asystem.cpu.rename.CommittedMaps 3410 # Number of HB maps that are committed 1128844SAli.Saidi@ARM.comsystem.cpu.rename.UndoneMaps 3812 # Number of HB maps that are undone due to squashing 1138844SAli.Saidi@ARM.comsystem.cpu.rename.serializingInsts 17 # count of serializing insts renamed 1148844SAli.Saidi@ARM.comsystem.cpu.rename.tempSerializingInsts 12 # count of temporary serializing insts renamed 1158844SAli.Saidi@ARM.comsystem.cpu.rename.skidInsts 229 # count of insts added to the skid buffer 1168844SAli.Saidi@ARM.comsystem.cpu.memDep0.insertedLoads 2496 # Number of loads inserted to the mem dependence unit. 1178844SAli.Saidi@ARM.comsystem.cpu.memDep0.insertedStores 1209 # Number of stores inserted to the mem dependence unit. 1188428SN/Asystem.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 1198428SN/Asystem.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. 1208844SAli.Saidi@ARM.comsystem.cpu.iq.iqInstsAdded 9121 # Number of instructions added to the IQ (excludes non-spec) 1218464SN/Asystem.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ 1228844SAli.Saidi@ARM.comsystem.cpu.iq.iqInstsIssued 8177 # Number of instructions issued 1238844SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedInstsIssued 38 # Number of squashed instructions issued 1248844SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedInstsExamined 3469 # Number of squashed instructions iterated over during squash; mainly for profiling 1258844SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedOperandsExamined 2115 # Number of squashed operands that are examined and possibly removed from graph 1268464SN/Asystem.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed 1278844SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::samples 13263 # Number of insts issued each cycle 1288844SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::mean 0.616527 # Number of insts issued each cycle 1298844SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::stdev 1.283212 # Number of insts issued each cycle 1308428SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1318844SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::0 9760 73.59% 73.59% # Number of insts issued each cycle 1328844SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::1 1384 10.44% 84.02% # Number of insts issued each cycle 1338844SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::2 845 6.37% 90.39% # Number of insts issued each cycle 1348844SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::3 558 4.21% 94.60% # Number of insts issued each cycle 1358844SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::4 351 2.65% 97.25% # Number of insts issued each cycle 1368844SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::5 227 1.71% 98.96% # Number of insts issued each cycle 1378844SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::6 90 0.68% 99.64% # Number of insts issued each cycle 1388844SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::7 34 0.26% 99.89% # Number of insts issued each cycle 1398844SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::8 14 0.11% 100.00% # Number of insts issued each cycle 1408428SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1418428SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1428428SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1438844SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::total 13263 # Number of insts issued each cycle 1448428SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1458844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntAlu 4 2.63% 2.63% # attempts to use FU when none available 1468844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available 1478844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available 1488844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available 1498844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available 1508844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available 1518844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available 1528844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available 1538844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available 1548844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available 1558844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available 1568844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available 1578844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available 1588844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available 1598844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available 1608844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available 1618844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available 1628844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available 1638844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available 1648844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available 1658844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available 1668844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available 1678844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available 1688844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available 1698844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available 1708844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available 1718844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available 1728844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available 1738844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available 1748844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::MemRead 97 63.82% 66.45% # attempts to use FU when none available 1758844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::MemWrite 51 33.55% 100.00% # attempts to use FU when none available 1768428SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1778428SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1788241SN/Asystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 1798844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntAlu 4822 58.97% 58.97% # Type of FU issued 1808844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntMult 4 0.05% 59.02% # Type of FU issued 1818844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.04% # Type of FU issued 1828844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.07% # Type of FU issued 1838844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.07% # Type of FU issued 1848844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.07% # Type of FU issued 1858844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.07% # Type of FU issued 1868844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.07% # Type of FU issued 1878844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.07% # Type of FU issued 1888844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.07% # Type of FU issued 1898844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.07% # Type of FU issued 1908844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.07% # Type of FU issued 1918844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.07% # Type of FU issued 1928844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.07% # Type of FU issued 1938844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.07% # Type of FU issued 1948844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.07% # Type of FU issued 1958844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.07% # Type of FU issued 1968844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.07% # Type of FU issued 1978844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.07% # Type of FU issued 1988844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.07% # Type of FU issued 1998844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.07% # Type of FU issued 2008844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.07% # Type of FU issued 2018844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.07% # Type of FU issued 2028844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.07% # Type of FU issued 2038844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.07% # Type of FU issued 2048844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.07% # Type of FU issued 2058844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.07% # Type of FU issued 2068844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.07% # Type of FU issued 2078844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.07% # Type of FU issued 2088844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::MemRead 2258 27.61% 86.68% # Type of FU issued 2098844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::MemWrite 1089 13.32% 100.00% # Type of FU issued 2108241SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2118241SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 2128844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::total 8177 # Type of FU issued 2138844SAli.Saidi@ARM.comsystem.cpu.iq.rate 0.322640 # Inst issue rate 2148844SAli.Saidi@ARM.comsystem.cpu.iq.fu_busy_cnt 152 # FU busy when requested 2158844SAli.Saidi@ARM.comsystem.cpu.iq.fu_busy_rate 0.018589 # FU busy rate (busy events/executed inst) 2168844SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_reads 29803 # Number of integer instruction queue reads 2178844SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_writes 12607 # Number of integer instruction queue writes 2188844SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 7305 # Number of integer instruction queue wakeup accesses 2198428SN/Asystem.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads 2208428SN/Asystem.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 2218428SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses 2228844SAli.Saidi@ARM.comsystem.cpu.iq.int_alu_accesses 8327 # Number of integer alu accesses 2238428SN/Asystem.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses 2248844SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.forwLoads 55 # Number of loads that had data forwarded from stores 2258428SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2268844SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.squashedLoads 1332 # Number of loads squashed 2278844SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 2288844SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations 2298844SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.squashedStores 284 # Number of stores squashed 2308428SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2318428SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2328428SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 2338428SN/Asystem.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 2348428SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2358844SAli.Saidi@ARM.comsystem.cpu.iew.iewSquashCycles 840 # Number of cycles IEW is squashing 2368844SAli.Saidi@ARM.comsystem.cpu.iew.iewBlockCycles 139 # Number of cycles IEW is blocking 2378844SAli.Saidi@ARM.comsystem.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking 2388844SAli.Saidi@ARM.comsystem.cpu.iew.iewDispatchedInsts 10598 # Number of instructions dispatched to IQ 2398844SAli.Saidi@ARM.comsystem.cpu.iew.iewDispSquashedInsts 139 # Number of squashed instructions skipped by dispatch 2408844SAli.Saidi@ARM.comsystem.cpu.iew.iewDispLoadInsts 2496 # Number of dispatched load instructions 2418844SAli.Saidi@ARM.comsystem.cpu.iew.iewDispStoreInsts 1209 # Number of dispatched store instructions 2428464SN/Asystem.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions 2438844SAli.Saidi@ARM.comsystem.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall 2448464SN/Asystem.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 2458844SAli.Saidi@ARM.comsystem.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations 2468844SAli.Saidi@ARM.comsystem.cpu.iew.predictedTakenIncorrect 132 # Number of branches that were predicted taken incorrectly 2478844SAli.Saidi@ARM.comsystem.cpu.iew.predictedNotTakenIncorrect 371 # Number of branches that were predicted not taken incorrectly 2488844SAli.Saidi@ARM.comsystem.cpu.iew.branchMispredicts 503 # Number of branch mispredicts detected at execute 2498844SAli.Saidi@ARM.comsystem.cpu.iew.iewExecutedInsts 7763 # Number of executed instructions 2508844SAli.Saidi@ARM.comsystem.cpu.iew.iewExecLoadInsts 2105 # Number of load instructions executed 2518844SAli.Saidi@ARM.comsystem.cpu.iew.iewExecSquashedInsts 414 # Number of squashed instructions skipped in execute 2528428SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 2538844SAli.Saidi@ARM.comsystem.cpu.iew.exec_nop 1464 # number of nop insts executed 2548844SAli.Saidi@ARM.comsystem.cpu.iew.exec_refs 3166 # number of memory reference insts executed 2558844SAli.Saidi@ARM.comsystem.cpu.iew.exec_branches 1317 # Number of branches executed 2568844SAli.Saidi@ARM.comsystem.cpu.iew.exec_stores 1061 # Number of stores executed 2578844SAli.Saidi@ARM.comsystem.cpu.iew.exec_rate 0.306305 # Inst execution rate 2588844SAli.Saidi@ARM.comsystem.cpu.iew.wb_sent 7406 # cumulative count of insts sent to commit 2598844SAli.Saidi@ARM.comsystem.cpu.iew.wb_count 7307 # cumulative count of insts written-back 2608844SAli.Saidi@ARM.comsystem.cpu.iew.wb_producers 2841 # num instructions producing a value 2618844SAli.Saidi@ARM.comsystem.cpu.iew.wb_consumers 4060 # num instructions consuming a value 2628428SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 2638844SAli.Saidi@ARM.comsystem.cpu.iew.wb_rate 0.288313 # insts written-back per cycle 2648844SAli.Saidi@ARM.comsystem.cpu.iew.wb_fanout 0.699754 # average fanout of values written-back 2658428SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 2668428SN/Asystem.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions 2678835SAli.Saidi@ARM.comsystem.cpu.commit.commitCommittedOps 5826 # The number of committed instructions 2688844SAli.Saidi@ARM.comsystem.cpu.commit.commitSquashedInsts 4764 # The number of squashed insts skipped by commit 2698428SN/Asystem.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards 2708844SAli.Saidi@ARM.comsystem.cpu.commit.branchMispredicts 425 # The number of times a branch was mispredicted 2718844SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::samples 12423 # Number of insts commited each cycle 2728844SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::mean 0.468969 # Number of insts commited each cycle 2738844SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::stdev 1.246143 # Number of insts commited each cycle 2748428SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2758844SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::0 9990 80.42% 80.42% # Number of insts commited each cycle 2768844SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::1 1014 8.16% 88.58% # Number of insts commited each cycle 2778844SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::2 641 5.16% 93.74% # Number of insts commited each cycle 2788844SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::3 335 2.70% 96.43% # Number of insts commited each cycle 2798844SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::4 140 1.13% 97.56% # Number of insts commited each cycle 2808844SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::5 89 0.72% 98.28% # Number of insts commited each cycle 2818844SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::6 74 0.60% 98.87% # Number of insts commited each cycle 2828844SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::7 44 0.35% 99.23% # Number of insts commited each cycle 2838844SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::8 96 0.77% 100.00% # Number of insts commited each cycle 2848428SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2858428SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2868428SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 2878844SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::total 12423 # Number of insts commited each cycle 2888835SAli.Saidi@ARM.comsystem.cpu.commit.committedInsts 5826 # Number of instructions committed 2898835SAli.Saidi@ARM.comsystem.cpu.commit.committedOps 5826 # Number of ops (including micro ops) committed 2908428SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 2918428SN/Asystem.cpu.commit.refs 2089 # Number of memory references committed 2928428SN/Asystem.cpu.commit.loads 1164 # Number of loads committed 2938428SN/Asystem.cpu.commit.membars 0 # Number of memory barriers committed 2948428SN/Asystem.cpu.commit.branches 916 # Number of branches committed 2958428SN/Asystem.cpu.commit.fp_insts 2 # Number of committed floating point instructions. 2968428SN/Asystem.cpu.commit.int_insts 5124 # Number of committed integer instructions. 2978428SN/Asystem.cpu.commit.function_calls 87 # Number of function calls committed. 2988844SAli.Saidi@ARM.comsystem.cpu.commit.bw_lim_events 96 # number cycles where commit BW limit reached 2998428SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 3008844SAli.Saidi@ARM.comsystem.cpu.rob.rob_reads 22904 # The number of ROB reads 3018844SAli.Saidi@ARM.comsystem.cpu.rob.rob_writes 22029 # The number of ROB writes 3028464SN/Asystem.cpu.timesIdled 251 # Number of times that the entire CPU went into an idle state and unscheduled itself 3038844SAli.Saidi@ARM.comsystem.cpu.idleCycles 12081 # Total number of cycles that the CPU has spent unscheduled due to idling 3048428SN/Asystem.cpu.committedInsts 5169 # Number of Instructions Simulated 3058835SAli.Saidi@ARM.comsystem.cpu.committedOps 5169 # Number of Ops (including micro ops) Simulated 3068428SN/Asystem.cpu.committedInsts_total 5169 # Number of Instructions Simulated 3078844SAli.Saidi@ARM.comsystem.cpu.cpi 4.903076 # CPI: Cycles Per Instruction 3088844SAli.Saidi@ARM.comsystem.cpu.cpi_total 4.903076 # CPI: Total CPI of All Threads 3098844SAli.Saidi@ARM.comsystem.cpu.ipc 0.203954 # IPC: Instructions Per Cycle 3108844SAli.Saidi@ARM.comsystem.cpu.ipc_total 0.203954 # IPC: Total IPC of All Threads 3118844SAli.Saidi@ARM.comsystem.cpu.int_regfile_reads 10565 # number of integer regfile reads 3128844SAli.Saidi@ARM.comsystem.cpu.int_regfile_writes 5131 # number of integer regfile writes 3138428SN/Asystem.cpu.fp_regfile_reads 3 # number of floating regfile reads 3148428SN/Asystem.cpu.fp_regfile_writes 1 # number of floating regfile writes 3158844SAli.Saidi@ARM.comsystem.cpu.misc_regfile_reads 151 # number of misc regfile reads 3168844SAli.Saidi@ARM.comsystem.cpu.icache.replacements 19 # number of replacements 3178844SAli.Saidi@ARM.comsystem.cpu.icache.tagsinuse 165.584947 # Cycle average of tags in use 3188844SAli.Saidi@ARM.comsystem.cpu.icache.total_refs 1592 # Total number of references to valid blocks. 3198844SAli.Saidi@ARM.comsystem.cpu.icache.sampled_refs 344 # Sample count of references to valid blocks. 3208844SAli.Saidi@ARM.comsystem.cpu.icache.avg_refs 4.627907 # Average number of references to valid blocks. 3218428SN/Asystem.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 3228844SAli.Saidi@ARM.comsystem.cpu.icache.occ_blocks::cpu.inst 165.584947 # Average occupied blocks per requestor 3238844SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::cpu.inst 0.080852 # Average percentage of cache occupancy 3248844SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::total 0.080852 # Average percentage of cache occupancy 3258844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1592 # number of ReadReq hits 3268844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::total 1592 # number of ReadReq hits 3278844SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::cpu.inst 1592 # number of demand (read+write) hits 3288844SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::total 1592 # number of demand (read+write) hits 3298844SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::cpu.inst 1592 # number of overall hits 3308844SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::total 1592 # number of overall hits 3318844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::cpu.inst 447 # number of ReadReq misses 3328844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::total 447 # number of ReadReq misses 3338844SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::cpu.inst 447 # number of demand (read+write) misses 3348844SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::total 447 # number of demand (read+write) misses 3358844SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::cpu.inst 447 # number of overall misses 3368844SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::total 447 # number of overall misses 3378844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 15909500 # number of ReadReq miss cycles 3388844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_latency::total 15909500 # number of ReadReq miss cycles 3398844SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_latency::cpu.inst 15909500 # number of demand (read+write) miss cycles 3408844SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_latency::total 15909500 # number of demand (read+write) miss cycles 3418844SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_latency::cpu.inst 15909500 # number of overall miss cycles 3428844SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_latency::total 15909500 # number of overall miss cycles 3438844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 2039 # number of ReadReq accesses(hits+misses) 3448844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::total 2039 # number of ReadReq accesses(hits+misses) 3458844SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::cpu.inst 2039 # number of demand (read+write) accesses 3468844SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::total 2039 # number of demand (read+write) accesses 3478844SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::cpu.inst 2039 # number of overall (read+write) accesses 3488844SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::total 2039 # number of overall (read+write) accesses 3498844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.219225 # miss rate for ReadReq accesses 3509055Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_miss_rate::total 0.219225 # miss rate for ReadReq accesses 3518844SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.219225 # miss rate for demand accesses 3529055Ssaidi@eecs.umich.edusystem.cpu.icache.demand_miss_rate::total 0.219225 # miss rate for demand accesses 3538844SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.219225 # miss rate for overall accesses 3549055Ssaidi@eecs.umich.edusystem.cpu.icache.overall_miss_rate::total 0.219225 # miss rate for overall accesses 3558844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35591.722595 # average ReadReq miss latency 3569055Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_avg_miss_latency::total 35591.722595 # average ReadReq miss latency 3578844SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 35591.722595 # average overall miss latency 3589055Ssaidi@eecs.umich.edusystem.cpu.icache.demand_avg_miss_latency::total 35591.722595 # average overall miss latency 3598844SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 35591.722595 # average overall miss latency 3609055Ssaidi@eecs.umich.edusystem.cpu.icache.overall_avg_miss_latency::total 35591.722595 # average overall miss latency 3618428SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3628428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3638428SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 3648428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 3658983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3668983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3678428SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 3688428SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 3698844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 103 # number of ReadReq MSHR hits 3708844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_hits::total 103 # number of ReadReq MSHR hits 3718844SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 103 # number of demand (read+write) MSHR hits 3728844SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_hits::total 103 # number of demand (read+write) MSHR hits 3738844SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 103 # number of overall MSHR hits 3748844SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_hits::total 103 # number of overall MSHR hits 3758844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 344 # number of ReadReq MSHR misses 3768844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::total 344 # number of ReadReq MSHR misses 3778844SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses 3788844SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::total 344 # number of demand (read+write) MSHR misses 3798844SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses 3808844SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::total 344 # number of overall MSHR misses 3818844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12065000 # number of ReadReq MSHR miss cycles 3828844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 12065000 # number of ReadReq MSHR miss cycles 3838844SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 12065000 # number of demand (read+write) MSHR miss cycles 3848844SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::total 12065000 # number of demand (read+write) MSHR miss cycles 3858844SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 12065000 # number of overall MSHR miss cycles 3868844SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::total 12065000 # number of overall MSHR miss cycles 3878844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.168710 # mshr miss rate for ReadReq accesses 3889055Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.168710 # mshr miss rate for ReadReq accesses 3898844SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.168710 # mshr miss rate for demand accesses 3909055Ssaidi@eecs.umich.edusystem.cpu.icache.demand_mshr_miss_rate::total 0.168710 # mshr miss rate for demand accesses 3918844SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.168710 # mshr miss rate for overall accesses 3929055Ssaidi@eecs.umich.edusystem.cpu.icache.overall_mshr_miss_rate::total 0.168710 # mshr miss rate for overall accesses 3938844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35072.674419 # average ReadReq mshr miss latency 3949055Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35072.674419 # average ReadReq mshr miss latency 3958844SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35072.674419 # average overall mshr miss latency 3969055Ssaidi@eecs.umich.edusystem.cpu.icache.demand_avg_mshr_miss_latency::total 35072.674419 # average overall mshr miss latency 3978844SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35072.674419 # average overall mshr miss latency 3989055Ssaidi@eecs.umich.edusystem.cpu.icache.overall_avg_mshr_miss_latency::total 35072.674419 # average overall mshr miss latency 3998428SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 4008428SN/Asystem.cpu.dcache.replacements 0 # number of replacements 4018844SAli.Saidi@ARM.comsystem.cpu.dcache.tagsinuse 92.322697 # Cycle average of tags in use 4028844SAli.Saidi@ARM.comsystem.cpu.dcache.total_refs 2472 # Total number of references to valid blocks. 4038464SN/Asystem.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. 4048844SAli.Saidi@ARM.comsystem.cpu.dcache.avg_refs 17.408451 # Average number of references to valid blocks. 4058428SN/Asystem.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 4068844SAli.Saidi@ARM.comsystem.cpu.dcache.occ_blocks::cpu.data 92.322697 # Average occupied blocks per requestor 4078844SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::cpu.data 0.022540 # Average percentage of cache occupancy 4088844SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::total 0.022540 # Average percentage of cache occupancy 4098844SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1886 # number of ReadReq hits 4108844SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_hits::total 1886 # number of ReadReq hits 4118844SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::cpu.data 586 # number of WriteReq hits 4128844SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::total 586 # number of WriteReq hits 4138844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_hits::cpu.data 2472 # number of demand (read+write) hits 4148844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_hits::total 2472 # number of demand (read+write) hits 4158844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_hits::cpu.data 2472 # number of overall hits 4168844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_hits::total 2472 # number of overall hits 4178835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::cpu.data 133 # number of ReadReq misses 4188835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::total 133 # number of ReadReq misses 4198844SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::cpu.data 339 # number of WriteReq misses 4208844SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::total 339 # number of WriteReq misses 4218844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::cpu.data 472 # number of demand (read+write) misses 4228844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::total 472 # number of demand (read+write) misses 4238844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::cpu.data 472 # number of overall misses 4248844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::total 472 # number of overall misses 4258844SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 4826500 # number of ReadReq miss cycles 4268844SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_latency::total 4826500 # number of ReadReq miss cycles 4278844SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 11393500 # number of WriteReq miss cycles 4288844SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_latency::total 11393500 # number of WriteReq miss cycles 4298844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_latency::cpu.data 16220000 # number of demand (read+write) miss cycles 4308844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_latency::total 16220000 # number of demand (read+write) miss cycles 4318844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_latency::cpu.data 16220000 # number of overall miss cycles 4328844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_latency::total 16220000 # number of overall miss cycles 4338844SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 2019 # number of ReadReq accesses(hits+misses) 4348844SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_accesses::total 2019 # number of ReadReq accesses(hits+misses) 4358835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 4368835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 4378844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_accesses::cpu.data 2944 # number of demand (read+write) accesses 4388844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_accesses::total 2944 # number of demand (read+write) accesses 4398844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_accesses::cpu.data 2944 # number of overall (read+write) accesses 4408844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_accesses::total 2944 # number of overall (read+write) accesses 4418844SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065874 # miss rate for ReadReq accesses 4429055Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_miss_rate::total 0.065874 # miss rate for ReadReq accesses 4438844SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.366486 # miss rate for WriteReq accesses 4449055Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_miss_rate::total 0.366486 # miss rate for WriteReq accesses 4458844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.160326 # miss rate for demand accesses 4469055Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_miss_rate::total 0.160326 # miss rate for demand accesses 4478844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.160326 # miss rate for overall accesses 4489055Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_miss_rate::total 0.160326 # miss rate for overall accesses 4498844SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36289.473684 # average ReadReq miss latency 4509055Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_avg_miss_latency::total 36289.473684 # average ReadReq miss latency 4518844SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33609.144543 # average WriteReq miss latency 4529055Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_avg_miss_latency::total 33609.144543 # average WriteReq miss latency 4538844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 34364.406780 # average overall miss latency 4549055Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_avg_miss_latency::total 34364.406780 # average overall miss latency 4558844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 34364.406780 # average overall miss latency 4569055Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_avg_miss_latency::total 34364.406780 # average overall miss latency 4578428SN/Asystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4588428SN/Asystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4598428SN/Asystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 4608428SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 4618983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 4628983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 4638428SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 4648428SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 4658835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits 4668835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits 4678844SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 288 # number of WriteReq MSHR hits 4688844SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_hits::total 288 # number of WriteReq MSHR hits 4698844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 330 # number of demand (read+write) MSHR hits 4708844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_hits::total 330 # number of demand (read+write) MSHR hits 4718844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 330 # number of overall MSHR hits 4728844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_hits::total 330 # number of overall MSHR hits 4738835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 4748835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses 4758835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses 4768835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses 4778835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 4788835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses 4798835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 4808835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses 4818844SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3267500 # number of ReadReq MSHR miss cycles 4828844SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 3267500 # number of ReadReq MSHR miss cycles 4838844SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1845500 # number of WriteReq MSHR miss cycles 4848844SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 1845500 # number of WriteReq MSHR miss cycles 4858844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 5113000 # number of demand (read+write) MSHR miss cycles 4868844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_latency::total 5113000 # number of demand (read+write) MSHR miss cycles 4878844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 5113000 # number of overall MSHR miss cycles 4888844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_latency::total 5113000 # number of overall MSHR miss cycles 4898844SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045072 # mshr miss rate for ReadReq accesses 4909055Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045072 # mshr miss rate for ReadReq accesses 4918835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses 4929055Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses 4938844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048234 # mshr miss rate for demand accesses 4949055Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_mshr_miss_rate::total 0.048234 # mshr miss rate for demand accesses 4958844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048234 # mshr miss rate for overall accesses 4969055Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_mshr_miss_rate::total 0.048234 # mshr miss rate for overall accesses 4978844SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35906.593407 # average ReadReq mshr miss latency 4989055Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35906.593407 # average ReadReq mshr miss latency 4998844SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36186.274510 # average WriteReq mshr miss latency 5009055Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36186.274510 # average WriteReq mshr miss latency 5018844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36007.042254 # average overall mshr miss latency 5029055Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_avg_mshr_miss_latency::total 36007.042254 # average overall mshr miss latency 5038844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36007.042254 # average overall mshr miss latency 5049055Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_avg_mshr_miss_latency::total 36007.042254 # average overall mshr miss latency 5058428SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 5068428SN/Asystem.cpu.l2cache.replacements 0 # number of replacements 5078844SAli.Saidi@ARM.comsystem.cpu.l2cache.tagsinuse 226.359524 # Cycle average of tags in use 5088428SN/Asystem.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. 5098844SAli.Saidi@ARM.comsystem.cpu.l2cache.sampled_refs 432 # Sample count of references to valid blocks. 5108844SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_refs 0.006944 # Average number of references to valid blocks. 5118428SN/Asystem.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 5128844SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_blocks::cpu.inst 168.225322 # Average occupied blocks per requestor 5138844SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_blocks::cpu.data 58.134201 # Average occupied blocks per requestor 5148844SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::cpu.inst 0.005134 # Average percentage of cache occupancy 5158844SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::cpu.data 0.001774 # Average percentage of cache occupancy 5168844SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::total 0.006908 # Average percentage of cache occupancy 5178835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits 5188835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits 5198835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 5208835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 5218835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 5228835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 3 # number of overall hits 5238844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 341 # number of ReadReq misses 5248835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 91 # number of ReadReq misses 5258844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::total 432 # number of ReadReq misses 5268835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses 5278835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses 5288844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.inst 341 # number of demand (read+write) misses 5298835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses 5308844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::total 483 # number of demand (read+write) misses 5318844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.inst 341 # number of overall misses 5328835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses 5338844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::total 483 # number of overall misses 5348844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11691000 # number of ReadReq miss cycles 5358844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 3142000 # number of ReadReq miss cycles 5368844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::total 14833000 # number of ReadReq miss cycles 5378844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1769000 # number of ReadExReq miss cycles 5388844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 1769000 # number of ReadExReq miss cycles 5398844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 11691000 # number of demand (read+write) miss cycles 5408844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 4911000 # number of demand (read+write) miss cycles 5418844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::total 16602000 # number of demand (read+write) miss cycles 5428844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 11691000 # number of overall miss cycles 5438844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 4911000 # number of overall miss cycles 5448844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::total 16602000 # number of overall miss cycles 5458844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 344 # number of ReadReq accesses(hits+misses) 5468835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) 5478844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::total 435 # number of ReadReq accesses(hits+misses) 5488835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) 5498835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) 5508844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.inst 344 # number of demand (read+write) accesses 5518835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses 5528844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::total 486 # number of demand (read+write) accesses 5538844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.inst 344 # number of overall (read+write) accesses 5548835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses 5558844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses 5568844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991279 # miss rate for ReadReq accesses 5578835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 5589055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_miss_rate::total 0.993103 # miss rate for ReadReq accesses 5598835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 5609055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 5618844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.991279 # miss rate for demand accesses 5628835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 5639055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_miss_rate::total 0.993827 # miss rate for demand accesses 5648844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.991279 # miss rate for overall accesses 5658835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 5669055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_miss_rate::total 0.993827 # miss rate for overall accesses 5678844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34284.457478 # average ReadReq miss latency 5688844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34527.472527 # average ReadReq miss latency 5699055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_avg_miss_latency::total 34335.648148 # average ReadReq miss latency 5708844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34686.274510 # average ReadExReq miss latency 5719055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 34686.274510 # average ReadExReq miss latency 5728844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34284.457478 # average overall miss latency 5738844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 34584.507042 # average overall miss latency 5749055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_avg_miss_latency::total 34372.670807 # average overall miss latency 5758844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34284.457478 # average overall miss latency 5768844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 34584.507042 # average overall miss latency 5779055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_avg_miss_latency::total 34372.670807 # average overall miss latency 5788428SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5798428SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5808428SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 5818428SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 5828983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5838983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5848428SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 5858428SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 5868844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 341 # number of ReadReq MSHR misses 5878835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 5888844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 432 # number of ReadReq MSHR misses 5898835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses 5908835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses 5918844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 341 # number of demand (read+write) MSHR misses 5928835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 5938844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::total 483 # number of demand (read+write) MSHR misses 5948844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 341 # number of overall MSHR misses 5958835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 5968844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::total 483 # number of overall MSHR misses 5978844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10590500 # number of ReadReq MSHR miss cycles 5988844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2858000 # number of ReadReq MSHR miss cycles 5998844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 13448500 # number of ReadReq MSHR miss cycles 6008844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1604000 # number of ReadExReq MSHR miss cycles 6018844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1604000 # number of ReadExReq MSHR miss cycles 6028844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10590500 # number of demand (read+write) MSHR miss cycles 6038844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4462000 # number of demand (read+write) MSHR miss cycles 6048844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 15052500 # number of demand (read+write) MSHR miss cycles 6058844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10590500 # number of overall MSHR miss cycles 6068844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4462000 # number of overall MSHR miss cycles 6078844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 15052500 # number of overall MSHR miss cycles 6088844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for ReadReq accesses 6098835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 6109055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993103 # mshr miss rate for ReadReq accesses 6118835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 6129055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 6138844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for demand accesses 6148835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 6159055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_mshr_miss_rate::total 0.993827 # mshr miss rate for demand accesses 6168844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for overall accesses 6178835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 6189055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_mshr_miss_rate::total 0.993827 # mshr miss rate for overall accesses 6198844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31057.184751 # average ReadReq mshr miss latency 6208844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31406.593407 # average ReadReq mshr miss latency 6219055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31130.787037 # average ReadReq mshr miss latency 6228844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31450.980392 # average ReadExReq mshr miss latency 6239055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31450.980392 # average ReadExReq mshr miss latency 6248844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31057.184751 # average overall mshr miss latency 6258844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31422.535211 # average overall mshr miss latency 6269055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 31164.596273 # average overall mshr miss latency 6278844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31057.184751 # average overall mshr miss latency 6288844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31422.535211 # average overall mshr miss latency 6299055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 31164.596273 # average overall mshr miss latency 6308428SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 6316039SN/A 6326039SN/A---------- End Simulation Statistics ---------- 633