stats.txt revision 8517
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000012 # Number of seconds simulated 4sim_ticks 12273500 # Number of ticks simulated 5sim_freq 1000000000000 # Frequency of simulated ticks 6host_inst_rate 33014 # Simulator instruction rate (inst/s) 7host_tick_rate 78373339 # Simulator tick rate (ticks/s) 8host_mem_usage 244788 # Number of bytes of host memory used 9host_seconds 0.16 # Real time elapsed on the host 10sim_insts 5169 # Number of instructions simulated 11system.cpu.dtb.read_hits 0 # DTB read hits 12system.cpu.dtb.read_misses 0 # DTB read misses 13system.cpu.dtb.read_accesses 0 # DTB read accesses 14system.cpu.dtb.write_hits 0 # DTB write hits 15system.cpu.dtb.write_misses 0 # DTB write misses 16system.cpu.dtb.write_accesses 0 # DTB write accesses 17system.cpu.dtb.hits 0 # DTB hits 18system.cpu.dtb.misses 0 # DTB misses 19system.cpu.dtb.accesses 0 # DTB accesses 20system.cpu.itb.read_hits 0 # DTB read hits 21system.cpu.itb.read_misses 0 # DTB read misses 22system.cpu.itb.read_accesses 0 # DTB read accesses 23system.cpu.itb.write_hits 0 # DTB write hits 24system.cpu.itb.write_misses 0 # DTB write misses 25system.cpu.itb.write_accesses 0 # DTB write accesses 26system.cpu.itb.hits 0 # DTB hits 27system.cpu.itb.misses 0 # DTB misses 28system.cpu.itb.accesses 0 # DTB accesses 29system.cpu.workload.num_syscalls 8 # Number of system calls 30system.cpu.numCycles 24548 # number of cpu cycles simulated 31system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 32system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 33system.cpu.BPredUnit.lookups 1977 # Number of BP lookups 34system.cpu.BPredUnit.condPredicted 1345 # Number of conditional branches predicted 35system.cpu.BPredUnit.condIncorrect 399 # Number of conditional branches incorrect 36system.cpu.BPredUnit.BTBLookups 1580 # Number of BTB lookups 37system.cpu.BPredUnit.BTBHits 493 # Number of BTB hits 38system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 39system.cpu.BPredUnit.usedRAS 251 # Number of times the RAS was used to get a target. 40system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. 41system.cpu.fetch.icacheStallCycles 7914 # Number of cycles fetch is stalled on an Icache miss 42system.cpu.fetch.Insts 12271 # Number of instructions fetch has processed 43system.cpu.fetch.Branches 1977 # Number of branches that fetch encountered 44system.cpu.fetch.predictedBranches 744 # Number of branches that fetch has predicted taken 45system.cpu.fetch.Cycles 3026 # Number of cycles fetch has run and was not squashing or blocked 46system.cpu.fetch.SquashCycles 1189 # Number of cycles fetch has spent squashing 47system.cpu.fetch.BlockedCycles 756 # Number of cycles fetch has spent blocked 48system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 49system.cpu.fetch.PendingTrapStallCycles 145 # Number of stall cycles due to pending traps 50system.cpu.fetch.CacheLines 1783 # Number of cache lines fetched 51system.cpu.fetch.IcacheSquashes 230 # Number of outstanding Icache misses that were squashed 52system.cpu.fetch.rateDist::samples 12623 # Number of instructions fetched each cycle (Total) 53system.cpu.fetch.rateDist::mean 0.972114 # Number of instructions fetched each cycle (Total) 54system.cpu.fetch.rateDist::stdev 2.277844 # Number of instructions fetched each cycle (Total) 55system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 56system.cpu.fetch.rateDist::0 9597 76.03% 76.03% # Number of instructions fetched each cycle (Total) 57system.cpu.fetch.rateDist::1 1250 9.90% 85.93% # Number of instructions fetched each cycle (Total) 58system.cpu.fetch.rateDist::2 108 0.86% 86.79% # Number of instructions fetched each cycle (Total) 59system.cpu.fetch.rateDist::3 139 1.10% 87.89% # Number of instructions fetched each cycle (Total) 60system.cpu.fetch.rateDist::4 289 2.29% 90.18% # Number of instructions fetched each cycle (Total) 61system.cpu.fetch.rateDist::5 93 0.74% 90.91% # Number of instructions fetched each cycle (Total) 62system.cpu.fetch.rateDist::6 132 1.05% 91.96% # Number of instructions fetched each cycle (Total) 63system.cpu.fetch.rateDist::7 145 1.15% 93.11% # Number of instructions fetched each cycle (Total) 64system.cpu.fetch.rateDist::8 870 6.89% 100.00% # Number of instructions fetched each cycle (Total) 65system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 66system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 67system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 68system.cpu.fetch.rateDist::total 12623 # Number of instructions fetched each cycle (Total) 69system.cpu.fetch.branchRate 0.080536 # Number of branch fetches per cycle 70system.cpu.fetch.rate 0.499878 # Number of inst fetches per cycle 71system.cpu.decode.IdleCycles 8103 # Number of cycles decode is idle 72system.cpu.decode.BlockedCycles 871 # Number of cycles decode is blocked 73system.cpu.decode.RunCycles 2859 # Number of cycles decode is running 74system.cpu.decode.UnblockCycles 51 # Number of cycles decode is unblocking 75system.cpu.decode.SquashCycles 739 # Number of cycles decode is squashing 76system.cpu.decode.BranchResolved 107 # Number of times decode resolved a branch 77system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction 78system.cpu.decode.DecodedInsts 11438 # Number of instructions handled by decode 79system.cpu.decode.SquashedInsts 162 # Number of squashed instructions handled by decode 80system.cpu.rename.SquashCycles 739 # Number of cycles rename is squashing 81system.cpu.rename.IdleCycles 8274 # Number of cycles rename is idle 82system.cpu.rename.BlockCycles 258 # Number of cycles rename is blocking 83system.cpu.rename.serializeStallCycles 499 # count of cycles rename stalled for serializing inst 84system.cpu.rename.RunCycles 2742 # Number of cycles rename is running 85system.cpu.rename.UnblockCycles 111 # Number of cycles rename is unblocking 86system.cpu.rename.RenamedInsts 11017 # Number of instructions processed by rename 87system.cpu.rename.LSQFullEvents 101 # Number of times rename has blocked due to LSQ full 88system.cpu.rename.RenamedOperands 6705 # Number of destination operands rename has renamed 89system.cpu.rename.RenameLookups 13125 # Number of register rename lookups that rename has made 90system.cpu.rename.int_rename_lookups 13120 # Number of integer rename lookups 91system.cpu.rename.fp_rename_lookups 5 # Number of floating rename lookups 92system.cpu.rename.CommittedMaps 3410 # Number of HB maps that are committed 93system.cpu.rename.UndoneMaps 3295 # Number of HB maps that are undone due to squashing 94system.cpu.rename.serializingInsts 18 # count of serializing insts renamed 95system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed 96system.cpu.rename.skidInsts 281 # count of insts added to the skid buffer 97system.cpu.memDep0.insertedLoads 2349 # Number of loads inserted to the mem dependence unit. 98system.cpu.memDep0.insertedStores 1175 # Number of stores inserted to the mem dependence unit. 99system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 100system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. 101system.cpu.iq.iqInstsAdded 8651 # Number of instructions added to the IQ (excludes non-spec) 102system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ 103system.cpu.iq.iqInstsIssued 7822 # Number of instructions issued 104system.cpu.iq.iqSquashedInstsIssued 50 # Number of squashed instructions issued 105system.cpu.iq.iqSquashedInstsExamined 2995 # Number of squashed instructions iterated over during squash; mainly for profiling 106system.cpu.iq.iqSquashedOperandsExamined 1815 # Number of squashed operands that are examined and possibly removed from graph 107system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed 108system.cpu.iq.issued_per_cycle::samples 12623 # Number of insts issued each cycle 109system.cpu.iq.issued_per_cycle::mean 0.619663 # Number of insts issued each cycle 110system.cpu.iq.issued_per_cycle::stdev 1.285161 # Number of insts issued each cycle 111system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 112system.cpu.iq.issued_per_cycle::0 9267 73.41% 73.41% # Number of insts issued each cycle 113system.cpu.iq.issued_per_cycle::1 1321 10.47% 83.88% # Number of insts issued each cycle 114system.cpu.iq.issued_per_cycle::2 831 6.58% 90.46% # Number of insts issued each cycle 115system.cpu.iq.issued_per_cycle::3 511 4.05% 94.51% # Number of insts issued each cycle 116system.cpu.iq.issued_per_cycle::4 357 2.83% 97.34% # Number of insts issued each cycle 117system.cpu.iq.issued_per_cycle::5 203 1.61% 98.95% # Number of insts issued each cycle 118system.cpu.iq.issued_per_cycle::6 83 0.66% 99.60% # Number of insts issued each cycle 119system.cpu.iq.issued_per_cycle::7 35 0.28% 99.88% # Number of insts issued each cycle 120system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle 121system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 122system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 123system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 124system.cpu.iq.issued_per_cycle::total 12623 # Number of insts issued each cycle 125system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 126system.cpu.iq.fu_full::IntAlu 3 2.05% 2.05% # attempts to use FU when none available 127system.cpu.iq.fu_full::IntMult 0 0.00% 2.05% # attempts to use FU when none available 128system.cpu.iq.fu_full::IntDiv 0 0.00% 2.05% # attempts to use FU when none available 129system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.05% # attempts to use FU when none available 130system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.05% # attempts to use FU when none available 131system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.05% # attempts to use FU when none available 132system.cpu.iq.fu_full::FloatMult 0 0.00% 2.05% # attempts to use FU when none available 133system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.05% # attempts to use FU when none available 134system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.05% # attempts to use FU when none available 135system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.05% # attempts to use FU when none available 136system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.05% # attempts to use FU when none available 137system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.05% # attempts to use FU when none available 138system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.05% # attempts to use FU when none available 139system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.05% # attempts to use FU when none available 140system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.05% # attempts to use FU when none available 141system.cpu.iq.fu_full::SimdMult 0 0.00% 2.05% # attempts to use FU when none available 142system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.05% # attempts to use FU when none available 143system.cpu.iq.fu_full::SimdShift 0 0.00% 2.05% # attempts to use FU when none available 144system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.05% # attempts to use FU when none available 145system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.05% # attempts to use FU when none available 146system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.05% # attempts to use FU when none available 147system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.05% # attempts to use FU when none available 148system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.05% # attempts to use FU when none available 149system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.05% # attempts to use FU when none available 150system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.05% # attempts to use FU when none available 151system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.05% # attempts to use FU when none available 152system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.05% # attempts to use FU when none available 153system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.05% # attempts to use FU when none available 154system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.05% # attempts to use FU when none available 155system.cpu.iq.fu_full::MemRead 91 62.33% 64.38% # attempts to use FU when none available 156system.cpu.iq.fu_full::MemWrite 52 35.62% 100.00% # attempts to use FU when none available 157system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 158system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 159system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 160system.cpu.iq.FU_type_0::IntAlu 4598 58.78% 58.78% # Type of FU issued 161system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.83% # Type of FU issued 162system.cpu.iq.FU_type_0::IntDiv 2 0.03% 58.86% # Type of FU issued 163system.cpu.iq.FU_type_0::FloatAdd 2 0.03% 58.89% # Type of FU issued 164system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.89% # Type of FU issued 165system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.89% # Type of FU issued 166system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.89% # Type of FU issued 167system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.89% # Type of FU issued 168system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.89% # Type of FU issued 169system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.89% # Type of FU issued 170system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.89% # Type of FU issued 171system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.89% # Type of FU issued 172system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.89% # Type of FU issued 173system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.89% # Type of FU issued 174system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.89% # Type of FU issued 175system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.89% # Type of FU issued 176system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.89% # Type of FU issued 177system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.89% # Type of FU issued 178system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.89% # Type of FU issued 179system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.89% # Type of FU issued 180system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.89% # Type of FU issued 181system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.89% # Type of FU issued 182system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.89% # Type of FU issued 183system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.89% # Type of FU issued 184system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.89% # Type of FU issued 185system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.89% # Type of FU issued 186system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.89% # Type of FU issued 187system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.89% # Type of FU issued 188system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.89% # Type of FU issued 189system.cpu.iq.FU_type_0::MemRead 2131 27.24% 86.13% # Type of FU issued 190system.cpu.iq.FU_type_0::MemWrite 1085 13.87% 100.00% # Type of FU issued 191system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 192system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 193system.cpu.iq.FU_type_0::total 7822 # Type of FU issued 194system.cpu.iq.rate 0.318641 # Inst issue rate 195system.cpu.iq.fu_busy_cnt 146 # FU busy when requested 196system.cpu.iq.fu_busy_rate 0.018665 # FU busy rate (busy events/executed inst) 197system.cpu.iq.int_inst_queue_reads 28459 # Number of integer instruction queue reads 198system.cpu.iq.int_inst_queue_writes 11666 # Number of integer instruction queue writes 199system.cpu.iq.int_inst_queue_wakeup_accesses 7121 # Number of integer instruction queue wakeup accesses 200system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads 201system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 202system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses 203system.cpu.iq.int_alu_accesses 7966 # Number of integer alu accesses 204system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses 205system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores 206system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 207system.cpu.iew.lsq.thread0.squashedLoads 1185 # Number of loads squashed 208system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed 209system.cpu.iew.lsq.thread0.memOrderViolation 9 # Number of memory ordering violations 210system.cpu.iew.lsq.thread0.squashedStores 250 # Number of stores squashed 211system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 212system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 213system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 214system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 215system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 216system.cpu.iew.iewSquashCycles 739 # Number of cycles IEW is squashing 217system.cpu.iew.iewBlockCycles 165 # Number of cycles IEW is blocking 218system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking 219system.cpu.iew.iewDispatchedInsts 10044 # Number of instructions dispatched to IQ 220system.cpu.iew.iewDispSquashedInsts 128 # Number of squashed instructions skipped by dispatch 221system.cpu.iew.iewDispLoadInsts 2349 # Number of dispatched load instructions 222system.cpu.iew.iewDispStoreInsts 1175 # Number of dispatched store instructions 223system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions 224system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall 225system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 226system.cpu.iew.memOrderViolationEvents 9 # Number of memory order violations 227system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly 228system.cpu.iew.predictedNotTakenIncorrect 309 # Number of branches that were predicted not taken incorrectly 229system.cpu.iew.branchMispredicts 416 # Number of branch mispredicts detected at execute 230system.cpu.iew.iewExecutedInsts 7537 # Number of executed instructions 231system.cpu.iew.iewExecLoadInsts 2031 # Number of load instructions executed 232system.cpu.iew.iewExecSquashedInsts 285 # Number of squashed instructions skipped in execute 233system.cpu.iew.exec_swp 0 # number of swp insts executed 234system.cpu.iew.exec_nop 1380 # number of nop insts executed 235system.cpu.iew.exec_refs 3091 # number of memory reference insts executed 236system.cpu.iew.exec_branches 1271 # Number of branches executed 237system.cpu.iew.exec_stores 1060 # Number of stores executed 238system.cpu.iew.exec_rate 0.307031 # Inst execution rate 239system.cpu.iew.wb_sent 7215 # cumulative count of insts sent to commit 240system.cpu.iew.wb_count 7123 # cumulative count of insts written-back 241system.cpu.iew.wb_producers 2761 # num instructions producing a value 242system.cpu.iew.wb_consumers 3949 # num instructions consuming a value 243system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 244system.cpu.iew.wb_rate 0.290166 # insts written-back per cycle 245system.cpu.iew.wb_fanout 0.699164 # average fanout of values written-back 246system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 247system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions 248system.cpu.commit.commitSquashedInsts 4210 # The number of squashed insts skipped by commit 249system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards 250system.cpu.commit.branchMispredicts 357 # The number of times a branch was mispredicted 251system.cpu.commit.committed_per_cycle::samples 11884 # Number of insts commited each cycle 252system.cpu.commit.committed_per_cycle::mean 0.490239 # Number of insts commited each cycle 253system.cpu.commit.committed_per_cycle::stdev 1.276602 # Number of insts commited each cycle 254system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 255system.cpu.commit.committed_per_cycle::0 9485 79.81% 79.81% # Number of insts commited each cycle 256system.cpu.commit.committed_per_cycle::1 966 8.13% 87.94% # Number of insts commited each cycle 257system.cpu.commit.committed_per_cycle::2 656 5.52% 93.46% # Number of insts commited each cycle 258system.cpu.commit.committed_per_cycle::3 321 2.70% 96.16% # Number of insts commited each cycle 259system.cpu.commit.committed_per_cycle::4 147 1.24% 97.40% # Number of insts commited each cycle 260system.cpu.commit.committed_per_cycle::5 102 0.86% 98.26% # Number of insts commited each cycle 261system.cpu.commit.committed_per_cycle::6 64 0.54% 98.80% # Number of insts commited each cycle 262system.cpu.commit.committed_per_cycle::7 41 0.35% 99.14% # Number of insts commited each cycle 263system.cpu.commit.committed_per_cycle::8 102 0.86% 100.00% # Number of insts commited each cycle 264system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 265system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 266system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 267system.cpu.commit.committed_per_cycle::total 11884 # Number of insts commited each cycle 268system.cpu.commit.count 5826 # Number of instructions committed 269system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 270system.cpu.commit.refs 2089 # Number of memory references committed 271system.cpu.commit.loads 1164 # Number of loads committed 272system.cpu.commit.membars 0 # Number of memory barriers committed 273system.cpu.commit.branches 916 # Number of branches committed 274system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. 275system.cpu.commit.int_insts 5124 # Number of committed integer instructions. 276system.cpu.commit.function_calls 87 # Number of function calls committed. 277system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached 278system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 279system.cpu.rob.rob_reads 21805 # The number of ROB reads 280system.cpu.rob.rob_writes 20822 # The number of ROB writes 281system.cpu.timesIdled 251 # Number of times that the entire CPU went into an idle state and unscheduled itself 282system.cpu.idleCycles 11925 # Total number of cycles that the CPU has spent unscheduled due to idling 283system.cpu.committedInsts 5169 # Number of Instructions Simulated 284system.cpu.committedInsts_total 5169 # Number of Instructions Simulated 285system.cpu.cpi 4.749081 # CPI: Cycles Per Instruction 286system.cpu.cpi_total 4.749081 # CPI: Total CPI of All Threads 287system.cpu.ipc 0.210567 # IPC: Instructions Per Cycle 288system.cpu.ipc_total 0.210567 # IPC: Total IPC of All Threads 289system.cpu.int_regfile_reads 10287 # number of integer regfile reads 290system.cpu.int_regfile_writes 4991 # number of integer regfile writes 291system.cpu.fp_regfile_reads 3 # number of floating regfile reads 292system.cpu.fp_regfile_writes 1 # number of floating regfile writes 293system.cpu.misc_regfile_reads 154 # number of misc regfile reads 294system.cpu.icache.replacements 17 # number of replacements 295system.cpu.icache.tagsinuse 161.223747 # Cycle average of tags in use 296system.cpu.icache.total_refs 1364 # Total number of references to valid blocks. 297system.cpu.icache.sampled_refs 336 # Sample count of references to valid blocks. 298system.cpu.icache.avg_refs 4.059524 # Average number of references to valid blocks. 299system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 300system.cpu.icache.occ_blocks::0 161.223747 # Average occupied blocks per context 301system.cpu.icache.occ_percent::0 0.078723 # Average percentage of cache occupancy 302system.cpu.icache.ReadReq_hits 1364 # number of ReadReq hits 303system.cpu.icache.demand_hits 1364 # number of demand (read+write) hits 304system.cpu.icache.overall_hits 1364 # number of overall hits 305system.cpu.icache.ReadReq_misses 419 # number of ReadReq misses 306system.cpu.icache.demand_misses 419 # number of demand (read+write) misses 307system.cpu.icache.overall_misses 419 # number of overall misses 308system.cpu.icache.ReadReq_miss_latency 15179500 # number of ReadReq miss cycles 309system.cpu.icache.demand_miss_latency 15179500 # number of demand (read+write) miss cycles 310system.cpu.icache.overall_miss_latency 15179500 # number of overall miss cycles 311system.cpu.icache.ReadReq_accesses 1783 # number of ReadReq accesses(hits+misses) 312system.cpu.icache.demand_accesses 1783 # number of demand (read+write) accesses 313system.cpu.icache.overall_accesses 1783 # number of overall (read+write) accesses 314system.cpu.icache.ReadReq_miss_rate 0.234997 # miss rate for ReadReq accesses 315system.cpu.icache.demand_miss_rate 0.234997 # miss rate for demand accesses 316system.cpu.icache.overall_miss_rate 0.234997 # miss rate for overall accesses 317system.cpu.icache.ReadReq_avg_miss_latency 36227.923628 # average ReadReq miss latency 318system.cpu.icache.demand_avg_miss_latency 36227.923628 # average overall miss latency 319system.cpu.icache.overall_avg_miss_latency 36227.923628 # average overall miss latency 320system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 321system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 322system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 323system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 324system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 325system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 326system.cpu.icache.fast_writes 0 # number of fast writes performed 327system.cpu.icache.cache_copies 0 # number of cache copies performed 328system.cpu.icache.writebacks 0 # number of writebacks 329system.cpu.icache.ReadReq_mshr_hits 83 # number of ReadReq MSHR hits 330system.cpu.icache.demand_mshr_hits 83 # number of demand (read+write) MSHR hits 331system.cpu.icache.overall_mshr_hits 83 # number of overall MSHR hits 332system.cpu.icache.ReadReq_mshr_misses 336 # number of ReadReq MSHR misses 333system.cpu.icache.demand_mshr_misses 336 # number of demand (read+write) MSHR misses 334system.cpu.icache.overall_mshr_misses 336 # number of overall MSHR misses 335system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 336system.cpu.icache.ReadReq_mshr_miss_latency 11784000 # number of ReadReq MSHR miss cycles 337system.cpu.icache.demand_mshr_miss_latency 11784000 # number of demand (read+write) MSHR miss cycles 338system.cpu.icache.overall_mshr_miss_latency 11784000 # number of overall MSHR miss cycles 339system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 340system.cpu.icache.ReadReq_mshr_miss_rate 0.188446 # mshr miss rate for ReadReq accesses 341system.cpu.icache.demand_mshr_miss_rate 0.188446 # mshr miss rate for demand accesses 342system.cpu.icache.overall_mshr_miss_rate 0.188446 # mshr miss rate for overall accesses 343system.cpu.icache.ReadReq_avg_mshr_miss_latency 35071.428571 # average ReadReq mshr miss latency 344system.cpu.icache.demand_avg_mshr_miss_latency 35071.428571 # average overall mshr miss latency 345system.cpu.icache.overall_avg_mshr_miss_latency 35071.428571 # average overall mshr miss latency 346system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 347system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 348system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 349system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 350system.cpu.dcache.replacements 0 # number of replacements 351system.cpu.dcache.tagsinuse 92.122056 # Cycle average of tags in use 352system.cpu.dcache.total_refs 2382 # Total number of references to valid blocks. 353system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. 354system.cpu.dcache.avg_refs 16.774648 # Average number of references to valid blocks. 355system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 356system.cpu.dcache.occ_blocks::0 92.122056 # Average occupied blocks per context 357system.cpu.dcache.occ_percent::0 0.022491 # Average percentage of cache occupancy 358system.cpu.dcache.ReadReq_hits 1804 # number of ReadReq hits 359system.cpu.dcache.WriteReq_hits 578 # number of WriteReq hits 360system.cpu.dcache.demand_hits 2382 # number of demand (read+write) hits 361system.cpu.dcache.overall_hits 2382 # number of overall hits 362system.cpu.dcache.ReadReq_misses 134 # number of ReadReq misses 363system.cpu.dcache.WriteReq_misses 347 # number of WriteReq misses 364system.cpu.dcache.demand_misses 481 # number of demand (read+write) misses 365system.cpu.dcache.overall_misses 481 # number of overall misses 366system.cpu.dcache.ReadReq_miss_latency 4801000 # number of ReadReq miss cycles 367system.cpu.dcache.WriteReq_miss_latency 11505500 # number of WriteReq miss cycles 368system.cpu.dcache.demand_miss_latency 16306500 # number of demand (read+write) miss cycles 369system.cpu.dcache.overall_miss_latency 16306500 # number of overall miss cycles 370system.cpu.dcache.ReadReq_accesses 1938 # number of ReadReq accesses(hits+misses) 371system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) 372system.cpu.dcache.demand_accesses 2863 # number of demand (read+write) accesses 373system.cpu.dcache.overall_accesses 2863 # number of overall (read+write) accesses 374system.cpu.dcache.ReadReq_miss_rate 0.069143 # miss rate for ReadReq accesses 375system.cpu.dcache.WriteReq_miss_rate 0.375135 # miss rate for WriteReq accesses 376system.cpu.dcache.demand_miss_rate 0.168006 # miss rate for demand accesses 377system.cpu.dcache.overall_miss_rate 0.168006 # miss rate for overall accesses 378system.cpu.dcache.ReadReq_avg_miss_latency 35828.358209 # average ReadReq miss latency 379system.cpu.dcache.WriteReq_avg_miss_latency 33157.060519 # average WriteReq miss latency 380system.cpu.dcache.demand_avg_miss_latency 33901.247401 # average overall miss latency 381system.cpu.dcache.overall_avg_miss_latency 33901.247401 # average overall miss latency 382system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 383system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 384system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 385system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 386system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 387system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 388system.cpu.dcache.fast_writes 0 # number of fast writes performed 389system.cpu.dcache.cache_copies 0 # number of cache copies performed 390system.cpu.dcache.writebacks 0 # number of writebacks 391system.cpu.dcache.ReadReq_mshr_hits 43 # number of ReadReq MSHR hits 392system.cpu.dcache.WriteReq_mshr_hits 296 # number of WriteReq MSHR hits 393system.cpu.dcache.demand_mshr_hits 339 # number of demand (read+write) MSHR hits 394system.cpu.dcache.overall_mshr_hits 339 # number of overall MSHR hits 395system.cpu.dcache.ReadReq_mshr_misses 91 # number of ReadReq MSHR misses 396system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses 397system.cpu.dcache.demand_mshr_misses 142 # number of demand (read+write) MSHR misses 398system.cpu.dcache.overall_mshr_misses 142 # number of overall MSHR misses 399system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 400system.cpu.dcache.ReadReq_mshr_miss_latency 3272000 # number of ReadReq MSHR miss cycles 401system.cpu.dcache.WriteReq_mshr_miss_latency 1835500 # number of WriteReq MSHR miss cycles 402system.cpu.dcache.demand_mshr_miss_latency 5107500 # number of demand (read+write) MSHR miss cycles 403system.cpu.dcache.overall_mshr_miss_latency 5107500 # number of overall MSHR miss cycles 404system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 405system.cpu.dcache.ReadReq_mshr_miss_rate 0.046956 # mshr miss rate for ReadReq accesses 406system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses 407system.cpu.dcache.demand_mshr_miss_rate 0.049598 # mshr miss rate for demand accesses 408system.cpu.dcache.overall_mshr_miss_rate 0.049598 # mshr miss rate for overall accesses 409system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35956.043956 # average ReadReq mshr miss latency 410system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35990.196078 # average WriteReq mshr miss latency 411system.cpu.dcache.demand_avg_mshr_miss_latency 35968.309859 # average overall mshr miss latency 412system.cpu.dcache.overall_avg_mshr_miss_latency 35968.309859 # average overall mshr miss latency 413system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 414system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 415system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 416system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 417system.cpu.l2cache.replacements 0 # number of replacements 418system.cpu.l2cache.tagsinuse 221.520650 # Cycle average of tags in use 419system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. 420system.cpu.l2cache.sampled_refs 424 # Sample count of references to valid blocks. 421system.cpu.l2cache.avg_refs 0.007075 # Average number of references to valid blocks. 422system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 423system.cpu.l2cache.occ_blocks::0 221.520650 # Average occupied blocks per context 424system.cpu.l2cache.occ_percent::0 0.006760 # Average percentage of cache occupancy 425system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits 426system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits 427system.cpu.l2cache.overall_hits 3 # number of overall hits 428system.cpu.l2cache.ReadReq_misses 424 # number of ReadReq misses 429system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses 430system.cpu.l2cache.demand_misses 475 # number of demand (read+write) misses 431system.cpu.l2cache.overall_misses 475 # number of overall misses 432system.cpu.l2cache.ReadReq_miss_latency 14561500 # number of ReadReq miss cycles 433system.cpu.l2cache.ReadExReq_miss_latency 1760000 # number of ReadExReq miss cycles 434system.cpu.l2cache.demand_miss_latency 16321500 # number of demand (read+write) miss cycles 435system.cpu.l2cache.overall_miss_latency 16321500 # number of overall miss cycles 436system.cpu.l2cache.ReadReq_accesses 427 # number of ReadReq accesses(hits+misses) 437system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses) 438system.cpu.l2cache.demand_accesses 478 # number of demand (read+write) accesses 439system.cpu.l2cache.overall_accesses 478 # number of overall (read+write) accesses 440system.cpu.l2cache.ReadReq_miss_rate 0.992974 # miss rate for ReadReq accesses 441system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses 442system.cpu.l2cache.demand_miss_rate 0.993724 # miss rate for demand accesses 443system.cpu.l2cache.overall_miss_rate 0.993724 # miss rate for overall accesses 444system.cpu.l2cache.ReadReq_avg_miss_latency 34343.160377 # average ReadReq miss latency 445system.cpu.l2cache.ReadExReq_avg_miss_latency 34509.803922 # average ReadExReq miss latency 446system.cpu.l2cache.demand_avg_miss_latency 34361.052632 # average overall miss latency 447system.cpu.l2cache.overall_avg_miss_latency 34361.052632 # average overall miss latency 448system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 449system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 450system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 451system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 452system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 453system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 454system.cpu.l2cache.fast_writes 0 # number of fast writes performed 455system.cpu.l2cache.cache_copies 0 # number of cache copies performed 456system.cpu.l2cache.writebacks 0 # number of writebacks 457system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 458system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits 459system.cpu.l2cache.ReadReq_mshr_misses 424 # number of ReadReq MSHR misses 460system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses 461system.cpu.l2cache.demand_mshr_misses 475 # number of demand (read+write) MSHR misses 462system.cpu.l2cache.overall_mshr_misses 475 # number of overall MSHR misses 463system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 464system.cpu.l2cache.ReadReq_mshr_miss_latency 13198000 # number of ReadReq MSHR miss cycles 465system.cpu.l2cache.ReadExReq_mshr_miss_latency 1598500 # number of ReadExReq MSHR miss cycles 466system.cpu.l2cache.demand_mshr_miss_latency 14796500 # number of demand (read+write) MSHR miss cycles 467system.cpu.l2cache.overall_mshr_miss_latency 14796500 # number of overall MSHR miss cycles 468system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 469system.cpu.l2cache.ReadReq_mshr_miss_rate 0.992974 # mshr miss rate for ReadReq accesses 470system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses 471system.cpu.l2cache.demand_mshr_miss_rate 0.993724 # mshr miss rate for demand accesses 472system.cpu.l2cache.overall_mshr_miss_rate 0.993724 # mshr miss rate for overall accesses 473system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31127.358491 # average ReadReq mshr miss latency 474system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31343.137255 # average ReadExReq mshr miss latency 475system.cpu.l2cache.demand_avg_mshr_miss_latency 31150.526316 # average overall mshr miss latency 476system.cpu.l2cache.overall_avg_mshr_miss_latency 31150.526316 # average overall mshr miss latency 477system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 478system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 479system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 480system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 481 482---------- End Simulation Statistics ---------- 483