stats.txt revision 8241
1 2---------- Begin Simulation Statistics ---------- 3host_inst_rate 109180 # Simulator instruction rate (inst/s) 4host_mem_usage 204504 # Number of bytes of host memory used 5host_seconds 0.05 # Real time elapsed on the host 6host_tick_rate 269299917 # Simulator tick rate (ticks/s) 7sim_freq 1000000000000 # Frequency of simulated ticks 8sim_insts 5169 # Number of instructions simulated 9sim_seconds 0.000013 # Number of seconds simulated 10sim_ticks 12793500 # Number of ticks simulated 11system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 12system.cpu.BPredUnit.BTBHits 531 # Number of BTB hits 13system.cpu.BPredUnit.BTBLookups 1503 # Number of BTB lookups 14system.cpu.BPredUnit.RASInCorrect 66 # Number of incorrect RAS predictions. 15system.cpu.BPredUnit.condIncorrect 380 # Number of conditional branches incorrect 16system.cpu.BPredUnit.condPredicted 1180 # Number of conditional branches predicted 17system.cpu.BPredUnit.lookups 1716 # Number of BP lookups 18system.cpu.BPredUnit.usedRAS 206 # Number of times the RAS was used to get a target. 19system.cpu.commit.branchMispredicts 339 # The number of times a branch was mispredicted 20system.cpu.commit.branches 916 # Number of branches committed 21system.cpu.commit.bw_lim_events 77 # number cycles where commit BW limit reached 22system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 23system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions 24system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards 25system.cpu.commit.commitSquashedInsts 3363 # The number of squashed insts skipped by commit 26system.cpu.commit.committed_per_cycle::samples 12220 # Number of insts commited each cycle 27system.cpu.commit.committed_per_cycle::mean 0.476759 # Number of insts commited each cycle 28system.cpu.commit.committed_per_cycle::stdev 1.219720 # Number of insts commited each cycle 29system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 30system.cpu.commit.committed_per_cycle::0 9742 79.72% 79.72% # Number of insts commited each cycle 31system.cpu.commit.committed_per_cycle::1 995 8.14% 87.86% # Number of insts commited each cycle 32system.cpu.commit.committed_per_cycle::2 703 5.75% 93.62% # Number of insts commited each cycle 33system.cpu.commit.committed_per_cycle::3 335 2.74% 96.36% # Number of insts commited each cycle 34system.cpu.commit.committed_per_cycle::4 169 1.38% 97.74% # Number of insts commited each cycle 35system.cpu.commit.committed_per_cycle::5 98 0.80% 98.54% # Number of insts commited each cycle 36system.cpu.commit.committed_per_cycle::6 69 0.56% 99.11% # Number of insts commited each cycle 37system.cpu.commit.committed_per_cycle::7 32 0.26% 99.37% # Number of insts commited each cycle 38system.cpu.commit.committed_per_cycle::8 77 0.63% 100.00% # Number of insts commited each cycle 39system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 40system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 41system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 42system.cpu.commit.committed_per_cycle::total 12220 # Number of insts commited each cycle 43system.cpu.commit.count 5826 # Number of instructions committed 44system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. 45system.cpu.commit.function_calls 87 # Number of function calls committed. 46system.cpu.commit.int_insts 5124 # Number of committed integer instructions. 47system.cpu.commit.loads 1164 # Number of loads committed 48system.cpu.commit.membars 0 # Number of memory barriers committed 49system.cpu.commit.refs 2089 # Number of memory references committed 50system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 51system.cpu.committedInsts 5169 # Number of Instructions Simulated 52system.cpu.committedInsts_total 5169 # Number of Instructions Simulated 53system.cpu.cpi 4.950281 # CPI: Cycles Per Instruction 54system.cpu.cpi_total 4.950281 # CPI: Total CPI of All Threads 55system.cpu.dcache.ReadReq_accesses 1798 # number of ReadReq accesses(hits+misses) 56system.cpu.dcache.ReadReq_avg_miss_latency 36128.906250 # average ReadReq miss latency 57system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35938.888889 # average ReadReq mshr miss latency 58system.cpu.dcache.ReadReq_hits 1670 # number of ReadReq hits 59system.cpu.dcache.ReadReq_miss_latency 4624500 # number of ReadReq miss cycles 60system.cpu.dcache.ReadReq_miss_rate 0.071190 # miss rate for ReadReq accesses 61system.cpu.dcache.ReadReq_misses 128 # number of ReadReq misses 62system.cpu.dcache.ReadReq_mshr_hits 38 # number of ReadReq MSHR hits 63system.cpu.dcache.ReadReq_mshr_miss_latency 3234500 # number of ReadReq MSHR miss cycles 64system.cpu.dcache.ReadReq_mshr_miss_rate 0.050056 # mshr miss rate for ReadReq accesses 65system.cpu.dcache.ReadReq_mshr_misses 90 # number of ReadReq MSHR misses 66system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) 67system.cpu.dcache.WriteReq_avg_miss_latency 34186.416185 # average WriteReq miss latency 68system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36205.882353 # average WriteReq mshr miss latency 69system.cpu.dcache.WriteReq_hits 579 # number of WriteReq hits 70system.cpu.dcache.WriteReq_miss_latency 11828500 # number of WriteReq miss cycles 71system.cpu.dcache.WriteReq_miss_rate 0.374054 # miss rate for WriteReq accesses 72system.cpu.dcache.WriteReq_misses 346 # number of WriteReq misses 73system.cpu.dcache.WriteReq_mshr_hits 295 # number of WriteReq MSHR hits 74system.cpu.dcache.WriteReq_mshr_miss_latency 1846500 # number of WriteReq MSHR miss cycles 75system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses 76system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses 77system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 78system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 79system.cpu.dcache.avg_refs 15.950355 # Average number of references to valid blocks. 80system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 81system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 82system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 83system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 84system.cpu.dcache.cache_copies 0 # number of cache copies performed 85system.cpu.dcache.demand_accesses 2723 # number of demand (read+write) accesses 86system.cpu.dcache.demand_avg_miss_latency 34710.970464 # average overall miss latency 87system.cpu.dcache.demand_avg_mshr_miss_latency 36035.460993 # average overall mshr miss latency 88system.cpu.dcache.demand_hits 2249 # number of demand (read+write) hits 89system.cpu.dcache.demand_miss_latency 16453000 # number of demand (read+write) miss cycles 90system.cpu.dcache.demand_miss_rate 0.174073 # miss rate for demand accesses 91system.cpu.dcache.demand_misses 474 # number of demand (read+write) misses 92system.cpu.dcache.demand_mshr_hits 333 # number of demand (read+write) MSHR hits 93system.cpu.dcache.demand_mshr_miss_latency 5081000 # number of demand (read+write) MSHR miss cycles 94system.cpu.dcache.demand_mshr_miss_rate 0.051781 # mshr miss rate for demand accesses 95system.cpu.dcache.demand_mshr_misses 141 # number of demand (read+write) MSHR misses 96system.cpu.dcache.fast_writes 0 # number of fast writes performed 97system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 98system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 99system.cpu.dcache.occ_blocks::0 91.720291 # Average occupied blocks per context 100system.cpu.dcache.occ_percent::0 0.022393 # Average percentage of cache occupancy 101system.cpu.dcache.overall_accesses 2723 # number of overall (read+write) accesses 102system.cpu.dcache.overall_avg_miss_latency 34710.970464 # average overall miss latency 103system.cpu.dcache.overall_avg_mshr_miss_latency 36035.460993 # average overall mshr miss latency 104system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 105system.cpu.dcache.overall_hits 2249 # number of overall hits 106system.cpu.dcache.overall_miss_latency 16453000 # number of overall miss cycles 107system.cpu.dcache.overall_miss_rate 0.174073 # miss rate for overall accesses 108system.cpu.dcache.overall_misses 474 # number of overall misses 109system.cpu.dcache.overall_mshr_hits 333 # number of overall MSHR hits 110system.cpu.dcache.overall_mshr_miss_latency 5081000 # number of overall MSHR miss cycles 111system.cpu.dcache.overall_mshr_miss_rate 0.051781 # mshr miss rate for overall accesses 112system.cpu.dcache.overall_mshr_misses 141 # number of overall MSHR misses 113system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 114system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 115system.cpu.dcache.replacements 0 # number of replacements 116system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. 117system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 118system.cpu.dcache.tagsinuse 91.720291 # Cycle average of tags in use 119system.cpu.dcache.total_refs 2249 # Total number of references to valid blocks. 120system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 121system.cpu.dcache.writebacks 0 # number of writebacks 122system.cpu.decode.BlockedCycles 742 # Number of cycles decode is blocked 123system.cpu.decode.BranchMispred 42 # Number of times decode detected a branch misprediction 124system.cpu.decode.BranchResolved 89 # Number of times decode resolved a branch 125system.cpu.decode.DecodedInsts 10279 # Number of instructions handled by decode 126system.cpu.decode.IdleCycles 8753 # Number of cycles decode is idle 127system.cpu.decode.RunCycles 2688 # Number of cycles decode is running 128system.cpu.decode.SquashCycles 636 # Number of cycles decode is squashing 129system.cpu.decode.SquashedInsts 153 # Number of squashed instructions handled by decode 130system.cpu.decode.UnblockCycles 37 # Number of cycles decode is unblocking 131system.cpu.dtb.accesses 0 # DTB accesses 132system.cpu.dtb.hits 0 # DTB hits 133system.cpu.dtb.misses 0 # DTB misses 134system.cpu.dtb.read_accesses 0 # DTB read accesses 135system.cpu.dtb.read_hits 0 # DTB read hits 136system.cpu.dtb.read_misses 0 # DTB read misses 137system.cpu.dtb.write_accesses 0 # DTB write accesses 138system.cpu.dtb.write_hits 0 # DTB write hits 139system.cpu.dtb.write_misses 0 # DTB write misses 140system.cpu.fetch.Branches 1716 # Number of branches that fetch encountered 141system.cpu.fetch.CacheLines 1531 # Number of cache lines fetched 142system.cpu.fetch.Cycles 2794 # Number of cycles fetch has run and was not squashing or blocked 143system.cpu.fetch.IcacheSquashes 211 # Number of outstanding Icache misses that were squashed 144system.cpu.fetch.Insts 10867 # Number of instructions fetch has processed 145system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 146system.cpu.fetch.SquashCycles 387 # Number of cycles fetch has spent squashing 147system.cpu.fetch.branchRate 0.067063 # Number of branch fetches per cycle 148system.cpu.fetch.icacheStallCycles 1531 # Number of cycles fetch is stalled on an Icache miss 149system.cpu.fetch.predictedBranches 737 # Number of branches that fetch has predicted taken 150system.cpu.fetch.rate 0.424691 # Number of inst fetches per cycle 151system.cpu.fetch.rateDist::samples 12856 # Number of instructions fetched each cycle (Total) 152system.cpu.fetch.rateDist::mean 0.845286 # Number of instructions fetched each cycle (Total) 153system.cpu.fetch.rateDist::stdev 2.112165 # Number of instructions fetched each cycle (Total) 154system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 155system.cpu.fetch.rateDist::0 10062 78.27% 78.27% # Number of instructions fetched each cycle (Total) 156system.cpu.fetch.rateDist::1 1173 9.12% 87.39% # Number of instructions fetched each cycle (Total) 157system.cpu.fetch.rateDist::2 132 1.03% 88.42% # Number of instructions fetched each cycle (Total) 158system.cpu.fetch.rateDist::3 122 0.95% 89.37% # Number of instructions fetched each cycle (Total) 159system.cpu.fetch.rateDist::4 273 2.12% 91.49% # Number of instructions fetched each cycle (Total) 160system.cpu.fetch.rateDist::5 123 0.96% 92.45% # Number of instructions fetched each cycle (Total) 161system.cpu.fetch.rateDist::6 157 1.22% 93.67% # Number of instructions fetched each cycle (Total) 162system.cpu.fetch.rateDist::7 97 0.75% 94.42% # Number of instructions fetched each cycle (Total) 163system.cpu.fetch.rateDist::8 717 5.58% 100.00% # Number of instructions fetched each cycle (Total) 164system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 165system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 166system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 167system.cpu.fetch.rateDist::total 12856 # Number of instructions fetched each cycle (Total) 168system.cpu.fp_regfile_reads 3 # number of floating regfile reads 169system.cpu.fp_regfile_writes 1 # number of floating regfile writes 170system.cpu.icache.ReadReq_accesses 1531 # number of ReadReq accesses(hits+misses) 171system.cpu.icache.ReadReq_avg_miss_latency 36303.482587 # average ReadReq miss latency 172system.cpu.icache.ReadReq_avg_mshr_miss_latency 35016.717325 # average ReadReq mshr miss latency 173system.cpu.icache.ReadReq_hits 1129 # number of ReadReq hits 174system.cpu.icache.ReadReq_miss_latency 14594000 # number of ReadReq miss cycles 175system.cpu.icache.ReadReq_miss_rate 0.262573 # miss rate for ReadReq accesses 176system.cpu.icache.ReadReq_misses 402 # number of ReadReq misses 177system.cpu.icache.ReadReq_mshr_hits 73 # number of ReadReq MSHR hits 178system.cpu.icache.ReadReq_mshr_miss_latency 11520500 # number of ReadReq MSHR miss cycles 179system.cpu.icache.ReadReq_mshr_miss_rate 0.214892 # mshr miss rate for ReadReq accesses 180system.cpu.icache.ReadReq_mshr_misses 329 # number of ReadReq MSHR misses 181system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 182system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 183system.cpu.icache.avg_refs 3.431611 # Average number of references to valid blocks. 184system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 185system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 186system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 187system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 188system.cpu.icache.cache_copies 0 # number of cache copies performed 189system.cpu.icache.demand_accesses 1531 # number of demand (read+write) accesses 190system.cpu.icache.demand_avg_miss_latency 36303.482587 # average overall miss latency 191system.cpu.icache.demand_avg_mshr_miss_latency 35016.717325 # average overall mshr miss latency 192system.cpu.icache.demand_hits 1129 # number of demand (read+write) hits 193system.cpu.icache.demand_miss_latency 14594000 # number of demand (read+write) miss cycles 194system.cpu.icache.demand_miss_rate 0.262573 # miss rate for demand accesses 195system.cpu.icache.demand_misses 402 # number of demand (read+write) misses 196system.cpu.icache.demand_mshr_hits 73 # number of demand (read+write) MSHR hits 197system.cpu.icache.demand_mshr_miss_latency 11520500 # number of demand (read+write) MSHR miss cycles 198system.cpu.icache.demand_mshr_miss_rate 0.214892 # mshr miss rate for demand accesses 199system.cpu.icache.demand_mshr_misses 329 # number of demand (read+write) MSHR misses 200system.cpu.icache.fast_writes 0 # number of fast writes performed 201system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 202system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 203system.cpu.icache.occ_blocks::0 158.750706 # Average occupied blocks per context 204system.cpu.icache.occ_percent::0 0.077515 # Average percentage of cache occupancy 205system.cpu.icache.overall_accesses 1531 # number of overall (read+write) accesses 206system.cpu.icache.overall_avg_miss_latency 36303.482587 # average overall miss latency 207system.cpu.icache.overall_avg_mshr_miss_latency 35016.717325 # average overall mshr miss latency 208system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 209system.cpu.icache.overall_hits 1129 # number of overall hits 210system.cpu.icache.overall_miss_latency 14594000 # number of overall miss cycles 211system.cpu.icache.overall_miss_rate 0.262573 # miss rate for overall accesses 212system.cpu.icache.overall_misses 402 # number of overall misses 213system.cpu.icache.overall_mshr_hits 73 # number of overall MSHR hits 214system.cpu.icache.overall_mshr_miss_latency 11520500 # number of overall MSHR miss cycles 215system.cpu.icache.overall_mshr_miss_rate 0.214892 # mshr miss rate for overall accesses 216system.cpu.icache.overall_mshr_misses 329 # number of overall MSHR misses 217system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 218system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 219system.cpu.icache.replacements 15 # number of replacements 220system.cpu.icache.sampled_refs 329 # Sample count of references to valid blocks. 221system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 222system.cpu.icache.tagsinuse 158.750706 # Cycle average of tags in use 223system.cpu.icache.total_refs 1129 # Total number of references to valid blocks. 224system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 225system.cpu.icache.writebacks 0 # number of writebacks 226system.cpu.idleCycles 12732 # Total number of cycles that the CPU has spent unscheduled due to idling 227system.cpu.iew.branchMispredicts 377 # Number of branch mispredicts detected at execute 228system.cpu.iew.exec_branches 1171 # Number of branches executed 229system.cpu.iew.exec_nop 1220 # number of nop insts executed 230system.cpu.iew.exec_rate 0.276575 # Inst execution rate 231system.cpu.iew.exec_refs 2915 # number of memory reference insts executed 232system.cpu.iew.exec_stores 1038 # Number of stores executed 233system.cpu.iew.exec_swp 0 # number of swp insts executed 234system.cpu.iew.iewBlockCycles 165 # Number of cycles IEW is blocking 235system.cpu.iew.iewDispLoadInsts 2109 # Number of dispatched load instructions 236system.cpu.iew.iewDispNonSpecInsts 10 # Number of dispatched non-speculative instructions 237system.cpu.iew.iewDispSquashedInsts 198 # Number of squashed instructions skipped by dispatch 238system.cpu.iew.iewDispStoreInsts 1127 # Number of dispatched store instructions 239system.cpu.iew.iewDispatchedInsts 9195 # Number of instructions dispatched to IQ 240system.cpu.iew.iewExecLoadInsts 1877 # Number of load instructions executed 241system.cpu.iew.iewExecSquashedInsts 216 # Number of squashed instructions skipped in execute 242system.cpu.iew.iewExecutedInsts 7077 # Number of executed instructions 243system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall 244system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 245system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall 246system.cpu.iew.iewSquashCycles 636 # Number of cycles IEW is squashing 247system.cpu.iew.iewUnblockCycles 14 # Number of cycles IEW is unblocking 248system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 249system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 250system.cpu.iew.lsq.thread.0.forwLoads 59 # Number of loads that had data forwarded from stores 251system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 252system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address 253system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 254system.cpu.iew.lsq.thread.0.memOrderViolation 5 # Number of memory ordering violations 255system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled 256system.cpu.iew.lsq.thread.0.squashedLoads 945 # Number of loads squashed 257system.cpu.iew.lsq.thread.0.squashedStores 202 # Number of stores squashed 258system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations 259system.cpu.iew.predictedNotTakenIncorrect 259 # Number of branches that were predicted not taken incorrectly 260system.cpu.iew.predictedTakenIncorrect 118 # Number of branches that were predicted taken incorrectly 261system.cpu.iew.wb_consumers 3566 # num instructions consuming a value 262system.cpu.iew.wb_count 6732 # cumulative count of insts written-back 263system.cpu.iew.wb_fanout 0.716489 # average fanout of values written-back 264system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 265system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 266system.cpu.iew.wb_producers 2555 # num instructions producing a value 267system.cpu.iew.wb_rate 0.263092 # insts written-back per cycle 268system.cpu.iew.wb_sent 6801 # cumulative count of insts sent to commit 269system.cpu.int_regfile_reads 9689 # number of integer regfile reads 270system.cpu.int_regfile_writes 4703 # number of integer regfile writes 271system.cpu.ipc 0.202009 # IPC: Instructions Per Cycle 272system.cpu.ipc_total 0.202009 # IPC: Total IPC of All Threads 273system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 274system.cpu.iq.FU_type_0::IntAlu 4286 58.77% 58.77% # Type of FU issued 275system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.82% # Type of FU issued 276system.cpu.iq.FU_type_0::IntDiv 2 0.03% 58.85% # Type of FU issued 277system.cpu.iq.FU_type_0::FloatAdd 2 0.03% 58.88% # Type of FU issued 278system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.88% # Type of FU issued 279system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.88% # Type of FU issued 280system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.88% # Type of FU issued 281system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.88% # Type of FU issued 282system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.88% # Type of FU issued 283system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.88% # Type of FU issued 284system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.88% # Type of FU issued 285system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.88% # Type of FU issued 286system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.88% # Type of FU issued 287system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.88% # Type of FU issued 288system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.88% # Type of FU issued 289system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.88% # Type of FU issued 290system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.88% # Type of FU issued 291system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.88% # Type of FU issued 292system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.88% # Type of FU issued 293system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.88% # Type of FU issued 294system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.88% # Type of FU issued 295system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.88% # Type of FU issued 296system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.88% # Type of FU issued 297system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.88% # Type of FU issued 298system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.88% # Type of FU issued 299system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.88% # Type of FU issued 300system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.88% # Type of FU issued 301system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.88% # Type of FU issued 302system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.88% # Type of FU issued 303system.cpu.iq.FU_type_0::MemRead 1952 26.77% 85.64% # Type of FU issued 304system.cpu.iq.FU_type_0::MemWrite 1047 14.36% 100.00% # Type of FU issued 305system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 306system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 307system.cpu.iq.FU_type_0::total 7293 # Type of FU issued 308system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses 309system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads 310system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses 311system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 312system.cpu.iq.fu_busy_cnt 143 # FU busy when requested 313system.cpu.iq.fu_busy_rate 0.019608 # FU busy rate (busy events/executed inst) 314system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 315system.cpu.iq.fu_full::IntAlu 7 4.90% 4.90% # attempts to use FU when none available 316system.cpu.iq.fu_full::IntMult 0 0.00% 4.90% # attempts to use FU when none available 317system.cpu.iq.fu_full::IntDiv 0 0.00% 4.90% # attempts to use FU when none available 318system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.90% # attempts to use FU when none available 319system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.90% # attempts to use FU when none available 320system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.90% # attempts to use FU when none available 321system.cpu.iq.fu_full::FloatMult 0 0.00% 4.90% # attempts to use FU when none available 322system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.90% # attempts to use FU when none available 323system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.90% # attempts to use FU when none available 324system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.90% # attempts to use FU when none available 325system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.90% # attempts to use FU when none available 326system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.90% # attempts to use FU when none available 327system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.90% # attempts to use FU when none available 328system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.90% # attempts to use FU when none available 329system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.90% # attempts to use FU when none available 330system.cpu.iq.fu_full::SimdMult 0 0.00% 4.90% # attempts to use FU when none available 331system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.90% # attempts to use FU when none available 332system.cpu.iq.fu_full::SimdShift 0 0.00% 4.90% # attempts to use FU when none available 333system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.90% # attempts to use FU when none available 334system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.90% # attempts to use FU when none available 335system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.90% # attempts to use FU when none available 336system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.90% # attempts to use FU when none available 337system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.90% # attempts to use FU when none available 338system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.90% # attempts to use FU when none available 339system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.90% # attempts to use FU when none available 340system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.90% # attempts to use FU when none available 341system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.90% # attempts to use FU when none available 342system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.90% # attempts to use FU when none available 343system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.90% # attempts to use FU when none available 344system.cpu.iq.fu_full::MemRead 84 58.74% 63.64% # attempts to use FU when none available 345system.cpu.iq.fu_full::MemWrite 52 36.36% 100.00% # attempts to use FU when none available 346system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 347system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 348system.cpu.iq.int_alu_accesses 7434 # Number of integer alu accesses 349system.cpu.iq.int_inst_queue_reads 27612 # Number of integer instruction queue reads 350system.cpu.iq.int_inst_queue_wakeup_accesses 6730 # Number of integer instruction queue wakeup accesses 351system.cpu.iq.int_inst_queue_writes 10338 # Number of integer instruction queue writes 352system.cpu.iq.iqInstsAdded 7965 # Number of instructions added to the IQ (excludes non-spec) 353system.cpu.iq.iqInstsIssued 7293 # Number of instructions issued 354system.cpu.iq.iqNonSpecInstsAdded 10 # Number of non-speculative instructions added to the IQ 355system.cpu.iq.iqSquashedInstsExamined 2360 # Number of squashed instructions iterated over during squash; mainly for profiling 356system.cpu.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued 357system.cpu.iq.iqSquashedOperandsExamined 1480 # Number of squashed operands that are examined and possibly removed from graph 358system.cpu.iq.issued_per_cycle::samples 12856 # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::mean 0.567284 # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::stdev 1.210668 # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::0 9551 74.29% 74.29% # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::1 1436 11.17% 85.46% # Number of insts issued each cycle 364system.cpu.iq.issued_per_cycle::2 786 6.11% 91.58% # Number of insts issued each cycle 365system.cpu.iq.issued_per_cycle::3 503 3.91% 95.49% # Number of insts issued each cycle 366system.cpu.iq.issued_per_cycle::4 300 2.33% 97.82% # Number of insts issued each cycle 367system.cpu.iq.issued_per_cycle::5 160 1.24% 99.07% # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::6 76 0.59% 99.66% # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::7 32 0.25% 99.91% # Number of insts issued each cycle 370system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle 371system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 372system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 373system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 374system.cpu.iq.issued_per_cycle::total 12856 # Number of insts issued each cycle 375system.cpu.iq.rate 0.285016 # Inst issue rate 376system.cpu.itb.accesses 0 # DTB accesses 377system.cpu.itb.hits 0 # DTB hits 378system.cpu.itb.misses 0 # DTB misses 379system.cpu.itb.read_accesses 0 # DTB read accesses 380system.cpu.itb.read_hits 0 # DTB read hits 381system.cpu.itb.read_misses 0 # DTB read misses 382system.cpu.itb.write_accesses 0 # DTB write accesses 383system.cpu.itb.write_hits 0 # DTB write hits 384system.cpu.itb.write_misses 0 # DTB write misses 385system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses) 386system.cpu.l2cache.ReadExReq_avg_miss_latency 34686.274510 # average ReadExReq miss latency 387system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31490.196078 # average ReadExReq mshr miss latency 388system.cpu.l2cache.ReadExReq_miss_latency 1769000 # number of ReadExReq miss cycles 389system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses 390system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses 391system.cpu.l2cache.ReadExReq_mshr_miss_latency 1606000 # number of ReadExReq MSHR miss cycles 392system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses 393system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses 394system.cpu.l2cache.ReadReq_accesses 419 # number of ReadReq accesses(hits+misses) 395system.cpu.l2cache.ReadReq_avg_miss_latency 34317.307692 # average ReadReq miss latency 396system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31129.807692 # average ReadReq mshr miss latency 397system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits 398system.cpu.l2cache.ReadReq_miss_latency 14276000 # number of ReadReq miss cycles 399system.cpu.l2cache.ReadReq_miss_rate 0.992840 # miss rate for ReadReq accesses 400system.cpu.l2cache.ReadReq_misses 416 # number of ReadReq misses 401system.cpu.l2cache.ReadReq_mshr_miss_latency 12950000 # number of ReadReq MSHR miss cycles 402system.cpu.l2cache.ReadReq_mshr_miss_rate 0.992840 # mshr miss rate for ReadReq accesses 403system.cpu.l2cache.ReadReq_mshr_misses 416 # number of ReadReq MSHR misses 404system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 405system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 406system.cpu.l2cache.avg_refs 0.007212 # Average number of references to valid blocks. 407system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 408system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 409system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 410system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 411system.cpu.l2cache.cache_copies 0 # number of cache copies performed 412system.cpu.l2cache.demand_accesses 470 # number of demand (read+write) accesses 413system.cpu.l2cache.demand_avg_miss_latency 34357.601713 # average overall miss latency 414system.cpu.l2cache.demand_avg_mshr_miss_latency 31169.164882 # average overall mshr miss latency 415system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits 416system.cpu.l2cache.demand_miss_latency 16045000 # number of demand (read+write) miss cycles 417system.cpu.l2cache.demand_miss_rate 0.993617 # miss rate for demand accesses 418system.cpu.l2cache.demand_misses 467 # number of demand (read+write) misses 419system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 420system.cpu.l2cache.demand_mshr_miss_latency 14556000 # number of demand (read+write) MSHR miss cycles 421system.cpu.l2cache.demand_mshr_miss_rate 0.993617 # mshr miss rate for demand accesses 422system.cpu.l2cache.demand_mshr_misses 467 # number of demand (read+write) MSHR misses 423system.cpu.l2cache.fast_writes 0 # number of fast writes performed 424system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 425system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 426system.cpu.l2cache.occ_blocks::0 218.141494 # Average occupied blocks per context 427system.cpu.l2cache.occ_percent::0 0.006657 # Average percentage of cache occupancy 428system.cpu.l2cache.overall_accesses 470 # number of overall (read+write) accesses 429system.cpu.l2cache.overall_avg_miss_latency 34357.601713 # average overall miss latency 430system.cpu.l2cache.overall_avg_mshr_miss_latency 31169.164882 # average overall mshr miss latency 431system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 432system.cpu.l2cache.overall_hits 3 # number of overall hits 433system.cpu.l2cache.overall_miss_latency 16045000 # number of overall miss cycles 434system.cpu.l2cache.overall_miss_rate 0.993617 # miss rate for overall accesses 435system.cpu.l2cache.overall_misses 467 # number of overall misses 436system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits 437system.cpu.l2cache.overall_mshr_miss_latency 14556000 # number of overall MSHR miss cycles 438system.cpu.l2cache.overall_mshr_miss_rate 0.993617 # mshr miss rate for overall accesses 439system.cpu.l2cache.overall_mshr_misses 467 # number of overall MSHR misses 440system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 441system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 442system.cpu.l2cache.replacements 0 # number of replacements 443system.cpu.l2cache.sampled_refs 416 # Sample count of references to valid blocks. 444system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 445system.cpu.l2cache.tagsinuse 218.141494 # Cycle average of tags in use 446system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. 447system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 448system.cpu.l2cache.writebacks 0 # number of writebacks 449system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 450system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. 451system.cpu.memDep0.insertedLoads 2109 # Number of loads inserted to the mem dependence unit. 452system.cpu.memDep0.insertedStores 1127 # Number of stores inserted to the mem dependence unit. 453system.cpu.misc_regfile_reads 134 # number of misc regfile reads 454system.cpu.numCycles 25588 # number of cpu cycles simulated 455system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 456system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 457system.cpu.rename.BlockCycles 238 # Number of cycles rename is blocking 458system.cpu.rename.CommittedMaps 3410 # Number of HB maps that are committed 459system.cpu.rename.IdleCycles 8904 # Number of cycles rename is idle 460system.cpu.rename.LSQFullEvents 71 # Number of times rename has blocked due to LSQ full 461system.cpu.rename.RenameLookups 11929 # Number of register rename lookups that rename has made 462system.cpu.rename.RenamedInsts 9880 # Number of instructions processed by rename 463system.cpu.rename.RenamedOperands 6029 # Number of destination operands rename has renamed 464system.cpu.rename.RunCycles 2577 # Number of cycles rename is running 465system.cpu.rename.SquashCycles 636 # Number of cycles rename is squashing 466system.cpu.rename.UnblockCycles 81 # Number of cycles rename is unblocking 467system.cpu.rename.UndoneMaps 2619 # Number of HB maps that are undone due to squashing 468system.cpu.rename.fp_rename_lookups 5 # Number of floating rename lookups 469system.cpu.rename.int_rename_lookups 11924 # Number of integer rename lookups 470system.cpu.rename.serializeStallCycles 420 # count of cycles rename stalled for serializing inst 471system.cpu.rename.serializingInsts 15 # count of serializing insts renamed 472system.cpu.rename.skidInsts 193 # count of insts added to the skid buffer 473system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed 474system.cpu.rob.rob_reads 21319 # The number of ROB reads 475system.cpu.rob.rob_writes 19020 # The number of ROB writes 476system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself 477system.cpu.workload.num_syscalls 8 # Number of system calls 478 479---------- End Simulation Statistics ---------- 480