stats.txt revision 6291
1 2---------- Begin Simulation Statistics ---------- 3host_inst_rate 27478 # Simulator instruction rate (inst/s) 4host_mem_usage 190884 # Number of bytes of host memory used 5host_seconds 0.18 # Real time elapsed on the host 6host_tick_rate 75816661 # Simulator tick rate (ticks/s) 7sim_freq 1000000000000 # Frequency of simulated ticks 8sim_insts 5024 # Number of instructions simulated 9sim_seconds 0.000014 # Number of seconds simulated 10sim_ticks 13881500 # Number of ticks simulated 11system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 12system.cpu.BPredUnit.BTBHits 549 # Number of BTB hits 13system.cpu.BPredUnit.BTBLookups 1924 # Number of BTB lookups 14system.cpu.BPredUnit.RASInCorrect 53 # Number of incorrect RAS predictions. 15system.cpu.BPredUnit.condIncorrect 721 # Number of conditional branches incorrect 16system.cpu.BPredUnit.condPredicted 1540 # Number of conditional branches predicted 17system.cpu.BPredUnit.lookups 2339 # Number of BP lookups 18system.cpu.BPredUnit.usedRAS 384 # Number of times the RAS was used to get a target. 19system.cpu.commit.COM:branches 879 # Number of branches committed 20system.cpu.commit.COM:bw_lim_events 63 # number cycles where commit BW limit reached 21system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits 22system.cpu.commit.COM:committed_per_cycle::samples 14165 # Number of insts commited each cycle 23system.cpu.commit.COM:committed_per_cycle::mean 0.399223 # Number of insts commited each cycle 24system.cpu.commit.COM:committed_per_cycle::stdev 1.126414 # Number of insts commited each cycle 25system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 26system.cpu.commit.COM:committed_per_cycle::0-1 11701 82.61% 82.61% # Number of insts commited each cycle 27system.cpu.commit.COM:committed_per_cycle::1-2 1166 8.23% 90.84% # Number of insts commited each cycle 28system.cpu.commit.COM:committed_per_cycle::2-3 493 3.48% 94.32% # Number of insts commited each cycle 29system.cpu.commit.COM:committed_per_cycle::3-4 279 1.97% 96.29% # Number of insts commited each cycle 30system.cpu.commit.COM:committed_per_cycle::4-5 290 2.05% 98.33% # Number of insts commited each cycle 31system.cpu.commit.COM:committed_per_cycle::5-6 74 0.52% 98.86% # Number of insts commited each cycle 32system.cpu.commit.COM:committed_per_cycle::6-7 61 0.43% 99.29% # Number of insts commited each cycle 33system.cpu.commit.COM:committed_per_cycle::7-8 38 0.27% 99.56% # Number of insts commited each cycle 34system.cpu.commit.COM:committed_per_cycle::8 63 0.44% 100.00% # Number of insts commited each cycle 35system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 36system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle 37system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle 38system.cpu.commit.COM:committed_per_cycle::total 14165 # Number of insts commited each cycle 39system.cpu.commit.COM:count 5655 # Number of instructions committed 40system.cpu.commit.COM:loads 1130 # Number of loads committed 41system.cpu.commit.COM:membars 0 # Number of memory barriers committed 42system.cpu.commit.COM:refs 2054 # Number of memory references committed 43system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed 44system.cpu.commit.branchMispredicts 604 # The number of times a branch was mispredicted 45system.cpu.commit.commitCommittedInsts 5655 # The number of committed instructions 46system.cpu.commit.commitNonSpecStalls 15 # The number of times commit has been forced to stall to communicate backwards 47system.cpu.commit.commitSquashedInsts 5936 # The number of squashed insts skipped by commit 48system.cpu.committedInsts 5024 # Number of Instructions Simulated 49system.cpu.committedInsts_total 5024 # Number of Instructions Simulated 50system.cpu.cpi 5.526274 # CPI: Cycles Per Instruction 51system.cpu.cpi_total 5.526274 # CPI: Total CPI of All Threads 52system.cpu.dcache.ReadReq_accesses 2286 # number of ReadReq accesses(hits+misses) 53system.cpu.dcache.ReadReq_avg_miss_latency 33976.377953 # average ReadReq miss latency 54system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36034.883721 # average ReadReq mshr miss latency 55system.cpu.dcache.ReadReq_hits 2159 # number of ReadReq hits 56system.cpu.dcache.ReadReq_miss_latency 4315000 # number of ReadReq miss cycles 57system.cpu.dcache.ReadReq_miss_rate 0.055556 # miss rate for ReadReq accesses 58system.cpu.dcache.ReadReq_misses 127 # number of ReadReq misses 59system.cpu.dcache.ReadReq_mshr_hits 41 # number of ReadReq MSHR hits 60system.cpu.dcache.ReadReq_mshr_miss_latency 3099000 # number of ReadReq MSHR miss cycles 61system.cpu.dcache.ReadReq_mshr_miss_rate 0.037620 # mshr miss rate for ReadReq accesses 62system.cpu.dcache.ReadReq_mshr_misses 86 # number of ReadReq MSHR misses 63system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses) 64system.cpu.dcache.WriteReq_avg_miss_latency 27701.724138 # average WriteReq miss latency 65system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36093.750000 # average WriteReq mshr miss latency 66system.cpu.dcache.WriteReq_hits 634 # number of WriteReq hits 67system.cpu.dcache.WriteReq_miss_latency 8033500 # number of WriteReq miss cycles 68system.cpu.dcache.WriteReq_miss_rate 0.313853 # miss rate for WriteReq accesses 69system.cpu.dcache.WriteReq_misses 290 # number of WriteReq misses 70system.cpu.dcache.WriteReq_mshr_hits 226 # number of WriteReq MSHR hits 71system.cpu.dcache.WriteReq_mshr_miss_latency 2310000 # number of WriteReq MSHR miss cycles 72system.cpu.dcache.WriteReq_mshr_miss_rate 0.069264 # mshr miss rate for WriteReq accesses 73system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses 74system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 75system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 76system.cpu.dcache.avg_refs 20.970370 # Average number of references to valid blocks. 77system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 78system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 79system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 80system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 81system.cpu.dcache.cache_copies 0 # number of cache copies performed 82system.cpu.dcache.demand_accesses 3210 # number of demand (read+write) accesses 83system.cpu.dcache.demand_avg_miss_latency 29612.709832 # average overall miss latency 84system.cpu.dcache.demand_avg_mshr_miss_latency 36060 # average overall mshr miss latency 85system.cpu.dcache.demand_hits 2793 # number of demand (read+write) hits 86system.cpu.dcache.demand_miss_latency 12348500 # number of demand (read+write) miss cycles 87system.cpu.dcache.demand_miss_rate 0.129907 # miss rate for demand accesses 88system.cpu.dcache.demand_misses 417 # number of demand (read+write) misses 89system.cpu.dcache.demand_mshr_hits 267 # number of demand (read+write) MSHR hits 90system.cpu.dcache.demand_mshr_miss_latency 5409000 # number of demand (read+write) MSHR miss cycles 91system.cpu.dcache.demand_mshr_miss_rate 0.046729 # mshr miss rate for demand accesses 92system.cpu.dcache.demand_mshr_misses 150 # number of demand (read+write) MSHR misses 93system.cpu.dcache.fast_writes 0 # number of fast writes performed 94system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 95system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 96system.cpu.dcache.overall_accesses 3210 # number of overall (read+write) accesses 97system.cpu.dcache.overall_avg_miss_latency 29612.709832 # average overall miss latency 98system.cpu.dcache.overall_avg_mshr_miss_latency 36060 # average overall mshr miss latency 99system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 100system.cpu.dcache.overall_hits 2793 # number of overall hits 101system.cpu.dcache.overall_miss_latency 12348500 # number of overall miss cycles 102system.cpu.dcache.overall_miss_rate 0.129907 # miss rate for overall accesses 103system.cpu.dcache.overall_misses 417 # number of overall misses 104system.cpu.dcache.overall_mshr_hits 267 # number of overall MSHR hits 105system.cpu.dcache.overall_mshr_miss_latency 5409000 # number of overall MSHR miss cycles 106system.cpu.dcache.overall_mshr_miss_rate 0.046729 # mshr miss rate for overall accesses 107system.cpu.dcache.overall_mshr_misses 150 # number of overall MSHR misses 108system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 109system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 110system.cpu.dcache.replacements 0 # number of replacements 111system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. 112system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 113system.cpu.dcache.tagsinuse 87.531358 # Cycle average of tags in use 114system.cpu.dcache.total_refs 2831 # Total number of references to valid blocks. 115system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 116system.cpu.dcache.writebacks 0 # number of writebacks 117system.cpu.decode.DECODE:BlockedCycles 479 # Number of cycles decode is blocked 118system.cpu.decode.DECODE:BranchMispred 128 # Number of times decode detected a branch misprediction 119system.cpu.decode.DECODE:BranchResolved 128 # Number of times decode resolved a branch 120system.cpu.decode.DECODE:DecodedInsts 14141 # Number of instructions handled by decode 121system.cpu.decode.DECODE:IdleCycles 9863 # Number of cycles decode is idle 122system.cpu.decode.DECODE:RunCycles 3823 # Number of cycles decode is running 123system.cpu.decode.DECODE:SquashCycles 1052 # Number of cycles decode is squashing 124system.cpu.decode.DECODE:SquashedInsts 251 # Number of squashed instructions handled by decode 125system.cpu.dtb.accesses 0 # DTB accesses 126system.cpu.dtb.hits 0 # DTB hits 127system.cpu.dtb.misses 0 # DTB misses 128system.cpu.dtb.read_accesses 0 # DTB read accesses 129system.cpu.dtb.read_hits 0 # DTB read hits 130system.cpu.dtb.read_misses 0 # DTB read misses 131system.cpu.dtb.write_accesses 0 # DTB write accesses 132system.cpu.dtb.write_hits 0 # DTB write hits 133system.cpu.dtb.write_misses 0 # DTB write misses 134system.cpu.fetch.Branches 2339 # Number of branches that fetch encountered 135system.cpu.fetch.CacheLines 2162 # Number of cache lines fetched 136system.cpu.fetch.Cycles 6161 # Number of cycles fetch has run and was not squashing or blocked 137system.cpu.fetch.IcacheSquashes 360 # Number of outstanding Icache misses that were squashed 138system.cpu.fetch.Insts 15261 # Number of instructions fetch has processed 139system.cpu.fetch.SquashCycles 737 # Number of cycles fetch has spent squashing 140system.cpu.fetch.branchRate 0.084246 # Number of branch fetches per cycle 141system.cpu.fetch.icacheStallCycles 2162 # Number of cycles fetch is stalled on an Icache miss 142system.cpu.fetch.predictedBranches 933 # Number of branches that fetch has predicted taken 143system.cpu.fetch.rate 0.549669 # Number of inst fetches per cycle 144system.cpu.fetch.rateDist::samples 15217 # Number of instructions fetched each cycle (Total) 145system.cpu.fetch.rateDist::mean 1.002892 # Number of instructions fetched each cycle (Total) 146system.cpu.fetch.rateDist::stdev 2.262712 # Number of instructions fetched each cycle (Total) 147system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 148system.cpu.fetch.rateDist::0-1 11225 73.77% 73.77% # Number of instructions fetched each cycle (Total) 149system.cpu.fetch.rateDist::1-2 1766 11.61% 85.37% # Number of instructions fetched each cycle (Total) 150system.cpu.fetch.rateDist::2-3 196 1.29% 86.66% # Number of instructions fetched each cycle (Total) 151system.cpu.fetch.rateDist::3-4 137 0.90% 87.56% # Number of instructions fetched each cycle (Total) 152system.cpu.fetch.rateDist::4-5 314 2.06% 89.62% # Number of instructions fetched each cycle (Total) 153system.cpu.fetch.rateDist::5-6 113 0.74% 90.37% # Number of instructions fetched each cycle (Total) 154system.cpu.fetch.rateDist::6-7 304 2.00% 92.36% # Number of instructions fetched each cycle (Total) 155system.cpu.fetch.rateDist::7-8 249 1.64% 94.00% # Number of instructions fetched each cycle (Total) 156system.cpu.fetch.rateDist::8 913 6.00% 100.00% # Number of instructions fetched each cycle (Total) 157system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 158system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 159system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 160system.cpu.fetch.rateDist::total 15217 # Number of instructions fetched each cycle (Total) 161system.cpu.icache.ReadReq_accesses 2162 # number of ReadReq accesses(hits+misses) 162system.cpu.icache.ReadReq_avg_miss_latency 35500 # average ReadReq miss latency 163system.cpu.icache.ReadReq_avg_mshr_miss_latency 34915.151515 # average ReadReq mshr miss latency 164system.cpu.icache.ReadReq_hits 1731 # number of ReadReq hits 165system.cpu.icache.ReadReq_miss_latency 15300500 # number of ReadReq miss cycles 166system.cpu.icache.ReadReq_miss_rate 0.199352 # miss rate for ReadReq accesses 167system.cpu.icache.ReadReq_misses 431 # number of ReadReq misses 168system.cpu.icache.ReadReq_mshr_hits 101 # number of ReadReq MSHR hits 169system.cpu.icache.ReadReq_mshr_miss_latency 11522000 # number of ReadReq MSHR miss cycles 170system.cpu.icache.ReadReq_mshr_miss_rate 0.152636 # mshr miss rate for ReadReq accesses 171system.cpu.icache.ReadReq_mshr_misses 330 # number of ReadReq MSHR misses 172system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 173system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 174system.cpu.icache.avg_refs 5.245455 # Average number of references to valid blocks. 175system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 176system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 177system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 178system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 179system.cpu.icache.cache_copies 0 # number of cache copies performed 180system.cpu.icache.demand_accesses 2162 # number of demand (read+write) accesses 181system.cpu.icache.demand_avg_miss_latency 35500 # average overall miss latency 182system.cpu.icache.demand_avg_mshr_miss_latency 34915.151515 # average overall mshr miss latency 183system.cpu.icache.demand_hits 1731 # number of demand (read+write) hits 184system.cpu.icache.demand_miss_latency 15300500 # number of demand (read+write) miss cycles 185system.cpu.icache.demand_miss_rate 0.199352 # miss rate for demand accesses 186system.cpu.icache.demand_misses 431 # number of demand (read+write) misses 187system.cpu.icache.demand_mshr_hits 101 # number of demand (read+write) MSHR hits 188system.cpu.icache.demand_mshr_miss_latency 11522000 # number of demand (read+write) MSHR miss cycles 189system.cpu.icache.demand_mshr_miss_rate 0.152636 # mshr miss rate for demand accesses 190system.cpu.icache.demand_mshr_misses 330 # number of demand (read+write) MSHR misses 191system.cpu.icache.fast_writes 0 # number of fast writes performed 192system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 193system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 194system.cpu.icache.overall_accesses 2162 # number of overall (read+write) accesses 195system.cpu.icache.overall_avg_miss_latency 35500 # average overall miss latency 196system.cpu.icache.overall_avg_mshr_miss_latency 34915.151515 # average overall mshr miss latency 197system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 198system.cpu.icache.overall_hits 1731 # number of overall hits 199system.cpu.icache.overall_miss_latency 15300500 # number of overall miss cycles 200system.cpu.icache.overall_miss_rate 0.199352 # miss rate for overall accesses 201system.cpu.icache.overall_misses 431 # number of overall misses 202system.cpu.icache.overall_mshr_hits 101 # number of overall MSHR hits 203system.cpu.icache.overall_mshr_miss_latency 11522000 # number of overall MSHR miss cycles 204system.cpu.icache.overall_mshr_miss_rate 0.152636 # mshr miss rate for overall accesses 205system.cpu.icache.overall_mshr_misses 330 # number of overall MSHR misses 206system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 207system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 208system.cpu.icache.replacements 16 # number of replacements 209system.cpu.icache.sampled_refs 330 # Sample count of references to valid blocks. 210system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 211system.cpu.icache.tagsinuse 158.760808 # Cycle average of tags in use 212system.cpu.icache.total_refs 1731 # Total number of references to valid blocks. 213system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 214system.cpu.icache.writebacks 0 # number of writebacks 215system.cpu.idleCycles 12547 # Total number of cycles that the CPU has spent unscheduled due to idling 216system.cpu.iew.EXEC:branches 1206 # Number of branches executed 217system.cpu.iew.EXEC:nop 1806 # number of nop insts executed 218system.cpu.iew.EXEC:rate 0.291349 # Inst execution rate 219system.cpu.iew.EXEC:refs 3420 # number of memory reference insts executed 220system.cpu.iew.EXEC:stores 1048 # Number of stores executed 221system.cpu.iew.EXEC:swp 0 # number of swp insts executed 222system.cpu.iew.WB:consumers 4016 # num instructions consuming a value 223system.cpu.iew.WB:count 7315 # cumulative count of insts written-back 224system.cpu.iew.WB:fanout 0.694970 # average fanout of values written-back 225system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ 226system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 227system.cpu.iew.WB:producers 2791 # num instructions producing a value 228system.cpu.iew.WB:rate 0.263471 # insts written-back per cycle 229system.cpu.iew.WB:sent 7402 # cumulative count of insts sent to commit 230system.cpu.iew.branchMispredicts 661 # Number of branch mispredicts detected at execute 231system.cpu.iew.iewBlockCycles 8 # Number of cycles IEW is blocking 232system.cpu.iew.iewDispLoadInsts 2783 # Number of dispatched load instructions 233system.cpu.iew.iewDispNonSpecInsts 15 # Number of dispatched non-speculative instructions 234system.cpu.iew.iewDispSquashedInsts 968 # Number of squashed instructions skipped by dispatch 235system.cpu.iew.iewDispStoreInsts 1158 # Number of dispatched store instructions 236system.cpu.iew.iewDispatchedInsts 11594 # Number of instructions dispatched to IQ 237system.cpu.iew.iewExecLoadInsts 2372 # Number of load instructions executed 238system.cpu.iew.iewExecSquashedInsts 531 # Number of squashed instructions skipped in execute 239system.cpu.iew.iewExecutedInsts 8089 # Number of executed instructions 240system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall 241system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 242system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall 243system.cpu.iew.iewSquashCycles 1052 # Number of cycles IEW is squashing 244system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking 245system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 246system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 247system.cpu.iew.lsq.thread.0.forwLoads 68 # Number of loads that had data forwarded from stores 248system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 249system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address 250system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 251system.cpu.iew.lsq.thread.0.memOrderViolation 22 # Number of memory ordering violations 252system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled 253system.cpu.iew.lsq.thread.0.squashedLoads 1653 # Number of loads squashed 254system.cpu.iew.lsq.thread.0.squashedStores 234 # Number of stores squashed 255system.cpu.iew.memOrderViolationEvents 22 # Number of memory order violations 256system.cpu.iew.predictedNotTakenIncorrect 276 # Number of branches that were predicted not taken incorrectly 257system.cpu.iew.predictedTakenIncorrect 385 # Number of branches that were predicted taken incorrectly 258system.cpu.ipc 0.180954 # IPC: Instructions Per Cycle 259system.cpu.ipc_total 0.180954 # IPC: Total IPC of All Threads 260system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 261system.cpu.iq.ISSUE:FU_type_0::IntAlu 4988 57.87% 57.87% # Type of FU issued 262system.cpu.iq.ISSUE:FU_type_0::IntMult 5 0.06% 57.92% # Type of FU issued 263system.cpu.iq.ISSUE:FU_type_0::IntDiv 2 0.02% 57.95% # Type of FU issued 264system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 57.97% # Type of FU issued 265system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 57.97% # Type of FU issued 266system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 57.97% # Type of FU issued 267system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 57.97% # Type of FU issued 268system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 57.97% # Type of FU issued 269system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 57.97% # Type of FU issued 270system.cpu.iq.ISSUE:FU_type_0::MemRead 2560 29.70% 87.67% # Type of FU issued 271system.cpu.iq.ISSUE:FU_type_0::MemWrite 1063 12.33% 100.00% # Type of FU issued 272system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 273system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 274system.cpu.iq.ISSUE:FU_type_0::total 8620 # Type of FU issued 275system.cpu.iq.ISSUE:fu_busy_cnt 162 # FU busy when requested 276system.cpu.iq.ISSUE:fu_busy_rate 0.018794 # FU busy rate (busy events/executed inst) 277system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 278system.cpu.iq.ISSUE:fu_full::IntAlu 10 6.17% 6.17% # attempts to use FU when none available 279system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 6.17% # attempts to use FU when none available 280system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 6.17% # attempts to use FU when none available 281system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 6.17% # attempts to use FU when none available 282system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 6.17% # attempts to use FU when none available 283system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 6.17% # attempts to use FU when none available 284system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 6.17% # attempts to use FU when none available 285system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 6.17% # attempts to use FU when none available 286system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 6.17% # attempts to use FU when none available 287system.cpu.iq.ISSUE:fu_full::MemRead 98 60.49% 66.67% # attempts to use FU when none available 288system.cpu.iq.ISSUE:fu_full::MemWrite 54 33.33% 100.00% # attempts to use FU when none available 289system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 290system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 291system.cpu.iq.ISSUE:issued_per_cycle::samples 15217 # Number of insts issued each cycle 292system.cpu.iq.ISSUE:issued_per_cycle::mean 0.566472 # Number of insts issued each cycle 293system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.217507 # Number of insts issued each cycle 294system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 295system.cpu.iq.ISSUE:issued_per_cycle::0-1 11370 74.72% 74.72% # Number of insts issued each cycle 296system.cpu.iq.ISSUE:issued_per_cycle::1-2 1673 10.99% 85.71% # Number of insts issued each cycle 297system.cpu.iq.ISSUE:issued_per_cycle::2-3 787 5.17% 90.89% # Number of insts issued each cycle 298system.cpu.iq.ISSUE:issued_per_cycle::3-4 717 4.71% 95.60% # Number of insts issued each cycle 299system.cpu.iq.ISSUE:issued_per_cycle::4-5 332 2.18% 97.78% # Number of insts issued each cycle 300system.cpu.iq.ISSUE:issued_per_cycle::5-6 198 1.30% 99.08% # Number of insts issued each cycle 301system.cpu.iq.ISSUE:issued_per_cycle::6-7 91 0.60% 99.68% # Number of insts issued each cycle 302system.cpu.iq.ISSUE:issued_per_cycle::7-8 34 0.22% 99.90% # Number of insts issued each cycle 303system.cpu.iq.ISSUE:issued_per_cycle::8 15 0.10% 100.00% # Number of insts issued each cycle 304system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 305system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle 306system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle 307system.cpu.iq.ISSUE:issued_per_cycle::total 15217 # Number of insts issued each cycle 308system.cpu.iq.ISSUE:rate 0.310474 # Inst issue rate 309system.cpu.iq.iqInstsAdded 9773 # Number of instructions added to the IQ (excludes non-spec) 310system.cpu.iq.iqInstsIssued 8620 # Number of instructions issued 311system.cpu.iq.iqNonSpecInstsAdded 15 # Number of non-speculative instructions added to the IQ 312system.cpu.iq.iqSquashedInstsExamined 4182 # Number of squashed instructions iterated over during squash; mainly for profiling 313system.cpu.iq.iqSquashedInstsIssued 30 # Number of squashed instructions issued 314system.cpu.iq.iqSquashedOperandsExamined 2741 # Number of squashed operands that are examined and possibly removed from graph 315system.cpu.itb.accesses 0 # DTB accesses 316system.cpu.itb.hits 0 # DTB hits 317system.cpu.itb.misses 0 # DTB misses 318system.cpu.itb.read_accesses 0 # DTB read accesses 319system.cpu.itb.read_hits 0 # DTB read hits 320system.cpu.itb.read_misses 0 # DTB read misses 321system.cpu.itb.write_accesses 0 # DTB write accesses 322system.cpu.itb.write_hits 0 # DTB write hits 323system.cpu.itb.write_misses 0 # DTB write misses 324system.cpu.l2cache.ReadExReq_accesses 49 # number of ReadExReq accesses(hits+misses) 325system.cpu.l2cache.ReadExReq_avg_miss_latency 34704.081633 # average ReadExReq miss latency 326system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31408.163265 # average ReadExReq mshr miss latency 327system.cpu.l2cache.ReadExReq_miss_latency 1700500 # number of ReadExReq miss cycles 328system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses 329system.cpu.l2cache.ReadExReq_misses 49 # number of ReadExReq misses 330system.cpu.l2cache.ReadExReq_mshr_miss_latency 1539000 # number of ReadExReq MSHR miss cycles 331system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses 332system.cpu.l2cache.ReadExReq_mshr_misses 49 # number of ReadExReq MSHR misses 333system.cpu.l2cache.ReadReq_accesses 416 # number of ReadReq accesses(hits+misses) 334system.cpu.l2cache.ReadReq_avg_miss_latency 34308.252427 # average ReadReq miss latency 335system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31129.854369 # average ReadReq mshr miss latency 336system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits 337system.cpu.l2cache.ReadReq_miss_latency 14135000 # number of ReadReq miss cycles 338system.cpu.l2cache.ReadReq_miss_rate 0.990385 # miss rate for ReadReq accesses 339system.cpu.l2cache.ReadReq_misses 412 # number of ReadReq misses 340system.cpu.l2cache.ReadReq_mshr_miss_latency 12825500 # number of ReadReq MSHR miss cycles 341system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990385 # mshr miss rate for ReadReq accesses 342system.cpu.l2cache.ReadReq_mshr_misses 412 # number of ReadReq MSHR misses 343system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses) 344system.cpu.l2cache.UpgradeReq_avg_miss_latency 34400 # average UpgradeReq miss latency 345system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31166.666667 # average UpgradeReq mshr miss latency 346system.cpu.l2cache.UpgradeReq_miss_latency 516000 # number of UpgradeReq miss cycles 347system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses 348system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses 349system.cpu.l2cache.UpgradeReq_mshr_miss_latency 467500 # number of UpgradeReq MSHR miss cycles 350system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses 351system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses 352system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 353system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 354system.cpu.l2cache.avg_refs 0.010076 # Average number of references to valid blocks. 355system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 356system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 357system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 358system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 359system.cpu.l2cache.cache_copies 0 # number of cache copies performed 360system.cpu.l2cache.demand_accesses 465 # number of demand (read+write) accesses 361system.cpu.l2cache.demand_avg_miss_latency 34350.325380 # average overall miss latency 362system.cpu.l2cache.demand_avg_mshr_miss_latency 31159.436009 # average overall mshr miss latency 363system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits 364system.cpu.l2cache.demand_miss_latency 15835500 # number of demand (read+write) miss cycles 365system.cpu.l2cache.demand_miss_rate 0.991398 # miss rate for demand accesses 366system.cpu.l2cache.demand_misses 461 # number of demand (read+write) misses 367system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 368system.cpu.l2cache.demand_mshr_miss_latency 14364500 # number of demand (read+write) MSHR miss cycles 369system.cpu.l2cache.demand_mshr_miss_rate 0.991398 # mshr miss rate for demand accesses 370system.cpu.l2cache.demand_mshr_misses 461 # number of demand (read+write) MSHR misses 371system.cpu.l2cache.fast_writes 0 # number of fast writes performed 372system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 373system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 374system.cpu.l2cache.overall_accesses 465 # number of overall (read+write) accesses 375system.cpu.l2cache.overall_avg_miss_latency 34350.325380 # average overall miss latency 376system.cpu.l2cache.overall_avg_mshr_miss_latency 31159.436009 # average overall mshr miss latency 377system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 378system.cpu.l2cache.overall_hits 4 # number of overall hits 379system.cpu.l2cache.overall_miss_latency 15835500 # number of overall miss cycles 380system.cpu.l2cache.overall_miss_rate 0.991398 # miss rate for overall accesses 381system.cpu.l2cache.overall_misses 461 # number of overall misses 382system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits 383system.cpu.l2cache.overall_mshr_miss_latency 14364500 # number of overall MSHR miss cycles 384system.cpu.l2cache.overall_mshr_miss_rate 0.991398 # mshr miss rate for overall accesses 385system.cpu.l2cache.overall_mshr_misses 461 # number of overall MSHR misses 386system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 387system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 388system.cpu.l2cache.replacements 0 # number of replacements 389system.cpu.l2cache.sampled_refs 397 # Sample count of references to valid blocks. 390system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 391system.cpu.l2cache.tagsinuse 208.689672 # Cycle average of tags in use 392system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks. 393system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 394system.cpu.l2cache.writebacks 0 # number of writebacks 395system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads. 396system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. 397system.cpu.memDep0.insertedLoads 2783 # Number of loads inserted to the mem dependence unit. 398system.cpu.memDep0.insertedStores 1158 # Number of stores inserted to the mem dependence unit. 399system.cpu.numCycles 27764 # number of cpu cycles simulated 400system.cpu.rename.RENAME:BlockCycles 20 # Number of cycles rename is blocking 401system.cpu.rename.RENAME:CommittedMaps 3304 # Number of HB maps that are committed 402system.cpu.rename.RENAME:IdleCycles 10242 # Number of cycles rename is idle 403system.cpu.rename.RENAME:LSQFullEvents 16 # Number of times rename has blocked due to LSQ full 404system.cpu.rename.RENAME:RenameLookups 15583 # Number of register rename lookups that rename has made 405system.cpu.rename.RENAME:RenamedInsts 13384 # Number of instructions processed by rename 406system.cpu.rename.RENAME:RenamedOperands 8214 # Number of destination operands rename has renamed 407system.cpu.rename.RENAME:RunCycles 3446 # Number of cycles rename is running 408system.cpu.rename.RENAME:SquashCycles 1052 # Number of cycles rename is squashing 409system.cpu.rename.RENAME:UnblockCycles 29 # Number of cycles rename is unblocking 410system.cpu.rename.RENAME:UndoneMaps 4910 # Number of HB maps that are undone due to squashing 411system.cpu.rename.RENAME:serializeStallCycles 428 # count of cycles rename stalled for serializing inst 412system.cpu.rename.RENAME:serializingInsts 20 # count of serializing insts renamed 413system.cpu.rename.RENAME:skidInsts 125 # count of insts added to the skid buffer 414system.cpu.rename.RENAME:tempSerializingInsts 14 # count of temporary serializing insts renamed 415system.cpu.timesIdled 249 # Number of times that the entire CPU went into an idle state and unscheduled itself 416system.cpu.workload.PROG:num_syscalls 13 # Number of system calls 417 418---------- End Simulation Statistics ---------- 419